Preparation method of infrared detector and infrared detector

Abstract

The invention provides a preparation method of an infrared detector and the infrared detector, and belongs to the technical field of infrared detection. The preparation method comprises the following steps: sequentially depositing a first dielectric layer, a sacrificial layer, a second dielectric layer, a heat-sensitive material layer and a third dielectric layer on the surface of a readout circuit wafer; etching the heat-sensitive material layer and the third dielectric layer to form a resistor part; etching a first counter bore in the second dielectric layer and the sacrificial layer; depositing a fourth dielectric layer; etching the fourth dielectric layer and the first dielectric layer at the first counter bore to form a first contact hole which exposes the bottom electrode on the surface of the readout circuit wafer, and etching the fourth dielectric layer and the third dielectric layer at the resistor part to form a second contact hole; preparing an electrode structure connected with the bottom electrode and the heat-sensitive material layer; and removing the sacrificial layer to obtain the infrared detector. The preparation method is simple and high in production efficiency, and the prepared product is better in quality.

Description

Technical Field

[0001] The present application relates to the field of infrared detection technology, and in particular, to a method for manufacturing an infrared detector and an infrared detector. Background Art

[0002] The working principle of a non-cooled infrared detector is usually based on the absorption and thermal effect of infrared radiation. When the surface of the detector absorbs infrared radiation from an object, it causes a change in the temperature of the detector material. This temperature change is converted into an electrical signal, thereby achieving the detection of infrared radiation.

[0003] Figure 1 It is shown that the existing non-cooled infrared detector generally includes main structures such as a substrate 1', an optical resonator 2', anchor posts 3', support legs 4' and a thermistor 5'. As Figure 2 shown, in the prior art when manufacturing a non-cooled infrared detector, in step S201, an oxide layer 2 and a polyimide sacrificial layer 3 are sequentially deposited on a readout circuit wafer 1 (the polyimide sacrificial layer 3 needs to be cured at a high temperature), and then photolithography and etching are performed to fabricate a CON hole. In step S202, a silicon nitride layer 4, a thermistor material layer 5 and a silicon nitride layer 6 are sequentially deposited on the wafer of S201, and then photolithography and etching are performed to fabricate a VOX pattern. In step S203, a silicon nitride layer 7 is deposited on the wafer of S202, and then photolithography and etching are performed to fabricate a VA1 contact hole. In step S204, photolithography and etching are performed again on the wafer of S203 to fabricate a VA2 contact hole. In step S205, an electrode metal 8 is deposited on the wafer of S204, and then photolithography and etching are performed to fabricate a ME1 pattern. In step S206, a silicon nitride layer 9 is deposited on the wafer of S205, and then photolithography and etching are performed to fabricate a BRG support leg.

[0004] In the above manufacturing process, since the VOX pattern is fabricated after the CON hole, it is easy for thermosensitive material residues to remain on the sidewall of the CON hole. This residue increases the heat conduction of the anchor post 3', resulting in a reduction in the performance of the detector. The thermosensitive material residues on the sidewall of the CON hole can be removed by over-etching, but over-etching will increase the probability of damage to the silicon nitride on the sidewall of the CON hole, leading to device failure, and the additional removal step will increase the manufacturing process and reduce production efficiency. Summary of the Invention

[0005] One object of the present invention is to provide a method for manufacturing an infrared detector that is simple, has high production efficiency and can obtain better product quality.

[0006] Another object of the present invention is to propose a sacrificial layer etching technology to solve the problems of hard mask etching and easy occurrence of lateral corrosion in the prior art, and ensure that the morphology of the first sunken hole meets the requirements.

[0007] A further object of the present invention is to ensure the electrical performance of the product and further improve the production efficiency.

[0008] An embodiment of the present invention provides a method for manufacturing an infrared detector, including:

[0009] Depositing a first dielectric layer, a sacrificial layer, a second dielectric layer, a thermosensitive material layer, and a third dielectric layer on the surface of the readout circuit wafer in sequence;

[0010] Etching the thermosensitive material layer and the third dielectric layer to form a resistor portion;

[0011] Etching a first through-hole in the second dielectric layer and the sacrificial layer;

[0012] Depositing a fourth dielectric layer;

[0013] Etching the fourth dielectric layer and the first dielectric layer at the first through-hole to form a first contact hole, and the first contact hole exposes the bottom electrode on the surface of the readout circuit wafer;

[0014] Etching the fourth dielectric layer and the third dielectric layer at the resistor portion to form a second contact hole;

[0015] Preparing an electrode structure connecting the bottom electrode and the thermosensitive material layer;

[0016] Removing the sacrificial layer to obtain the infrared detector.

[0017] Further, the first contact hole and the second contact hole are formed by the same etching.

[0018] Further, before the step of depositing a first dielectric layer, a sacrificial layer, a second dielectric layer, a thermosensitive material layer, and a third dielectric layer on the surface of the readout circuit wafer in sequence, it further includes:

[0019] Setting and designing the thicknesses of the first dielectric layer, the third dielectric layer, and the fourth dielectric layer according to the requirements of synchronous etching.

[0020] Further, before the step of depositing a first dielectric layer, a sacrificial layer, a second dielectric layer, a thermosensitive material layer, and a third dielectric layer on the surface of the readout circuit wafer in sequence, it further includes:

[0021] Designing a photomask according to the target sizes of the first contact hole and the second contact hole;

[0022] Adjusting multiple groups of lithography parameters on the photomask and conducting tests to obtain lithography parameters that meet the requirements of synchronous etching.

[0023] Further, the lithography parameters include depth of focus and energy matrix.

[0024] Further, the step of etching the first through-hole in the second dielectric layer and the sacrificial layer includes:

[0025] Etching the second dielectric layer and the sacrificial layer step by step with different gas flow ratios to avoid lateral erosion of the first through-hole.

[0026] Further, the step of preparing the electrode structure connecting the bottom electrode and the thermosensitive material layer includes:

[0027] Depositing a conductive material layer;

[0028] Etching the region between the two first contact holes to form a spacer;

[0029] Depositing a fifth dielectric layer.

[0030] Further, after the step of depositing the fifth dielectric layer, it further includes:

[0031] Etching the fifth dielectric layer, the conductive material layer, the fourth dielectric layer and the second dielectric layer according to a preset pattern to form support legs between the etched regions.

[0032] In particular, an embodiment of the present invention further provides an infrared detector prepared by the preparation method according to any one of the above.

[0033] According to the first aspect of the present invention, a preparation method of an infrared detector is provided. The method first etches the resistance part and then etches the first through-hole, which can avoid the residue of the thermosensitive material in the first through-hole caused by etching the first through-hole first and then the resistance part in the prior art, and fundamentally avoids the problem of performance degradation of the infrared detector caused by the residue of the thermosensitive material at the anchor post. Compared with the prior art process method of reducing the residue by cleaning, the preparation method of this embodiment is simple, efficient and has better effects, which is beneficial to improving the production efficiency and quality of products.

[0034] Further, when the present invention etches the first through-hole, the second dielectric and the sacrificial layer are etched step by step, and different gas flow ratios are used in the two-step etching, so as to ensure that the first through-hole does not undergo lateral erosion and ensure that the morphology of the first through-hole meets the requirements.

[0035] According to the second aspect of the present invention, by pre-designing the thickness of the material layer where the first contact hole and the second contact hole are located or the lithography parameters of the first contact hole and the second contact hole, the first contact hole and the second contact hole are formed synchronously in one etching. This process of synchronously etching to form the first contact hole and the second contact hole can avoid the corrosion of the bottom electrode at the readout circuit wafer, ensure the electrical performance of the product, and avoid the glue residue in the first contact hole. In addition, this etching process only requires one etching and one cleaning, which can effectively improve the production efficiency. Description of the Drawings

[0036] Figure 1 is a schematic structural diagram of an infrared detector in the prior art;

[0037] Figure 2 is a schematic diagram of the preparation principle of an infrared detector in the prior art;

[0038] Figure 3 is a flowchart of a method for preparing an infrared detector according to an embodiment of the present invention;

[0039] Figure 4 is Figure 3 the schematic diagram of the preparation principle of the infrared detector in

[0040] Figure 5 is a flowchart of a method for preparing an infrared detector according to another embodiment of the present invention;

[0041] Reference numerals:

[0042] 10 - readout circuit wafer, 20 - first dielectric layer, 30 - sacrificial layer, 40 - second dielectric layer, 50 - thermosensitive material layer, 60 - third dielectric layer, 101 - resistor portion, 102 - first sinkhole, 70 - fourth dielectric layer, 103 - first contact hole, 104 - second contact hole, 80 - conductive material layer, 105 - spacer, 90 - fifth dielectric layer, 106 - support leg. Detailed embodiments

[0043] In order to make the above - mentioned objects, features and advantages of the present application more obvious and understandable, the following will describe the detailed embodiments of the present application in conjunction with the accompanying drawings. Many specific details are set forth in the following description in order to fully understand the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0044] It should be noted that when a component is referred to as being "fixed to" or "disposed on" another component, it can be directly on the other component or there may also be an intermediate component. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be an intermediate component at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in the specification of the present application are only for the purpose of illustration and do not represent the only implementation manner.

[0045] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0046] In this application, unless otherwise clearly specified and limited, the first feature may be in direct contact with the second feature or in indirect contact with the second feature through an intermediate medium when the first feature is "on" or "under" the second feature. Moreover, when the first feature is "above", "over" or "on top of" the second feature, the first feature may be directly above or obliquely above the second feature, or merely indicate that the horizontal height of the first feature is higher than that of the second feature. When the first feature is "below", "beneath" or "underneath" the second feature, the first feature may be directly below or obliquely below the second feature, or merely indicate that the horizontal height of the first feature is lower than that of the second feature.

[0047] Unless otherwise defined, all technical and scientific terms used in the specification of this application have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in the specification of this application includes any and all combinations of one or more of the related listed items.

[0048] As described in the background art section, during the existing preparation process of an infrared detector, in order to form an effective support structure for the thermistor 5', when preparing the support structure layer of the thermistor, after etching CON contact holes in the polyimide sacrificial layer 3, a whole layer of silicon nitride layer 4 is deposited. After the polyimide sacrificial layer 3 is finally removed, the silicon nitride layer 4 plays a role in pre-filling the CON holes, ensuring good coverage of the electrode metal 8 and avoiding breakage of the electrode metal 8 at the CON holes. In addition, the silicon nitride layer 4 is also the basic support structure of the electrode metal 8, so it is usually continuously arranged to form Figure 1 a strong anchor post 3' support structure in the middle, and is also the basic support post of the thermistor 5'. In the area of the anchor post 3', local etching is only carried out at the necessary electrode connection VA1. Therefore, when forming the anchor post 3' by deposition in the prior art, a continuous silicon nitride layer 4 is required. This silicon nitride layer 4 serves as both the direct bottom support cantilever structure of the thermistor 5' and the two legs (i.e., the anchor posts 3') of the bottom support cantilever structure. This structure has become a conventional support structure in this field. However, this structure inevitably brings the problem of residual thermosensitive material on the sidewalls of the contact holes.

[0049] The inventors of the present application have broken through the conventional understanding of the continuity of the support structure in the prior art. Instead of using the method of etching to remove the thermosensitive material to solve the residue problem, they directly avoid the residue of the thermosensitive material by adjusting the process steps.

[0050] Figure 3 FIG. is a flowchart of a method for manufacturing an infrared detector according to an embodiment of the present invention. Figure 4 is Figure 3 the schematic diagram of the preparation principle of the infrared detector in. As Figure 3 and Figure 4 shown, in one embodiment, the method for manufacturing an infrared detector includes:

[0051] Step S100, sequentially depositing a first dielectric layer 20, a sacrificial layer 30, a second dielectric layer 40, a thermosensitive material layer 50, and a third dielectric layer 60 on the surface of the readout circuit wafer 10;

[0052] Step S200, etching the thermosensitive material layer 50 and the third dielectric layer 60 to form a resistance portion 101;

[0053] Step S300, etching a first sink hole 102 in the second dielectric layer 40 and the sacrificial layer 30;

[0054] Step S400, depositing a fourth dielectric layer 70;

[0055] Step S500, etching the fourth dielectric layer 70 and the first dielectric layer 20 at the first sink hole 102 to form a first contact hole 103, and the first contact hole 103 exposes the bottom electrode on the surface of the readout circuit wafer 10;

[0056] Step S600, etching the fourth dielectric layer 70 and the third dielectric layer 60 at the resistance portion 101 to form a second contact hole 104;

[0057] Step S700, preparing an electrode structure connecting the bottom electrode and the thermosensitive material layer 50;

[0058] Step S800, removing the sacrificial layer 30 to obtain an infrared detector.

[0059] The steps of preparing the electrode structure in Step S700 generally include the following steps:

[0060] Depositing a conductive material layer 80;

[0061] Etching the region between the two first contact holes 103 to form a spacer 105;

[0062] Depositing a fifth dielectric layer 90;

[0063] Etch the fifth dielectric layer 90, the conductive material layer 80, the fourth dielectric layer 70, and the second dielectric layer 40 according to a preset pattern to form support legs 106 between the etched areas.

[0064] In step S100, the first dielectric layer 20 is used to provide electrical isolation, and can be made of silicon nitride, silicon oxide, or a silicon nitride / silicon oxide composite material, which is not limited here. The sacrificial layer 30 is used to form the final hole structure, and the material of the sacrificial layer 30 is polyimide. The second dielectric layer 40 provides basic support and isolation for the thermosensitive material layer 50, and the material of the second dielectric layer 40 can be silicon nitride, silicon oxide, etc., which is not limited here. The thermosensitive material layer 50 is the sensing component of the infrared detector, and generates different resistance changes under different infrared radiations. The material of the thermosensitive material layer 50 can be vanadium oxide, germanium, amorphous silicon, etc., which is not limited here. The third dielectric layer 60 is the protective layer of the thermosensitive material layer 50, used to prevent external contamination or mechanical damage, and the material of the third dielectric layer 60 can be silicon nitride, silicon oxide, etc., which is not limited here.

[0065] The etching in step S200 stops at the second dielectric layer 40.

[0066] In step S300, etching is performed at the second dielectric layer 40 and the sacrificial layer 30 on both sides of the resistance portion 101, and the etching stops at the first dielectric layer 20, so that two first sink holes 102 are formed on both sides of the resistance portion 101.

[0067] Step S400 is a deposition performed on the entire surface of the product formed in step S300. The fourth dielectric layer 70 is used to provide insulation for the conductive material layer 80, so that the conductive material layer 80 has good stability. The material of the fourth dielectric layer 70 can be silicon nitride, silicon dioxide, etc., which is not limited here.

[0068] The etching in step S500 stops at the readout circuit wafer 10. The area of the first sink hole 102 is the area where the bottom electrode of the readout circuit wafer 10 is located. After etching to form the first contact hole 103, the bottom electrode is exposed within the first contact hole 103.

[0069] The etching in step S600 stops at the surface of the thermosensitive material layer 50.

[0070] Steps S500 and S600 in this embodiment can be performed step by step or synchronously, which is not limited here.

[0071] The conductive material layer 80 in step S700 is used to form a conductive path to provide electrical connection. The material of the conductive material layer 80 can be common conductive materials such as aluminum, gold, copper, molybdenum or titanium, etc., which are not limited herein. The area between the two first contact holes 103 is etched to disconnect the conductive material layer 80. The fifth dielectric layer 90 is deposited on the surface of the entire product to form a protective layer. The material of the fifth dielectric layer 90 can be materials such as silicon dioxide, silicon nitride, etc., which are not limited herein.

[0072] In step S800, common solvents or etching can be used to release the sacrificial layer 30 to form a suspended structure, thereby manufacturing an infrared detector. This process step is a conventional technical means in the art and will not be elaborated herein.

[0073] The method for manufacturing the infrared detector of this embodiment first etches the resistor part 101 and then etches the first sink hole 102, which can avoid the residue of the thermosensitive material in the first sink hole 102 caused by etching the first sink hole 102 first and then the resistor part 101 in the prior art, and fundamentally avoids the problem of performance degradation of the infrared detector caused by the residue of the thermosensitive material at the anchor post. Compared with the prior art process method of reducing the residue by over-etching, the manufacturing method of this embodiment is simple, efficient and has better effects, which is beneficial to improving the production efficiency and quality of the product.

[0074] The infrared detector prepared by the above embodiment has no obvious change in performance compared with the detector in the prior art. Structurally, it only lacks the second dielectric layer 40 at the first sink hole 102. Through the use performance of the actual product, it is found that the reduction of the second dielectric layer 40 at the first sink hole 102 does not affect the support effect. This is because the bonding force between the subsequent fourth dielectric layer 70 and the second dielectric layer 40 in the area other than the first sink hole 102 enables the entire structure to still have a good support effect and meet the requirement of supporting the resistor part 101. This new support structure formed by the cooperation of the fourth dielectric layer 70 and the second dielectric layer 40 disconnected at the first sink hole 102 also provides a basis for the implementation of the new manufacturing method of this application. Here, the fourth dielectric layer 70 also provides a basis for the effective deposition of the conductive material layer 80.

[0075] Figure 5 It is a flowchart of a method for manufacturing an infrared detector according to another embodiment of the present invention. As Figure 5 shown, in one embodiment, step S300 includes:

[0076] Step S310, etching the second dielectric layer 40 and the sacrificial layer 30 step by step with different gas flow ratios to avoid lateral erosion of the first sink hole 102.

[0077] In one embodiment, the material of the second dielectric layer 40 is silicon nitride, and the material of the sacrificial layer 30 is polyimide. When etching the first blind via 102, O2 and CF4 gases are used for etching. When etching the second dielectric layer 40, the flow rate ratio of O2 to CF4 is any value from 1:12 to 3:12. For example, the flow rate ratio of O2 to CF4 is 1:12, 2:12, or 3:12, or any other value from 1:12 to 3:12, which is not limited herein. When etching the sacrificial layer 30, the flow rate ratio of O2 to CF4 is any value from 9:12 to 11:12. For example, the flow rate ratio of O2 to CF4 is 9:12, 10:12, or 11:12, or any other value from 9:12 to 11:12, which is not limited herein.

[0078] In this embodiment, when etching the first blind via 102, the second dielectric and the sacrificial layer 30 are etched step by step, and different gas flow rate ratios are used in the two-step etching, so as to ensure that the first blind via 102 does not undergo lateral etching and the morphology of the first blind via 102 meets the requirements.

[0079] Further, in the prior art, the first contact hole 103 and the second contact hole 104 are formed step by step through two etching processes. The reason is that in order to play a better supporting role, the first dielectric layer 20 and the third dielectric layer 60 are located at different layer positions, and their functions are different, so their thicknesses are not necessarily the same. In addition, since the first contact hole 103 is formed in the first blind via 102 (generally with a depth of 2000 ± 200 nm), and the second contact hole 104 is formed on the product surface, after photoresist coating, the wafer will be planarized by the photoresist. Therefore, the exposure foci of the first contact hole 103 and the second contact hole 104 are not on the same horizontal plane, and it is difficult to perform synchronous lithography on the first contact hole 103 and the second contact hole 104. Thus, the prior art uses two-step lithography to fabricate the first contact hole 103 and the second contact hole 104.

[0080] However, the etching method of separately exposing, developing, etching, and removing the photoresist for the first contact hole 103 and the second contact hole 104 using two photomask levels will, on the one hand, reduce the production efficiency. On the other hand, during the step-by-step etching, when etching the second contact hole 104, the first contact hole 103 is filled with photoresist. After etching the second contact hole 104, the cleaning requires removing the photoresist in the first contact hole 103 and the polymer in the second contact hole 104 simultaneously. This method requires cleaning the first contact hole 103 twice and also increases the risk of photoresist residue in the first contact hole 103. Moreover, when cleaning after etching the second contact hole 104, the first contact hole 103 is exposed to the cleaning solution, which increases the risk of corrosion of the bottom electrode at the bottom of the first contact hole 103, thus affecting the electrical performance of the readout circuit and the electrode structure. Based on these defects, the present application also provides the following technical solutions.

[0081] In one embodiment, the first contact hole 103 and the second contact hole 104 are formed by the same etching process, that is, step S600 and step S700 are executed simultaneously. Forming the first contact hole 103 and the second contact hole 104 in the same etching process can be achieved by adjusting the thickness of the material in the etching area and the etching condition parameters (such as gas flow rate, etching time, and etching) to complete the etching of the two contact holes in one etching process. For example, by precisely controlling the etching conditions, the etching rates of the first material on the bottom surface of the counterbore and the surface of the structure can be made different, so as to achieve the simultaneous etching of the two surfaces. Or by precisely controlling the etching time and gas flow rate, and using the depth control ability of plasma etching, the bottom surface of the counterbore and the surface of the structure are etched step by step. Low-energy etching can be used to preferentially etch the bottom surface of the counterbore to ensure that the depths of both are the same.

[0082] In a further embodiment, before step S100, there is also a design step S50 for achieving the simultaneous formation of the first contact hole 103 and the second contact hole 104 in one etching process.

[0083] In one embodiment, the design step includes setting the thicknesses of the first dielectric layer 20, the third dielectric layer 60, and the fourth dielectric layer 70 according to the requirements of synchronous etching.

[0084] In this embodiment, the etching conditions are not changed, that is, the first contact hole 103 and the second contact hole 104 use the same etching conditions. By experimental or simulation methods, the thicknesses of the first dielectric layer 20, the third dielectric layer 60, and the fourth dielectric layer 70 are changed, and with the goal of synchronous etching completion, the appropriate thicknesses of the first dielectric layer 20, the third dielectric layer 60, and the fourth dielectric layer 70 can be obtained.

[0085] In one embodiment, the first dielectric layer 20 is silicon oxide, the third dielectric layer 60 is silicon nitride, and the fourth dielectric layer 70 is silicon nitride. The thickness of the first dielectric layer 20 is 50 ± 5 nm, the thickness of the third dielectric layer 60 is 60 ± 6 nm, and the thickness of the fourth dielectric layer 70 is 80 ± 8 nm. Generally, the etching rate of silicon nitride is faster than that of silicon oxide, so the thickness of the third dielectric layer 60 is slightly greater than that of the first dielectric layer 20. This embodiment can achieve the synchronous etching of the first contact hole 103 and the second contact hole 104 under the same etching conditions.

[0086] In another embodiment, the design step includes:

[0087] Designing a photomask according to the target sizes of the first contact hole 103 and the second contact hole 104;

[0088] Adjusting multiple groups of lithography parameters on the photomask and conducting tests to obtain lithography parameters that meet the requirements of synchronous etching.

[0089] The lithography parameters in this embodiment include depth of focus and energy matrix.

[0090] Specifically, taking the depth of focus and the energy matrix as adjustment variables, exposure and development are carried out under different lithography parameters, and the line widths and topographies of the first contact hole 103 and the second contact hole 104 under different lithography parameters are collected. The lithography parameters are continuously adjusted until the line widths and topographies of the first contact hole 103 and the second contact hole 104 both meet the design requirements, and a photomask is fabricated according to the lithography parameters that meet the requirements for use in subsequent preparation processes.

[0091] In this embodiment, by pre-designing the thickness of the material layer where the first contact hole 103 and the second contact hole 104 are located or the lithography parameters of the first contact hole 103 and the second contact hole 104, the first contact hole 103 and the second contact hole 104 are synchronously formed in one etching. This process of synchronously etching to form the first contact hole 103 and the second contact hole 104 can avoid the corrosion of the bottom electrode at the readout circuit wafer 10, ensure the electrical performance of the product, and avoid the glue residue in the first contact hole 103. In addition, this etching process only requires one etching and one cleaning, which can effectively improve the production efficiency.

[0092] An embodiment of the present application further provides an infrared detector prepared by the preparation method according to the above embodiment.

[0093] The above-described embodiments merely represent several implementation manners of the present invention, and the description thereof is relatively specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

Claims

1. A method for preparing an infrared detector, characterized in that: include: Depositing a first dielectric layer, a sacrificial layer, a second dielectric layer, a thermosensitive material layer and a third dielectric layer in sequence on the surface of the readout circuit wafer; Etching the thermosensitive material layer and the third dielectric layer to form a resistor portion; Etching a first countersunk hole in the second dielectric layer and the sacrificial layer; depositing a fourth dielectric layer; Etching the fourth dielectric layer and the first dielectric layer at the first countersunk hole to form a first contact hole, wherein the first contact hole exposes a bottom electrode on the surface of the readout circuit wafer; Etching the fourth dielectric layer and the third dielectric layer at the resistor portion to form a second contact hole; preparing an electrode structure connecting the bottom electrode and the thermosensitive material layer; The sacrificial layer is removed to obtain the infrared detector.

2. The method for preparing an infrared detector according to claim 1, characterized in that: The first contact hole and the second contact hole are formed by etching at the same time.

3. The method for preparing an infrared detector according to claim 2, characterized in that: Before the step of sequentially depositing a first dielectric layer, a sacrificial layer, a second dielectric layer, a heat-sensitive material layer and a third dielectric layer on the surface of the readout circuit wafer, the step further includes: The thicknesses of the first dielectric layer, the third dielectric layer and the fourth dielectric layer are designed and set according to the synchronous etching requirements.

4. The method for preparing an infrared detector according to claim 2, characterized in that: Before the step of sequentially depositing a first dielectric layer, a sacrificial layer, a second dielectric layer, a heat-sensitive material layer and a third dielectric layer on the surface of the readout circuit wafer, the step further includes: designing a photomask according to target sizes of the first contact hole and the second contact hole; A plurality of groups of photolithography parameters on the photomask are adjusted and tested to obtain photolithography parameters that meet the requirements of synchronous etching.

5. The method for preparing an infrared detector according to claim 4, characterized in that: The lithography parameters include focal depth and energy matrix.

6. The method for preparing an infrared detector according to any one of claims 1 to 5, characterized in that: The step of etching a first countersunk hole in the second dielectric layer and the sacrificial layer comprises: The second dielectric layer and the sacrificial layer are etched stepwise with different gas flow ratios to avoid lateral erosion of the first countersunk hole.

7. The method for preparing an infrared detector according to claim 1, characterized in that: The step of preparing an electrode structure connecting the bottom electrode and the thermosensitive material layer comprises: depositing a layer of conductive material; Etching a region between the two first contact holes to form a spacer region; A fifth dielectric layer is deposited.

8. The method for preparing an infrared detector according to claim 7, characterized in that: The step of depositing the fifth dielectric layer further includes: The fifth dielectric layer, the conductive material layer, the fourth dielectric layer and the second dielectric layer are etched according to a preset pattern to form support legs between etched areas.

9. An infrared detector prepared according to the preparation method according to any one of claims 1 to 8.

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