Open circuit detection circuit

Abstract

The technical scheme of the invention discloses an open circuit detection circuit, and relates to the technical field of circuit protection, the open circuit detection circuit comprises a power driving chip, a detection circuit and a control chip; the detection circuit is connected with the power driving chip, a load and the control chip, and the detection circuit is used for carrying out open-circuit fault diagnosis on the power driving chip and the load and transmitting a diagnosis result to the control chip; and the control chip is used for sending out a fault prompt when receiving the diagnosis result, and prompting a user that the load is open-circuited. And the detection circuit monitors whether the load is open-circuited and transmits a diagnosis result to the control chip, and the control chip sends out a fault prompt. According to the open circuit detection circuit, discrete devices are adopted to build the detection circuit, the detection circuit judges whether the load is in an open circuit or not by detecting the threshold values of the voltage and the current of the power driving chip, and the open circuit detection circuit has the advantages of being low in cost and easy to replace.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit protection, and particularly to an open - circuit detection circuit. Background Art

[0002] To meet the control of electrical appliances in daily life, when an electrical appliance detects a switch demand, the power drive module in the electrical appliance drives or shuts off the load to realize the normal use of the electrical appliance. Due to possible open - circuit faults such as poor soldering, loose connectors, and disconnected wire harnesses, the electrical appliance cannot work properly. The detection circuit is mainly used to monitor this fault to facilitate users to identify and solve the problem. With the rapid development of integrated circuits, the detection circuit of the existing power drive module is mainly integrated in the power drive chip, and open - circuit fault diagnosis is carried out according to the current detected by the current output detection pin (IS). The existing scheme has a high integration degree and a small occupied area. However, if it is damaged due to problems such as poor soldering and short - circuit, the whole chip needs to be replaced during maintenance, resulting in a high maintenance cost. Summary of the Invention

[0003] The main object of the present invention is to propose an open - circuit detection circuit, aiming to solve the technical problem of high maintenance cost caused by the need to replace the whole chip during the maintenance of the detection circuit of the power drive module.

[0004] To achieve the above object, the open - circuit detection circuit proposed by the present invention includes: a power drive chip, a detection circuit, and a control chip;

[0005] The detection circuit is connected to the power drive chip, the load, and the control chip;

[0006] The detection circuit is used to perform open - circuit fault diagnosis on the power drive chip and the load, and transmit the diagnosis result to the control chip;

[0007] The control chip is used to issue a fault prompt when receiving the diagnosis result to prompt the user that the load is open - circuited.

[0008] In one embodiment, the detection circuit includes: an on - detection circuit and an off - detection circuit;

[0009] The on - detection circuit is respectively connected to the power drive chip, the load, and the control chip, and the off - detection circuit is respectively connected to the power drive chip, the load, and the control chip;

[0010] The on - detection circuit is used to detect the current of the load to obtain a diagnostic current when the power drive chip is in the on state, and transmit the diagnostic current to the control chip;

[0011] The shutdown detection circuit is used to detect the output voltage of the load when the power driving chip is in the shutdown state, compare the output voltage with a threshold voltage, and output the comparison result to the control chip;

[0012] The control chip is further configured to determine whether the load is in an open circuit state according to the diagnostic current and the comparison result.

[0013] In one embodiment, the shutdown detection circuit includes: a collection circuit and a comparison circuit;

[0014] The collection circuit is respectively connected to the power driving chip, the load and the comparison circuit, and the comparison circuit is connected to the collection circuit and the control chip;

[0015] The collection circuit is configured to detect the output voltage of the load when the power driving chip is in the shutdown state and transmit it to the comparison circuit;

[0016] The comparison circuit is configured to compare the output voltage with the threshold voltage and output the comparison result to the control chip.

[0017] In one embodiment, the shutdown detection circuit further includes: a bias circuit;

[0018] The bias circuit is connected to the comparison circuit;

[0019] The bias circuit is configured to provide a bias voltage for the comparison circuit.

[0020] In one embodiment, the shutdown detection circuit further includes: a voltage stabilizing circuit;

[0021] The voltage stabilizing circuit is connected to the bias circuit and the comparison circuit;

[0022] The voltage stabilizing circuit is configured to stabilize the comparison circuit by charging and discharging.

[0023] In one embodiment, the startup detection circuit includes: a first MOS transistor, a second MOS transistor and a first diode;

[0024] The gate of the first MOS transistor is connected to the power driving chip and the gate of the second MOS transistor, the drain of the first MOS transistor is connected to the drain of the second MOS transistor and the cathode of the first diode, and the source of the first MOS transistor is connected to the source of the second MOS transistor, the load and the anode of the first diode.

[0025] In one embodiment, the acquisition circuit includes: a third MOS transistor and a second diode; the gate of the third MOS transistor is connected to the power driving chip, the drain of the third MOS transistor is connected to the cathode of the second diode, and the source of the third MOS transistor is connected to the load and the comparison circuit.

[0026] In one embodiment, the comparison circuit includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a first inverter, and a second inverter;

[0027] The source of the fourth MOS transistor is connected to the load and the acquisition circuit, the gate of the fourth MOS transistor is grounded, the drain of the fourth MOS transistor is connected to the voltage stabilizing circuit, the bias circuit, and the gate of the fifth MOS transistor, the source of the fifth MOS transistor is grounded, the drain of the fifth MOS transistor is connected to the source of the sixth MOS transistor and the input terminal of the first inverter, the gate of the sixth MOS transistor is connected to the bias circuit, the source of the sixth MOS transistor is connected to a current source, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the control chip.

[0028] In one embodiment, the bias circuit includes: a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, and a tenth MOS transistor;

[0029] The source of the seventh MOS transistor is connected to the current source, the gate of the seventh MOS transistor is connected to the gate of the sixth MOS transistor, the drain of the seventh MOS transistor is connected to the drain of the eighth MOS transistor, the source of the eighth MOS transistor is grounded, the gate of the eighth MOS transistor is connected to the gate of the ninth MOS transistor and the gate of the tenth MOS transistor, the sources of the ninth MOS transistor and the tenth MOS transistor are grounded, the drain of the ninth MOS transistor is connected to the current source, and the drain of the tenth MOS transistor is connected to the voltage stabilizing circuit, the drain of the fourth MOS transistor, and the gate of the fifth MOS transistor.

[0030] In one embodiment, the voltage stabilizing circuit includes: an eleventh MOS transistor and a twelfth MOS transistor;

[0031] The drain of the eleventh MOS transistor is connected to the drain of the tenth MOS transistor, the drain of the fourth MOS transistor, and the gate of the fifth MOS transistor, the gate of the eleventh MOS transistor is connected to the output terminal of the second inverter and the control chip, the source of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor, the source of the twelfth MOS transistor is grounded, and the gate of the twelfth MOS transistor is connected to the gate of the eighth MOS transistor, the gate of the ninth MOS transistor, and the gate of the tenth MOS transistor.

[0032] The technical solution of the present invention discloses an open - circuit detection circuit, and the open - circuit detection circuit includes: a power drive chip, a detection circuit, and a control chip; the detection circuit is connected to the power drive chip, a load, and the control chip, and the detection circuit is configured to perform open - circuit fault diagnosis on the power drive chip and the load, and transmit the diagnosis result to the control chip; the control chip is configured to issue a fault prompt when receiving the diagnosis result to prompt the user that the load is open - circuited. The detection circuit monitors whether the load is open - circuited and transmits the diagnosis result to the control chip, and the control chip issues a fault prompt. The present invention uses discrete devices to build the detection circuit, and the detection circuit determines whether the load is open - circuited by detecting the voltage and current thresholds of the power drive chip. The detection circuit of the present application has the advantages of low cost and easy replacement. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0034] Figure 1 It is a schematic block diagram of the first embodiment of the open - circuit detection circuit provided by the present invention;

[0035] Figure 2 It is another schematic block diagram of the first embodiment of the open - circuit detection circuit provided by the present invention;

[0036] Figure 3 It is a schematic circuit diagram of the second embodiment of the open - circuit detection circuit provided by the present invention;

[0037] Figure 4 It is a schematic circuit diagram of the third embodiment of the open - circuit detection circuit provided by the present invention;

[0038] Figure 5 It is another schematic circuit diagram of the third embodiment of the open - circuit detection circuit provided by the present invention.

[0039] Explanation of the reference numerals in the drawings:

[0040] Label Name Label Name 100 Detection circuit 200 Power driver chip 300 Control chip I0 Current source Q1 to Q12 First to twelfth MOS transistors V1 to V2 First to second inverters D1 to D2 First to second diodes 400 Load

[0041] The realization of the object of the present invention, functional features, and advantages will be further described in conjunction with the embodiments and with reference to the drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0043] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present invention, the directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0044] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In addition, if "and / or" or "and / or" appears throughout the text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or the solution where A and B are satisfied simultaneously. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0045] To meet the control of household appliances in daily life, when the household appliance detects a switch demand, the power drive module in the household appliance drives or shuts off the load to realize the normal use of the household appliance. Due to possible open circuit faults such as poor soldering, loose connectors, and disconnected wire harnesses, the household appliance cannot work properly. The detection circuit is mainly used to monitor this fault to facilitate the user to identify and solve the problem. With the rapid development of integrated circuits, the detection circuits of existing power drive modules are mainly integrated in power drive chips (such as Figure 2 ), and open circuit fault diagnosis is performed according to the current detected by the current output detection pin (IS). The existing solutions have high integration and small occupied area. If they are damaged due to problems such as poor soldering and short circuit, the entire chip needs to be replaced during maintenance, resulting in high maintenance costs.

[0046] The present invention proposes an open circuit detection circuit. Please refer to Figure 1 , Figure 1 which is a module schematic diagram of the first embodiment of the open circuit detection circuit proposed by the present invention.

[0047] In this embodiment, the open - circuit detection circuit includes: a power - driving chip 200, a detection circuit 100, and a control - type chip 300; the detection circuit 100 is connected to the power - driving chip 200, a load 400, and the control - type chip 300. The detection circuit is used to perform open - circuit fault diagnosis on the power - driving chip and the load, and transmit the diagnosis result to the control - type chip; the control - type chip is used to issue a fault prompt when receiving the diagnosis result, prompting the user that the load is open - circuited.

[0048] It should be noted that when the power - driving chip 200 drives the load 400, the load may be damaged or have a dry joint, which may cause an open - circuit fault in the entire system. Therefore, a detection circuit needs to be added to the circuit. The detection circuit can generate corresponding diagnostic current or voltage to the control - type chip 300 according to the load connection status in a timely manner, and the control - type chip 300 prompts the user that the external load has an open - circuit fault.

[0049] It can be understood that the control - type chip 300 can also detect whether the detection circuit 100 fails. If a device in the detection circuit 100 is damaged, the control - type chip 300 prompts the user to replace the detection circuit. The detection circuit of the present application is composed of MOS transistor inverters, and the replacement cost of the detection circuit is low.

[0050] Specifically, the detection circuit monitors whether the load is open - circuited and reports the fault to the control - type chip. The control - type chip issues a fault code, and the user can clearly understand the fault problem after seeing the fault code.

[0051] In this embodiment, the detection circuit monitors whether the load is open - circuited and transmits the diagnosis result to the control - type chip, and the control - type chip issues a fault prompt. The present invention uses discrete devices to isolate the open - circuit detection from the power - driving chip 200, and builds a detection circuit 100. The detection circuit determines whether the load is open - circuited by detecting the voltage or current threshold of the power - driving chip. The detection circuit of the present application has the advantages of low cost and easy replacement.

[0052] As Figure 3 shown, it is the circuit diagram of the second embodiment of the open - circuit detection circuit proposed in the embodiment of the present invention.

[0053] Based on the above - mentioned first embodiment, the second embodiment of the open - circuit detection circuit of the present invention is proposed.

[0054] The detection circuit includes: an on - detection circuit and an off - detection circuit; the on - detection circuit is respectively connected to the power drive chip, the load, and the control chip, and the off - detection circuit is respectively connected to the power drive chip, the load, and the control chip; the on - detection circuit is used to detect the current of the load to obtain a diagnostic current when the power drive chip is in the on state, and transmit the diagnostic current to the control chip; the off - detection circuit is used to detect the output voltage of the load when the power drive chip is in the off state, compare the output voltage with a threshold voltage, and output a comparison result to the control chip; the control chip is further used to determine whether the load is in an open - circuit state according to the diagnostic current and the comparison result.

[0055] It can be understood that when the power drive chip is turned on and off, there are two corresponding open - circuit protection methods respectively.

[0056] It should be noted that when the power drive chip is turned on, for the on - detection circuit, the load current is sampled to obtain a diagnostic current. The on - detection circuit transmits the diagnostic current to the control chip, and the control chip determines whether the load is in an open - circuit state according to the diagnostic current.

[0057] Specifically, when the power drive chip is turned off, for the off - detection circuit, it is impossible to sample the diagnostic current of the load current because no matter whether the external load is open - circuited, the diagnostic current is 0A. Therefore, it is not possible to use the change of the diagnostic current to complete the open - circuit detection as when the power drive chip is in the on state. Instead, it is necessary to judge the open - circuit situation of the load by detecting the magnitude of the output voltage of the load. The off - detection circuit transmits the voltage comparison result to the control chip, and the control chip determines whether the load is in an open - circuit state according to the comparison result.

[0058] The on - detection circuit includes: a first MOS transistor Q1, a second MOS transistor Q2, and a first diode D1; the gate of the first MOS transistor is connected to the power drive chip and the gate of the second MOS transistor, the drain of the first MOS transistor is connected to the drain of the second MOS transistor and the cathode of the first diode, and the source of the first MOS transistor is connected to the source of the second MOS transistor, the load, and the anode of the first diode.

[0059] It can be understood that when the power drive chip is in the on state, the schematic diagram of open - circuit detection is as Figure 3 shown. By adding a first MOS transistor M1 for current sampling at the connection of the power drive chip, the load current can be sampled to obtain a corresponding diagnostic current. When the load is normally connected, the diagnostic current I detected by the control chip IS is the same as the load current IL Is in a direct proportional relationship, that is:

[0060] I IS = I L / K ILS ;

[0061] Wherein, the current sampling ratio coefficient K ILS Is affected by temperature, power supply voltage, load current, etc., and a more accurate ratio coefficient K can be obtained through circuit calibration ILS .

[0062] It can be understood that Q1 and Q2 are NMOS transistors. When the power driving chip is turned on, both Q1 and Q2 are turned on, and the control chip detects the diagnostic current of the load.

[0063] In this embodiment, when the power driving chip is turned on, the enabling detection circuit samples the load current to obtain the diagnostic current. The enabling detection circuit transmits the diagnostic current to the control chip, and the control chip determines whether the load is in an open circuit state according to the diagnostic current; when the power driving chip is turned off, the disabling detection circuit compares the output voltage of the load with the threshold voltage to judge the open circuit situation of the load. The disabling detection circuit transmits the voltage comparison result to the control chip, and the control chip determines whether the load is in an open circuit state according to the comparison result.

[0064] Such as Figure 4 And Figure 5 The disabling detection circuit shown is the circuit diagram of the third embodiment of the open circuit detection circuit proposed by the embodiment of the present invention.

[0065] Based on the above first embodiment and / or second embodiment, the third embodiment of the open circuit detection circuit of the present invention is proposed.

[0066] The disabling detection circuit includes: an acquisition circuit and a comparison circuit; the acquisition circuit is respectively connected to the power driving chip, the load and the comparison circuit, and the comparison circuit is connected to the acquisition circuit and the control chip; the acquisition circuit is used to detect the output voltage of the load and transmit it to the comparison circuit when the power driving chip is in the off state; the comparison circuit is used to compare the output voltage with the threshold voltage and output the comparison result to the control chip.

[0067] It can be understood that the disabling detection circuit judges the open circuit situation of the load by detecting the magnitude of the output voltage of the load, and the detection method is as Figure 4As shown, the acquisition circuit is connected to the load and is used to acquire the output voltage of the load. The comparison circuit is connected to the acquisition circuit and the control chip. The comparison circuit compares the output voltage of the load with the threshold voltage and transmits the comparison result to the control chip, and the control chip determines whether the load is open-circuited.

[0068] The acquisition circuit includes: a third MOS transistor Q1 and a second diode D2; the gate of the third MOS transistor is connected to the power driver chip, the drain of the third MOS transistor is connected to the cathode of the second diode, and the source of the third MOS transistor is connected to the load and the comparison circuit.

[0069] It should be noted that when the load is normally connected, the load branch is grounded, so the value of the output voltage Vout is relatively low; when the load is open-circuited, the output terminal Vout of the load is floating, so the value of the load output voltage Vout is relatively high. According to the above principle, when the output voltage Vout is greater than a certain threshold, it is determined that the load has an abnormal open-circuit condition. That is, the open-circuit condition of the load in the off state of the power driver chip is:

[0070] V OUT >V S -V DS(OLOFF) ;

[0071] where Vs is the current source voltage and V DS(OLOFF) is the threshold voltage.

[0072] It can be understood that when the power driver chip is turned off, M3 is cut off, the current of the load is 0, the sampling circuit detects the output voltage Vout of the load, and transmits the output voltage to the comparison circuit.

[0073] The comparison circuit includes: a fourth MOS transistor Q4, a fifth MOS transistor Q5, a sixth MOS transistor Q6, a first inverter V1 and a second inverter V2; the source of the fourth MOS transistor Q4 is connected to the load and the acquisition circuit, the gate of the fourth MOS transistor Q4 is grounded, the drain of the fourth MOS transistor Q4 is connected to the voltage stabilization circuit, the bias circuit and the gate of the fifth MOS transistor Q5, the source of the fifth MOS transistor Q5 is grounded, the drain of the fifth MOS transistor Q5 is connected to the source of the sixth MOS transistor Q6 and the input end of the first inverter, the gate of the sixth MOS transistor Q6 is connected to the bias circuit, the source of the sixth MOS transistor Q6 is connected to the current source, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is connected to the control chip.

[0074] It can be understood that as Figure 5As shown, connect Vout to a comparison circuit for magnitude judgment, and output the comparison result Z to a control chip. Under normal circumstances where the load is properly connected, Z is at a high level. The NMOS transistor Q4, PMOS transistors Q5 and Q6 are responsible for judging whether the magnitude of the output voltage Vout is within the specified range, and the threshold voltage V DS(OLOFF) can be adjusted by adjusting their sizes.

[0075] It should be noted that when the load is properly connected, the difference between the output voltage Vout and the ground voltage GND is small and not sufficient to turn on the PMOS transistor Q4. Therefore, the transistors Q10 to Q12 are in an unpowered state, the voltage at point A is approximately equal to 0, then the NMOS transistor Q5 is turned off, the voltage at point B is pulled up to a high level, and after being buffered by two inverters V1 and V2, the output open-circuit detection signal Z is also at a high level. When the control chip receives a high level, it determines that the load is operating normally. The function of an inverter is to invert the input signal, that is, to implement the logical NOT function. Using two inverters in series serves to isolate and protect the control chip.

[0076] Specifically, when the load is open-circuited, the output voltage Vout is high, that is, it meets the load open-circuit condition under the off state of the power drive chip. The relatively high output voltage Vout turns on the PMOS transistor Q4, and the voltage at point A is approximately equal to the output voltage of the power transistor Vout. At this time, the magnitude of Vout determines whether the NMOS transistor Q5 is turned on. In the design of the comparison circuit, the conduction threshold voltage V TH8 of the NMOS transistor Q5 is made less than the threshold voltage V S -V DS(OLOFF) of the output voltage Vout to ensure that when the PMOS transistor Q4 is turned on, the NMOS transistor Q5 must also be turned on. At this time, the voltage at point A exceeds the conduction voltage of the NMOS transistor Q5, the NMOS transistor Q5 is turned on, the voltage at point B is correspondingly pulled down to a low level, and after passing through two inverters V1 and V2, the output open-circuit detection signal Z is at a low level. When the control chip receives a comparison result of low level, it determines that the load is open-circuited. Therefore, when the load is open-circuited, the voltage at point A stabilizes at a value slightly smaller than the output voltage VOUT.

[0077] The shutdown detection circuit further includes: a bias circuit; the bias circuit is connected to the comparison circuit; the bias circuit is used to provide a bias voltage for the comparison circuit.

[0078] The bias circuit includes: a seventh MOS transistor Q7, an eighth MOS transistor Q8, a ninth MOS transistor Q9, and a tenth MOS transistor Q10; the source of the seventh MOS transistor is connected to the current source, the gate of the seventh MOS transistor is connected to the gate of the sixth MOS transistor, the drain of the seventh MOS transistor is connected to the drain of the eighth MOS transistor, the source of the eighth MOS transistor is grounded, the gate of the eighth MOS transistor is connected to the gates of the ninth MOS transistor and the tenth MOS transistor, the sources of the ninth MOS transistor and the tenth MOS transistor are grounded, the drain of the ninth MOS transistor is connected to the current source, and the drain of the tenth MOS transistor is connected to the voltage stabilizing circuit, the drain of the fourth MOS transistor, and the gate of the fifth MOS transistor.

[0079] It can be understood that the current source I0 and the MOS transistors Q7 - Q10 form a bias circuit to provide a bias voltage for the comparison circuit.

[0080] The shutdown detection circuit further includes: a voltage stabilizing circuit; the voltage stabilizing circuit is connected to the bias circuit and the comparison circuit; the voltage stabilizing circuit is used to stabilize the comparison circuit through charge and discharge.

[0081] The voltage stabilizing circuit includes: an eleventh MOS transistor Q11 and a twelfth MOS transistor Q12; the drain of the eleventh MOS transistor Q11 is connected to the drain of the tenth MOS transistor Q10, the drain of the fourth MOS transistor, and the gate of the fifth MOS transistor, the gate of the eleventh MOS transistor is connected to the output terminal of the second inverter and the control chip, the source of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor, the source of the twelfth MOS transistor is grounded, and the gate of the twelfth MOS transistor is connected to the gates of the eighth MOS transistor, the ninth MOS transistor, and the tenth MOS transistor.

[0082] It can be understood that the open - circuit detection signal Z of high level is connected back to the gate of the NMOS transistor Q11, making the pull - down branches of Q11 and Q12 conduct, further stabilizing the voltage at point A near the low potential. The open - circuit detection signal Z of low level is connected to the gate of the NMOS transistor Q11, turning off the pull - down branches of Q11 and Q12. At the same time, since the size of the NMOS transistor Q10 is small, the degree of pulling down the voltage at point A is also very small, making the voltage at point A stable at a high level.

[0083] It should be noted that the NMOS transistors Q11 and Q12 stabilize the operating point of the circuit by charging and discharging point A, improving the accuracy and stability of the shutdown detection circuit.

[0084] In this embodiment, when the load is normally connected, the load branch is grounded. Therefore, the value of the output voltage Vout is low and cannot turn on Q4 and Q5 of the comparison circuit. The control chip receives the output open-circuit detection signal Z as a high level, determines that the load is operating normally, Q11 and Q12 of the voltage stabilization circuit turn on, further turning off Q4 and Q5 of the comparison circuit, and the control chip continuously receives the output open-circuit detection signal Z as a high level. When the load is open-circuited, the output voltage Vout is floating. Therefore, the value of the output voltage Vout of the power transistor is high, Q4 and Q5 of the comparison circuit turn on, the control chip receives the output open-circuit detection signal Z as a low level, the control chip determines that the load is open-circuited, Q11 and Q12 of the voltage stabilization circuit turn off, keeping Q4 and Q5 of the comparison circuit continuously turned on, and the control chip continuously receives the output open-circuit detection signal Z as a low level.

[0085] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or system. Without more limitations, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or system including that element.

[0086] The above are only exemplary embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural transformation made under the technical concept of the present invention by using the content of the specification and drawings of the present invention, or direct / indirect application in other related technical fields is included in the patent protection scope of the present invention.

Claims

1. An open circuit detection circuit, characterized in that: The open circuit detection circuit comprises: a power driving chip, a detection circuit and a control chip; The detection circuit is connected to the power driver chip, the load and the control chip; The detection circuit is used to perform open circuit fault diagnosis on the power driver chip and the load, and transmit the diagnosis result to the control chip; The control chip is used to issue a fault prompt when receiving the diagnosis result, prompting the user that the load is open.

2. The open circuit detection circuit according to claim 1, characterized in that: The detection circuit includes: an open detection circuit and a closed detection circuit; The opening detection circuit is respectively connected to the power driving chip, the load and the control chip, and the closing detection circuit is respectively connected to the power driving chip, the load and the control chip; The start-up detection circuit is used to detect the current of the load to obtain the diagnostic current when the power driving chip is in the start-up state, and transmit the diagnostic current to the control chip; The shutdown detection circuit is used to detect the output voltage of the load when the power driver chip is in the shutdown state, compare the output voltage with the threshold voltage, and output the comparison result to the control chip; The control chip is further used to determine whether the load is in an open circuit state according to the diagnostic current and the comparison result.

3. The open circuit detection circuit as claimed in claim 2, characterized in that: The shutdown detection circuit comprises: an acquisition circuit and a comparison circuit; The acquisition circuit is respectively connected to the power driving chip, the load and the comparison circuit, and the comparison circuit is connected to the acquisition circuit and the control chip; The acquisition circuit is used to detect the output voltage of the load when the power driving chip is in the off state, and transmit it to the comparison circuit; The comparison circuit is used to compare the output voltage with the threshold voltage and output the comparison result to the control chip.

4. The open circuit detection circuit as claimed in claim 3, characterized in that: The shutdown detection circuit further includes: a bias circuit; The bias circuit is connected to the comparison circuit; The bias circuit is used to provide a bias voltage for the comparison circuit.

5. The open circuit detection circuit as claimed in claim 4, characterized in that: The shutdown detection circuit further includes: a voltage stabilizing circuit; The voltage stabilizing circuit is connected to the bias circuit and the comparison circuit; The voltage stabilizing circuit is used to stabilize the comparison circuit through charging and discharging.

6. The open circuit detection circuit according to claim 5, characterized in that: The start-up detection circuit comprises: a first MOS tube, a second MOS tube and a first diode; The gate of the first MOS tube is connected to the power driving chip and the gate of the second MOS tube, the drain of the first MOS tube is connected to the drain of the second MOS tube and the cathode of the first diode, and the source of the first MOS tube is connected to the source of the second MOS tube, the load and the anode of the first diode.

7. The open circuit detection circuit according to claim 6, characterized in that: The acquisition circuit includes: a third MOS tube and a second diode; The gate of the third MOS tube is connected to the power driving chip, the drain of the third MOS tube is connected to the cathode of the second diode, and the source of the third MOS tube is connected to the load and the comparison circuit.

8. The open circuit detection circuit according to claim 7, characterized in that: The comparison circuit includes: a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a first inverter and a second inverter; the source of the fourth MOS tube is connected to the load and the acquisition circuit, the gate of the fourth MOS tube is grounded, the drain of the fourth MOS tube is connected to the voltage stabilizing circuit, the bias circuit and the gate of the fifth MOS tube, the source of the fifth MOS tube is grounded, the drain of the fifth MOS tube is connected to the source of the sixth MOS tube and the input end of the first inverter, the gate of the sixth MOS tube is connected to the bias circuit, the source of the sixth MOS tube is connected to the current source, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is connected to the control chip.

9. The open circuit detection circuit according to claim 8, characterized in that: The bias circuit includes: a seventh MOS tube, an eighth MOS tube, a ninth MOS tube and a tenth MOS tube; The source of the seventh MOS tube is connected to the current source, the gate of the seventh MOS tube is connected to the gate of the sixth MOS tube, the drain of the seventh MOS tube is connected to the drain of the eighth MOS tube, the source of the eighth MOS tube is grounded, the gate of the eighth MOS tube is connected to the gate of the ninth MOS tube and the gate of the tenth MOS tube, the source of the ninth MOS tube and the source of the tenth MOS tube are grounded, the drain of the ninth MOS tube is connected to the current source, and the drain of the tenth MOS tube is connected to the voltage stabilizing circuit, the drain of the fourth MOS tube and the gate of the fifth MOS tube.

10. The open circuit detection circuit according to claim 9, characterized in that: The voltage stabilizing circuit comprises: an eleventh MOS tube and a twelfth MOS tube; The drain of the eleventh MOS tube is connected to the drain of the tenth MOS tube, the drain of the fourth MOS tube and the gate of the fifth MOS tube, the gate of the eleventh MOS tube is connected to the output end of the second inverter and the control chip, the source of the eleventh MOS tube is connected to the drain of the twelfth MOS tube, the source of the twelfth MOS tube is grounded, and the gate of the twelfth MOS tube is connected to the gates of the eighth MOS tube, the ninth MOS tube and the tenth MOS tube.

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