Test fixture, test system and test method

Abstract

The present application discloses a test fixture, a test system and a test method, which relate to the field of server testing technology, including setting a first controller, in which line sequence relationship information is stored, wherein the first controller is sequentially connected to an output connector, a virtual board to be tested, a second controller, a virtual board to be tested and an input connector, so as to control the virtual board to be tested to send a test pulse signal from a preset port through the second controller, and when the first controller receives the test pulse signal and obtains the conductive port information associated with the test pulse signal, configures the conductive port connection to achieve connectivity between the preset port and the target port. This solves the problem that manual cable detection and wiring adjustment work is tedious, time-consuming and very inefficient, and can realize automatic correction of the cable wiring sequence on the board and automatic detection of the cable status on the board, thereby improving the efficiency and quality of quality inspection.

Description

Technical Field

[0001] The present application relates to the field of server testing technology, and in particular to a test fixture, a test system, and a test method. Background Art

[0002] Test fixtures are typically used to perform functional tests on assembled server boards. To test the various functions on the boards, the test fixtures require a complex wiring system and ensure that all cables are correctly connected.

[0003] In some related technologies, when determining whether the cable wiring in a test fixture is correct, a quality inspector typically manually uses the two test pens of a multimeter to measure the contact at each end of the connected cable. Due to the large size of the test system, two quality inspectors are often required to work together to complete the test. When abnormal wiring is found, workers are required to manually correct the wiring sequence, which is tedious, time-consuming, and very inefficient. In addition, when the PIN spacing in the connector is dense and very small, manual inspection is prone to missed inspections and incorrect inspections. The manual inspection process may have blind spots, and some small areas cannot be fully inspected. Furthermore, the professional quality of the inspectors varies, resulting in uneven product quality after inspection. Summary of the Invention

[0004] The present application provides a test fixture, a test system, and a test method, which can automatically correct the cable wiring sequence in the test fixture and automatically detect the cable status between the board to be tested and the accompanying board to be tested, so as to at least solve the problems of missed detection and false detection caused by manual labor, and improve the efficiency and quality of quality inspection.

[0005] This application provides a test fixture, including:

[0006] a first controller, one end of the first controller being connected to the input connector and the other end being connected to the output connector;

[0007] a second controller, wherein the first controller stores line sequence relationship information, one end of the second controller is connected to the virtual board to be tested, and the other end is connected to the accompanying virtual board to be tested, the other end of the virtual board to be tested is connected to the input connector, and the other end of the accompanying virtual board to be tested is connected to the output connector;

[0008] querying the line sequence relationship information to obtain a target port number of the accompanying test virtual board associated with the preset port of the virtual board to be tested, and controlling the preset port to send a test pulse signal according to the target port number through the second controller;

[0009] The first controller receives the test pulse signal sent by the input connector, obtains the conductive port information associated with the test pulse signal, and configures the conductive port connection to achieve connectivity between the preset port and the target port.

[0010] Furthermore, an operational amplifier buffer is provided between the input connector and the first controller, and the operational amplifier buffer is used to convert the signal from the input connector and send the converted signal to the first controller.

[0011] Furthermore, it also includes a driving buffer and a relay module, the first end of the driving buffer is connected to the first controller, the second end of the driving buffer is connected to the first end of the relay module, the second end of the relay module is connected to the input connector, and the third end of the relay module is connected to the output connector; in response to the first controller confirming that the test pulse signal is a power signal, the first controller controls the relay module to turn on the power signal and transmits the power signal to the accompanying test virtual board.

[0012] Furthermore, the conductive port includes an input end and an output end, and at least one of the input ends is configured to be connected to at least one of the output ends so that the conductive port is connected.

[0013] Furthermore, the second controller controls the preset port to send different numbers of the test pulse signals to the first controller, and the number of the test pulse signals is determined according to the target port number.

[0014] Furthermore, the second controller includes a control module and a debugging interface board, and the debugging interface board is provided with a signal sending end and a signal receiving end; the signal sending end is connected to the debugging interface of the virtual board to be tested, and is used to send the test pulse signal generated by the control module, and the signal receiving end is connected to the debugging interface of the accompanying virtual board for testing, and is used to receive the test pulse signal.

[0015] Furthermore, a plurality of connection interfaces are provided on the debugging interface board, and the number of the connection interfaces is greater than or equal to the number of PINs of the virtual board to be tested.

[0016] Furthermore, the signal receiving end of the debugging interface board is provided with a plurality of receiving PINs and a plurality of indicator lights, and the receiving PINs and the indicator lights are provided in a one-to-one correspondence.

[0017] Furthermore, the control module controls the sending PIN of the signal sending end to send a diagnostic pulse signal, the signal receiving end receives the diagnostic pulse signal, and records the port number of the diagnostic pulse signal; the port number of the diagnostic pulse signal is compared and analyzed with the line sequence relationship information, and in response to an abnormality in the port number of the diagnostic pulse signal, the indicator light of the port associated with the abnormal port number is controlled to light up.

[0018] Furthermore, the virtual board to be tested is provided with an interface PIN to be tested, the interface PIN to be tested is connected to a probe fixing board, the probe fixing board is connected to a probe, and the probe is connected to the input connector via a connecting line.

[0019] Furthermore, one end of the output connector away from the first controller is connected to a connection terminal on the accompanying test virtual board via a connecting line.

[0020] Furthermore, the number of PINs of the conduction port of the first controller is greater than the number of PINs of the virtual board to be tested.

[0021] Furthermore, the accompanying test virtual board is provided with a reserved interface, and the reserved interface is provided as a universal connector.

[0022] The present application also provides a testing system, which includes any of the above-mentioned testing fixtures.

[0023] The present application also provides a testing method based on any of the above-mentioned test fixtures, the method comprising:

[0024] querying the line sequence relationship information to obtain a target port number of the accompanying test virtual board associated with the preset port of the virtual board to be tested, and controlling the preset port by the second controller to send a test pulse signal according to the target port number;

[0025] The first controller receives the test pulse signal sent by the input connector, obtains the conductive port information associated with the test pulse signal, and configures the conductive port to be connected to achieve connection between the preset port and the target port.

[0026] By setting a first controller in the present application to connect the output connector, the accompanying test virtual board, the second controller, the virtual board to be tested and the input connector in sequence, the second controller controls the virtual board to be tested to send a test pulse signal from the preset port. When the first controller receives the information of this pulse test signal and obtains the conduction port information associated with the test pulse signal, the conduction port inside the first controller is configured to be connected to achieve the connection between the preset port and the target port, thereby achieving the connection between the virtual board to be tested and the corresponding port on the accompanying test virtual board; so that when the wiring sequence needs to be corrected, it is only necessary for the second controller to control the virtual board to be tested to send the corresponding test pulse signal in sequence according to the port number of the preset port. After the first controller receives this test pulse signal, it connects its internal ports according to the test pulse signal information to ensure that the port on the virtual board to be tested and the port on the accompanying test virtual board are correctly connected, thereby automatically correcting the cable wiring sequence on the board and automatically detecting the cable status on the board, thereby improving the efficiency and quality of quality inspection. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0028] Figure 1 A schematic diagram of a test fixture provided in an embodiment of the present application;

[0029] Figure 2 A schematic diagram of the connection architecture between the first controller and the second controller provided in an embodiment of the present application;

[0030] Figure 3 A schematic diagram of the structure of the virtual board to be tested provided in an embodiment of the present application;

[0031] Figure 4 A schematic diagram of the internal circuit of the first controller provided in this embodiment;

[0032] Figure 5 A schematic diagram showing the connection between the black box, the virtual board to be tested, and the accompanying virtual board provided in this embodiment;

[0033] Figure 6 A schematic diagram showing the connection between the second controller, the virtual board to be tested, and the accompanying virtual board provided in this embodiment;

[0034] Figure 7 A schematic diagram of the structure of the accompanying test virtual board provided in this embodiment;

[0035] Figure 8A schematic diagram of a test fixture in another embodiment provided by this embodiment;

[0036] Figure 9 Schematic diagram of the testing method provided in this embodiment. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0038] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0039] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0040] The embodiment of the present application provides a test fixture that can correct and detect the cable sequence in the test fixture, such as Figure 1 and Figure 2 As shown, it specifically includes: a first controller, an output connector, a companion test virtual board, a second controller, a virtual board to be tested, and an input connector, wherein the first controller is configured as an MCU module, an MCU chip is configured in the MCU module, a first end of the first controller is connected to the input connector, a second end of the first controller is connected to the output connector, the other end of the input connector is connected to the virtual board to be tested, and the other end of the output connector is connected to the companion test virtual board; the second controller is configured as an MCU controller, and line sequence relationship information is stored in the second controller, a first end of the second controller is connected to the virtual board to be tested, and the other end of the second controller is connected to the companion test virtual board to form a wiring test architecture for the virtual board to be tested.

[0041] When correcting the wiring sequence, the system first performs corrections based on the ports in the wire sequence relationship information. The system first confirms the preset port of the virtual board under test, then queries the wire sequence relationship information to obtain the target port number of the accompanying virtual board associated with the preset port of the virtual board under test. The system then controls the preset port via the second controller to send a test pulse signal based on the target port number. Specifically, the second controller controls the preset port to send different numbers of test pulse signals to the first controller, with the number of test pulse signals determined by the target port number. For example, if the target port number is "P1-PIN3," three test pulse signals are sent, while if the target port number is "P1-PIN6," six test pulse signals are sent.

[0042] Furthermore, the first controller receives the test pulse signal sent by the input connector, obtains the conduction port information associated with the test pulse signal according to the number of the test pulse signal, and configures the conduction port connection to achieve connectivity between the preset port and the target port, that is, to achieve correct connection between the ports on the virtual board to be tested and the accompanying virtual board.

[0043] It should be noted that the virtual board to be tested in this embodiment refers to a board that has the same shape, size and test interface position as the real board to be tested. By simplifying the internal circuits of the virtual board to be tested, end-to-end connectivity with the debug interface is achieved, thereby facilitating line sequence correction and quality inspection of the board. Specifically, Figure 3 As shown, the virtual board to be tested in this embodiment includes N interfaces to be tested, which are named 1, 2, 3...N respectively. A number of PINs are set for each interface to be tested, and the PINs are numbered from 1 to X. The debug interface on the virtual board to be tested is set with X PINs. The internal connection lines of the virtual board to be tested are configured so that the interface to be tested PIN1 corresponds to the debug interface PIN1, the interface to be tested PIN2 corresponds to the debug interface PIN2, and the interface to be tested PINX corresponds to the debug interface PINX.

[0044] Furthermore, the internal link design of the accompanying test virtual board is the same as that of the virtual card to be tested, and the shape, size and position of the accompanying test interface are the same as those of the real accompanying test board; there are multiple accompanying test virtual boards, each of which contains one or more accompanying test interfaces. In this embodiment, multiple accompanying test interfaces are integrated on one board, and the accompanying test interfaces are numbered 1 to N and the PIN pins are numbered 1 to X respectively.

[0045] It should be noted that in order to ensure that the line sequence correction of all interfaces to be tested on the virtual card to be tested can be achieved through the cooperation of the first controller and the second controller in this embodiment, the number of PINs of the conduction port of the first controller is set to be greater than the number of PINs of the virtual board to be tested, based on the maximum number of ports supported by the MCU in the first controller, and the MCU model is not restricted.

[0046] In this embodiment, the test fixture also includes an operational amplifier buffer connected between the first controller and the input connector, and the operational amplifier buffer is used to convert the signal of the input connector and send the converted signal to the first controller. Specifically, the operational amplifier buffer converts the input connector signal into a standard voltage logic state through the high-impedance input of the operational amplifier, and sends it to the first controller for detection to avoid directly inputting high voltage to damage the first controller. At the same time, the operational amplifier buffer realizes a foolproof function, avoiding the risk of burning the board or damaging the link equipment in the traditional mode, that is, it not only realizes the protection of the MCU chip in the first controller, but also isolates the input and output ends, blocks abnormal circuits and high voltages outside the operational amplifier, and even if there is a wiring error in the test fixture, it can be directly powered on using the real board to be tested without burning.

[0047] It should be noted that in this embodiment, the test pulse signal is a pulse signal with a pulse greater than 0. When the test pulse signal is 0 pulse, the test pulse signal is a power signal. In this case, the power signal needs to be configured for correct connection. Specifically, the test fixture also includes a drive buffer and a relay module. The first end of the drive buffer is connected to the first controller, the second end of the drive buffer is connected to the first end of the relay module, the second end of the relay module is connected to the input connector, and the third end of the relay module is connected to the output connector.

[0048] Among them, the driving buffer is used to provide the relay module with current and voltage to drive the relay module to work, so that the MCU signal from the first controller drives the relay to work. The relay module is used to control the driving buffer to drive the relay module to work after the first controller detects the power signal, and transmit the input power signal to the output connector. The power signal includes VCC signal, GND signal, etc., that is, in response to the first controller confirming that the test pulse signal is a power signal, the first controller controls the relay module to turn on the power signal, and transmits the power signal to the accompanying test virtual board through the output connector to realize the power signal configuration connection.

[0049] For example, Figure 4 As shown, PIN1 of P2 is configured as a VCC signal, PIN2 of P2 is configured as a GND signal, and PIN3 of P2 is configured as a pulse signal. When the second controller controls the virtual board to be tested to send the VCC signal of P2 to the first controller, the MCU module in the first controller recognizes the VCC signal and controls the corresponding conduction port in the relay module to be turned on, and then transmits the VCC signal to the virtual board to be tested through the output connector.

[0050] In a specific embodiment, the conductive port in the first controller is set to include a plurality of input terminals and a plurality of output terminals, and the plurality of input terminals and the plurality of output terminals are numbered respectively, and each input terminal is set to have a first number, and each output terminal is set to have a second number, the input terminals are 1~M, and the output terminals are set to 1~N, and at least one input terminal is configured to be connected with at least one output terminal to form a conductive path, and the conductive path is set to have a third number, and a correspondence table between the input terminal, the output terminal and the conductive path is constructed; the conductive path number is set to correspond one-to-one with the number of test pulse signals, and before the line sequence correction is performed, the above-mentioned input terminal and the output terminal are in a non-connected state. When the first controller receives the test pulse signal, the conductive path number associated with it is queried according to the number of the test pulse signal, and the correspondence table is queried in combination with the third number of the conductive path to obtain the corresponding numbers of the input terminal and the output terminal that can realize the connection of the conductive path, and the input terminal PIN and the output terminal PIN of the corresponding number are configured to be connected, thereby realizing the connection of the conductive port.

[0051] For example, Figure 4 As shown, by querying the line sequence correspondence, it can be confirmed that PIN3 on the virtual board to be tested should be connected to PIN6 on the accompanying virtual board. When the first controller receives the test pulse signal sent by the second controller, it identifies the conduction path number of the test pulse signal pipeline, thereby confirming which port of the input connector the test pulse signal points to, and judging the input and output ends that should be connected; illustratively, the MCU should control the input end PIN8 to connect to the output end PIN18, that is, after the MCU module of the first controller receives the pulse signal, it controls the internal link of the chip to connect the input end PIN8 and the output end PIN18, thereby completing the line sequence correction work, and using the test fixture after the line sequence correction for the server board test to ensure the accuracy of the server board test.

[0052] In a specific embodiment, in order to make the test fixture more convenient to connect with the board to be tested in the actual use scenario, the first controller, operational amplifier buffer, input connector, relay module, drive buffer and output connector are connected as follows: Figure 1 and Figure 5 The connection relationships shown are connected in sequence, and the architecture after connection is configured as a whole, that is, it is set as a black box. The black box is provided with a P1 interface and a P2 interface on the outside, wherein the P1 interface is used to connect the connecting line of the accompanying virtual board, wherein the accompanying virtual board includes but is not limited to the hard disk backplane, and the P2 interface is used to connect the connecting line of the virtual board to be tested, so as to realize the connection assembly of the test fixture.

[0053] Through the above settings, the second controller can control the preset port of the virtual board to be tested to send different numbers of test pulse signals to the first controller. The number of test pulse signals is determined according to the port number of the preset port. Specifically, the line sequence relationship information is queried according to the port number of the preset port to obtain the preset number of test pulse signals. When performing line sequence correction, different preset numbers of test pulse signals are sent to the first controller in sequence according to the order of the tested interfaces of the virtual board to be tested in the line sequence relationship information to achieve correction of all line sequences. After the virtual board to be tested and the accompanying virtual board are connected to each other according to the above wiring test architecture, the wiring of the interfaces on the virtual board to be tested can be automatically corrected in sequence by sending test pulse signals, which greatly improves the wiring correction efficiency and avoids the situation where wiring confusion is caused by manual operation.

[0054] In order to achieve further diagnosis of the corrected wiring to ensure that the lines in the entire wiring system are correctly connected, a second controller is set up, including a control module and a debugging interface board. The debugging interface board is provided with a signal sending end and a signal receiving end; the signal sending end is connected to the debugging interface of the virtual board to be tested, and is used to send the test pulse signal generated by the control module; the signal receiving end is connected to the debugging interface of the accompanying virtual board, and is used to receive the test pulse signal.

[0055] It should be noted that the control module uses an MCU as the main control chip, which is used to generate, send, and receive pulse signals. The debug interface board serves as a connection unit, and a plurality of connection interfaces are provided on the debug interface board, wherein the number of connection interfaces is greater than or equal to the number of pins of the virtual board to be tested. By arranging multiple connection interfaces on the debug interface board, the conductivity test of the interface on the virtual board to be tested can be implemented.

[0056] Further, such as Figure 6 As shown, a number of receiving PINs and a number of indicator lights are set at the signal receiving end of the debugging interface board, and the receiving PINs and the indicator lights are set one by one, wherein the indicator lights are controlled to light up by the control module. The second controller also includes a communication module, which is used for remote connection with an external server to upload the quality inspection diagnosis results to the external server.

[0057] The virtual board to be tested in this embodiment is provided with a test interface, which is connected to a probe fixing plate, a probe is connected to the probe fixing plate, the probe is connected to the input connector via a connecting line, and the end of the output connector away from the first controller is connected to the terminal on the accompanying virtual board via a connecting line.

[0058] like Figure 1As shown, when performing line sequence correction and diagnosis on the board to be tested in the test fixture, it is only necessary to obtain the virtual board to be tested corresponding to the board to be tested, and configure the virtual board to be tested to connect in sequence, the connection interface on the debugging interface board, the signal sending end in the first controller, the signal receiving end in the first controller, the connection interface of the accompanying virtual board, the wiring terminal, the original cable of the whole machine and the second controller, and configure the above connection architecture to form a diagnostic platform, wherein the diagnostic platform has an external signal sending end and a signal receiving end to facilitate the assembly and connection of the test fixture. Then configure one end of the input connector in the second controller to be connected in sequence with the probe, the probe fixing plate and the virtual board to be tested, thereby forming a complete test system, adjust the test fixture to the working state, that is, close the lid, complete the docking of the upper and lower molds, that is, realize the connection between the PIN pin of the interface to be tested on the virtual board to be tested and the probe, and complete the physical environment connection.

[0059] In a specific embodiment, the diagnostic test process is started: the control module controls the sending PIN of the signal sending end to send a diagnostic pulse signal, the signal receiving end receives the diagnostic pulse signal, and records the port number of the diagnostic pulse signal; the port number of the diagnostic pulse signal is compared and analyzed with the line sequence relationship information, and in response to an abnormality in the port number of the diagnostic pulse signal, the indicator light of the port associated with the abnormal port number is controlled to light up.

[0060] For example, Figure 4 As shown, the line sequence correction process is started. The line sequence corresponding information is stored in the MCU module of the first controller. The 1-X1 PIN of the virtual board of the test board is controlled to send different numbers of pulse signals. The number of pulses depends on the target port number of the accompanying test board to which the current PIN needs to be connected. For example, if the target port number is PIN3, then 3 pulses are sent. And so on, the line sequence correction work of all PINs is completed one by one. Then, the line conductivity diagnosis test is started. The first controller controls the interface to send pulse signals in sequence through the signal sending end according to the port order in the line sequence relationship information. If the signal receiving end receives this pulse signal, it indicates that the line of the preset port is conductive. If this pulse signal is not received, it indicates that the line of the preset port is not conductive. According to the above process, all ports on the virtual board to be tested are tested, and the diagnostic test results are recorded and output. Combined with the abnormal port information in the diagnostic test results, the indicator light corresponding to the abnormal port is controlled to light up.

[0061] In a specific embodiment, in order to ensure that the accompanying test virtual board can be applied to the test process of the test board in various scenarios, such as Figure 7 As shown, the accompanying test virtual board is set to set several reserved interfaces, and the reserved interfaces are set to universal connectors. For example, the reserved interfaces use universal PHB connectors. When other connectors need to be installed, it can be achieved by adding an adapter board, which saves costs.

[0062] The solution in this embodiment optimizes the wiring method. It is no longer necessary to perform wiring one by one according to the corresponding line sequence. Instead, the solution in this embodiment automatically corrects the connected lines to achieve connectivity between the corresponding ports on the board under test and the accompanying board under test, improving wiring efficiency. At the same time, an automated diagnostic test process is employed to automatically diagnose and test the connected wiring architecture, avoiding missed or incorrect detections caused by human factors. Furthermore, the system is not limited by fixture size, blind spots, or other factors. Port-by-port testing is efficient and accurate, improving the quality of delivered products and reducing the time-consuming and tedious nature of manual quality inspections, thereby improving quality inspection efficiency and quality.

[0063] Corresponding to the above embodiment, a test fixture is provided in this embodiment. The difference between this embodiment and the above embodiment is that the first controller is not provided in this embodiment. By setting the first controller as an adapter card, other components remain unchanged, that is, by Figure 8 The test fixture shown is used to implement diagnostic testing of the virtual board to be tested, specifically including the virtual board to be tested, which is configured to be connected in sequence to the connection interface on the debugging interface board, the signal sending end in the first controller, the signal receiving end in the first controller, the connection interface of the accompanying virtual board, the wiring terminal, the original cable of the whole machine and the adapter card. One end of the adapter card is connected to the probe through a cable, and the other end is connected to the wiring terminal on the accompanying virtual board through the original cable of the whole machine. Through the above-mentioned test architecture, the first controller controls the interface to send pulse signals in sequence through the signal sending end according to the port order in the line sequence relationship information. When the signal receiving end receives this pulse signal, it indicates that the line of the preset port is conductive. If the pulse signal is not received, it indicates that the line of the preset port is not conductive, thereby realizing the conductivity test of the connection line between the virtual board to be tested and the accompanying virtual board.

[0064] Corresponding to the above embodiments, this embodiment provides a test system, which includes any one of the above test fixtures.

[0065] In a specific embodiment, the test fixture includes:

[0066] a first controller, one end of the first controller being connected to the input connector and the other end being connected to the output connector;

[0067] A second controller stores line sequence relationship information in the first controller, one end of the second controller is connected to the virtual board to be tested, and the other end is connected to the accompanying virtual board to be tested, the other end of the virtual board to be tested is connected to the input connector, and the other end of the accompanying virtual board to be tested is connected to the output connector;

[0068] Querying the line sequence relationship information to obtain the target port number of the accompanying virtual board associated with the preset port of the virtual board to be tested, and controlling the preset port to send a test pulse signal according to the target port number through the second controller;

[0069] The first controller receives the test pulse signal sent by the input connector, obtains the conductive port information associated with the test pulse signal, and configures the conductive port connection to achieve connectivity between the preset port and the target port.

[0070] In a specific embodiment, an operational amplifier buffer is provided between the input connector and the first controller, and the operational amplifier buffer is used to convert the signal from the input connector and send the converted signal to the first controller.

[0071] In a specific embodiment, it also includes a driving buffer and a relay module, the first end of the driving buffer is connected to the first controller, the second end of the driving buffer is connected to the first end of the relay module, the second end of the relay module is connected to the input connector, and the third end of the relay module is connected to the output connector; in response to the first controller confirming that the test pulse signal is a power signal, the first controller controls the relay module to turn on the power signal and transmit the power signal to the accompanying test virtual board.

[0072] In a specific embodiment, the conductive port includes an input terminal and an output terminal, and at least one input terminal is configured to communicate with at least one output terminal so that the conductive port is connected.

[0073] In a specific embodiment, the second controller controls the preset port to send different numbers of test pulse signals to the first controller, and the number of the test pulse signals is determined according to the target port number.

[0074] In a specific embodiment, the second controller includes a control module and a debugging interface board, and the debugging interface board is provided with a signal sending end and a signal receiving end; the signal sending end is connected to the debugging interface of the virtual board to be tested, and is used to send the test pulse signal generated by the control module, and the signal receiving end is connected to the debugging interface of the accompanying virtual board for testing, and is used to receive the test pulse signal.

[0075] In a specific embodiment, a plurality of connection interfaces are provided on the debugging interface board, and the number of the connection interfaces is greater than or equal to the number of PINs of the virtual board to be tested.

[0076] In a specific embodiment, the signal receiving end of the debugging interface board is provided with a plurality of receiving PINs and a plurality of indicator lights, and the receiving PINs and the indicator lights are provided in a one-to-one correspondence.

[0077] In a specific embodiment, the control module controls the sending PIN of the signal sending end to send a diagnostic pulse signal, the signal receiving end receives the diagnostic pulse signal, and records the port number of the diagnostic pulse signal; the port number of the diagnostic pulse signal is compared and analyzed with the line sequence relationship information, and in response to an abnormality in the port number of the diagnostic pulse signal, the indicator light of the port associated with the abnormal port number is controlled to light up.

[0078] In a specific embodiment, the virtual board to be tested is provided with a test interface PIN, the test interface PIN is connected to a probe fixing board, the probe fixing board is connected to a probe, and the probe is connected to an input connector via a connecting line.

[0079] In a specific embodiment, the end of the output connector away from the first controller is connected to a connection terminal on the accompanying test virtual board through a connecting wire.

[0080] In a specific embodiment, the number of PINs in the driving circuit of the first controller is greater than the number of PINs of the virtual board to be tested.

[0081] In a specific embodiment, the accompanying test virtual board is provided with a reserved interface, and the reserved interface is provided as a universal connector.

[0082] Corresponding to the above embodiment, this embodiment provides a testing method based on the above test fixture, such as Figure 9 As shown, the method includes:

[0083] Step 101: querying line sequence relationship information to obtain a target port number of a companion virtual board associated with a preset port of the virtual board to be tested, and a second controller controlling the preset port to send a test pulse signal according to the target port number;

[0084] Step 102: The first controller receives the test pulse signal sent by the input connector, obtains the conductive port information associated with the test pulse signal, and configures the conductive port to be connected to achieve connection between the preset port and the target port.

[0085] In a specific embodiment, the control module in the second controller controls the sending PIN of the signal sending end to send a diagnostic pulse signal, the signal receiving end receives the diagnostic pulse signal, and records the port number of the diagnostic pulse signal; compares and analyzes the port number of the diagnostic pulse signal with the line sequence relationship information, and in response to an abnormality in the port number of the diagnostic pulse signal, controls the indicator light of the port associated with the abnormal port number to light up.

[0086] For descriptions of the features in the embodiments corresponding to the test method, please refer to the relevant descriptions of the embodiments corresponding to the test fixture, which will not be repeated here.

[0087] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0088] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above-mentioned test method embodiments when running.

[0089] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0090] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0091] The above is a detailed introduction to a test fixture, test system and test method provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A test fixture, characterized in that: include: a first controller, one end of the first controller being connected to the input connector and the other end being connected to the output connector; a second controller, wherein the first controller stores line sequence relationship information, one end of the second controller is connected to the virtual board to be tested, and the other end is connected to the accompanying virtual board to be tested, the other end of the virtual board to be tested is connected to the input connector, and the other end of the accompanying virtual board to be tested is connected to the output connector; querying the line sequence relationship information to obtain a target port number of the accompanying test virtual board associated with the preset port of the virtual board to be tested, and controlling the preset port to send a test pulse signal according to the target port number through the second controller; The first controller receives the test pulse signal sent by the input connector, obtains the conductive port information associated with the test pulse signal, and configures the conductive port connection to achieve connectivity between the preset port and the target port.

2. The test fixture according to claim 1, characterized in that: An operational amplifier buffer is provided between the input connector and the first controller, and the operational amplifier buffer is used to convert the signal from the input connector and send the converted signal to the first controller.

3. The test fixture according to claim 1 or 2, characterized in that: It also includes a driving buffer and a relay module, wherein a first end of the driving buffer is connected to the first controller, a second end of the driving buffer is connected to a first end of the relay module, a second end of the relay module is connected to the input connector, and a third end of the relay module is connected to the output connector; In response to the first controller confirming that the test pulse signal is a power signal, the first controller controls the relay module to turn on the power signal and transmits the power signal to the accompanying test virtual board.

4. The test fixture according to claim 3, characterized in that: The conductive port includes an input end and an output end, and at least one of the input ends is configured to communicate with at least one of the output ends so that the conductive port is in communication.

5. The test fixture according to claim 1 or 2, characterized in that: The second controller controls the preset port to send different numbers of the test pulse signals to the first controller, and the number of the test pulse signals is determined according to the target port number.

6. The test fixture according to claim 1 or 2, characterized in that: The second controller includes a control module and a debugging interface board, wherein the debugging interface board is provided with a signal sending end and a signal receiving end; The signal sending end is connected to the debugging interface of the virtual board to be tested and is used to send the test pulse signal generated by the control module. The signal receiving end is connected to the debugging interface of the accompanying virtual board and is used to receive the test pulse signal.

7. The test fixture according to claim 6, characterized in that: The debugging interface board is provided with a plurality of connection interfaces, and the number of the connection interfaces is greater than or equal to the number of PINs of the virtual board to be tested.

8. The test fixture according to claim 6, characterized in that: The signal receiving end of the debugging interface board is provided with a plurality of receiving PINs and a plurality of indicator lights, and the receiving PINs and the indicator lights are provided in a one-to-one correspondence.

9. The test fixture according to claim 8, characterized in that: The control module controls the sending PIN of the signal sending end to send a diagnostic pulse signal, the signal receiving end receives the diagnostic pulse signal, and records the port number of the diagnostic pulse signal; The port number of the diagnostic pulse signal is compared and analyzed with the line sequence relationship information. In response to an abnormality in the port number of the diagnostic pulse signal, the indicator light of the port associated with the abnormal port number is controlled to light up.

10. The test fixture according to claim 1 or 2, characterized in that: The virtual board to be tested is provided with an interface to be tested, the interface to be tested is connected to a probe fixing board, the probe fixing board is connected to a probe, and the probe is connected to the input connector via a connecting line.

11. The test fixture according to claim 10, characterized in that: One end of the output connector away from the first controller is connected to a connection terminal on the accompanying test virtual board through a connecting line.

12. The test fixture according to claim 1 or 2, characterized in that: The number of PINs of the conductive port of the first controller is greater than the number of PINs of the virtual board to be tested.

13. The test fixture according to claim 1 or 2, characterized in that: The accompanying test virtual board is provided with a reserved interface, and the reserved interface is provided as a universal connector.

14. A testing system, characterized in that: The testing system comprises the testing fixture according to any one of claims 1 to 13.

15. A testing method based on the testing fixture according to any one of claims 1 to 13, characterized in that: The method comprises: Querying line sequence relationship information according to the port number of the preset port to obtain a preset number of test pulse signals, and the second controller controls the preset port of the virtual board to be tested to send the preset number of test pulse signals; The first controller receives the test pulse signal sent by the input connector, and queries the line sequence relationship information based on the test pulse signal information to obtain the target port number associated with the test pulse signal information, and controls the driving circuit in the first controller to connect to the target port according to the target port number.

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