Data loading method, data burning method and equipment

Abstract

The invention relates to the field of chip design, and discloses a data loading method, a data burning method and equipment. After a chip is powered on, target data stored in an OTP memory are loaded according to a preset working sequence; under the condition that the first data in the target data is loaded, sending the first data to a corresponding target register so as to configure the target register; loading the first data again under the condition that a preset reloading condition is met, so as to trigger and execute the step of sending the first data to the corresponding target register and the following steps under the condition that the first data is loaded, so as to configure the target register again; on the premise that the chip is not scrapped, it can be guaranteed that the configured target register is not cracked, and therefore the running safety of the chip is guaranteed.

Description

Technical Field

[0001] The present disclosure relates to the field of chip design, and particularly to a data loading method, a data programming method, and a device. Background Art

[0002] Chip power-on initialization refers to a series of initialization and configuration processes inside the chip after electrical energy is applied to the chip. Chip power-on initialization is a crucial step for the chip to work properly. During the initialization process, it is usually necessary to load pre-stored data to configure the chip.

[0003] Generally, the target data used in the chip initialization process can be stored in an external flash memory or a one-time programmable (OTP) memory inside the chip. The target data is read during the initialization process to configure the chip.

[0004] However, the cost of flash memory is relatively high and it is an external device. Compared with the initialization based on the OTP memory, the initialization based on flash memory is slower. For the chip configurations with high real-time requirements, such as chip clock calibration, voltage calibration and other configuration parameters, using flash memory for initialization may affect the normal startup of the chip. At the same time, there is also a risk that the target data stored in such an external device is cracked.

[0005] Since each bit of the OTP memory can only be written once and cannot be changed, the target data can be written into the OTP memory, thus avoiding the problem of the stored target data being cracked and improving the security of the chip. However, multiple functional modules may be integrated in the chip. After the target register of the functional module is configured based on the target data in the OTP memory, the data in the target register can also be cracked.

[0006] In order to prevent the data of the functional modules in the chip from being cracked, traditional methods include adding external circuit anti-cracking means and detecting cracking and automatically triggering inactivation means.

[0007] However, adding external circuits will lead to problems of increasing the chip manufacturing difficulty and cost, and detecting cracking and automatically triggering inactivation will lead to the problem of chip scrapping. Summary of the Invention

[0008] In view of this, the present disclosure provides a data loading method, a data programming method, and a device, which can perform power-on initialization on a type of chip and prevent the chip from being cracked without damaging the chip.

[0009] According to one aspect of the present disclosure, there is provided a data loading method, the method comprising:

[0010] After the chip is powered on, load the target data stored in the one-time programmable OTP memory according to a preset working sequence; wherein, a one-time programmable OTP memory is provided in the chip, and the target data includes first data, and the first data is used to configure at least one target register in the chip;

[0011] When the first data is loaded, send the first data to the corresponding target register to configure the target register;

[0012] When a preset reloading condition is satisfied, reload the first data again to trigger the execution of the step of sending the first data to the corresponding target register and subsequent steps when the first data is loaded, so as to reconfigure the target register.

[0013] In a possible implementation manner, the target data further includes second data, and the second data is used to identify whether to start a reloading mechanism, and the data loading order of the second data is before the data loading order of the first data;

[0014] Correspondingly, the method further includes:

[0015] When the second data is loaded, determine whether the second data is the same as a preset identifier;

[0016] When the second data is the same as the preset identifier, start the reloading mechanism to trigger the execution of the step of reloading the first data again when a preset reloading condition is satisfied and subsequent steps.

[0017] In a possible implementation manner, the reloading condition includes: the target data is loaded once, and the timer duration triggered after the chip is powered on reaches a preset duration; wherein, the preset duration is greater than the total duration of the target data being loaded once;

[0018] Correspondingly, starting the reloading mechanism includes:

[0019] Start a timer to obtain the timer duration; when the timer duration of the timer reaches the preset duration, start timing again.

[0020] In a possible implementation manner, the first data includes the register address and register data of the target register;

[0021] Correspondingly, sending the first data to the corresponding target register includes:

[0022] For each set of first data, drive the read register address to the address interface connected to the bus, and drive the read register data to the data interface connected to the bus;

[0023] After the first data is read, trigger the enable interface connected to the bus to generate an enable signal to send the memory data at the data interface to the target register indicated by the register address at the address interface.

[0024] In a possible implementation, the target data further includes third data for calibrating target parameters in the chip;

[0025] Correspondingly, the method further includes:

[0026] When the third data is loaded, send the third data to the parameter interface corresponding to the target parameter in the chip to calibrate the target parameter;

[0027] When the reloading condition is met, reload the third data to trigger the execution of the step of sending the third data to the parameter interface corresponding to the target parameter in the chip and subsequent steps to calibrate the target parameter again.

[0028] The OTP memory includes a storage space for storing at least two sets of third data. Correspondingly, the currently effective third data also has a flag bit for identifying that the third data is currently effective;

[0029] Correspondingly, the method further includes:

[0030] Load the third data with the flag bit in the storage space.

[0031] In a possible implementation, the sending the third data to the parameter interface corresponding to the target parameter in the chip includes:

[0032] Drive the third data to the data interface connected to the dedicated line to send the third data to the parameter interface through the dedicated line.

[0033] In a possible implementation, the loading the target data stored in the OTP memory according to a preset working order includes:

[0034] Read the target data;

[0035] Perform data verification on the target data and store the verification value obtained from the data verification.

[0036] According to another aspect of the present disclosure, a data programming method is provided, the method including:

[0037] Obtaining target data sent by a programming device; wherein, the target data includes first data for configuring at least one target register in a chip;

[0038] Storing the target data in an OTP memory, so that after the chip to which the OTP memory belongs is powered on, the target data stored in the OTP memory is loaded according to a preset working order; when the first data is loaded, sending the first data to a corresponding target register to configure the target register; and when a preset reloading condition is met, reloading the first data again to trigger the execution of the step of sending the first data to a corresponding target register and subsequent steps when the first data is loaded, so as to configure the target register again.

[0039] In a possible implementation manner, after storing the target data in the OTP memory, it further includes:

[0040] When it is necessary to update the first data, obtaining the updated first data;

[0041] Storing the updated first data in the OTP memory.

[0042] In a possible implementation manner, the target data further includes third data for calibrating target parameters in the chip; the OTP memory includes a storage space for storing at least two groups of third data, and the currently effective third data further has a flag bit;

[0043] Correspondingly, after storing the target data in the OTP memory, it further includes:

[0044] When it is necessary to update the currently effective third data in the OTP memory, destroying the flag bit of the currently effective third data;

[0045] Obtaining the updated third data;

[0046] Setting a flag bit for the updated third data, and storing the updated third data with the flag bit in the storage space.

[0047] According to another aspect of the present disclosure, an OTP module is provided, the OTP module including:

[0048] An OTP controller;

[0049] A register for storing executable instructions of the OTP controller;

[0050] An OTP memory for storing target data, where the target data includes first data for configuring at least one target register in a chip to which the OTP module belongs;

[0051] Wherein, the OTP controller is configured to implement any of the above methods when executing an instruction stored in the register.

[0052] According to another aspect of the present disclosure, a chip is provided, which includes the above OTP module.

[0053] According to another aspect of the present disclosure, a display device is provided, which includes a plurality of display units and at least one of the above chips.

[0054] In a possible implementation, the display unit includes a display panel, and the display panel includes at least one of a liquid crystal display panel, a micro light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electro-wetting display panel, and a small-pitch display panel.

[0055] After the chip is powered on, load the target data stored in the OTP memory according to a preset working sequence; when the first data in the target data is loaded, send the first data to the corresponding target register to configure the target register; when a preset reloading condition is met, reload the first data again to trigger the execution of the step of sending the first data to the corresponding target register and subsequent steps when the first data is loaded, so as to reconfigure the target register again; on the one hand, by burning the target data into the OTP memory, it can be ensured that the target data stored in the OTP memory cannot be cracked; on the other hand, the first data in the OTP memory can be repeatedly used to configure the target register. In this way, even if the configuration data in the target register is tampered with briefly, the configuration data in the target register will be reconfigured due to the reloading mechanism later. Without scrapping the chip, it is ensured that the configured target register cannot be cracked, thereby ensuring the security of the chip operation.

[0056] According to the following detailed description of exemplary embodiments with reference to the accompanying drawings, other features and aspects of the present disclosure will become clear. Description of the Drawings

[0057] The accompanying drawings that are included in and form a part of the specification illustrate exemplary embodiments, features, and aspects of the present disclosure, and are used to explain the principles of the present disclosure together with the specification.

[0058] Figure 1 The structural diagram of an OTP module according to an embodiment of the present disclosure is shown;

[0059] Figure 2 The structural diagram of a chip according to an embodiment of the present disclosure is shown;

[0060] Figure 3 The flowchart of a data programming method according to an embodiment of the present disclosure is shown;

[0061] Figure 4 The schematic diagram of a preset storage structure for storing target data according to an embodiment of the present disclosure is shown;

[0062] Figure 5 The flowchart of a data loading method according to an embodiment of the present disclosure is shown;

[0063] Figure 6 The schematic diagram of a storage structure for storing first data according to an embodiment of the present disclosure is shown;

[0064] Figure 7 The schematic diagram of a finite state machine in an OTP module according to an embodiment of the present disclosure is shown;

[0065] Figure 8 The block diagram of a data loading device according to an embodiment of the present disclosure is shown;

[0066] Figure 9 The block diagram of a data programming device according to an embodiment of the present disclosure is shown. Detailed Description of the Embodiments

[0067] The various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings do not have to be drawn to scale unless otherwise specified.

[0068] In the description of the present disclosure, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present disclosure.

[0069] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, "a plurality of" means two or more unless otherwise specifically defined.

[0070] In the present disclosure, unless otherwise clearly specified and limited, the terms such as "install", "connect", "connection", "fixation", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0071] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" in this article represents any one of a plurality or any combination of at least two of a plurality. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set composed of A, B, and C.

[0072] Figure 1 The structural diagram of an OTP module according to an embodiment of the present disclosure is shown. When the OTP module is disposed in a chip, it is used to configure the chip, and the configuration includes the power-on initialization configuration of the chip. As Figure 1 shown, the OTP module includes: an OTP controller 110, a register 120, and an OTP memory 130.

[0073] In this application, the OTP memory 130 is used to store target data, and the target data includes the data required for the power-on initialization of the chip when the OTP module is disposed in the chip. Since a chip generally has at least one functional module, these functional modules need to use the register 120 to temporarily store data and instructions during operation. Based on this, the chip further includes at least one target register 120. In this embodiment, the target data includes first data, and the first data is used to configure at least one target register 120 in the chip.

[0074] Optionally, the configuration content of the target register 120 includes but is not limited to: configuring the working mode, communication interface, working clock, working parameters, whether to disable, etc. of the corresponding functional module. This embodiment does not limit the configuration content of the target register 120.

[0075] The OTP controller 110 has an open-source abstract interface, enabling software and / or hardware components to interact with the OTP memory 130, thereby programming specific data or code into the OTP memory 130 to manage and operate the OTP memory 130 through the OTP controller 110.

[0076] Optionally, the OTP controller 110 and the OTP memory 130 can be integrated into the same module. In this case, communication between the OTP controller 110 and the OTP memory 130 can be achieved through an internal dedicated interface or an internal bus; alternatively, the OTP controller 110 and the OTP memory 130 exist as independent components. In this case, communication between the OTP controller 110 and the OTP memory 130 can be achieved through an external interface. The implementation manners of the OTP controller 110 and the OTP memory 130 are not limited in this embodiment.

[0077] The register 120 is communicatively connected to the OTP controller 110 and is used to store the instructions executable by the OTP controller 110. Exemplarily, the register 120 stores at least the working sequence (or timing) when the OTP controller 110 loads the target data, so that the OTP controller 110 can load the target data according to this working sequence.

[0078] Optionally, the register 120 and the OTP controller 110 can be integrated into the same module, or they can also exist as independent components separately. The implementation manner of the register 120 is not limited in this embodiment. Figure 1 In this example, the OTP controller 110, the OTP memory 130, and the register 120 are integrated into the same module, and communication between the three is achieved through internal lines for illustration. As Figure 1 shown, the OTP controller 110 includes a finite state machine OTP_Loader FSM and a control unit OTP_CTRL. Among them, the finite state machine is used to control the data loading process of the OTP module according to a preset working sequence. For example, if the preset working sequence includes data verification, parameter calibration, and target register 120 configuration in sequence, then the finite state machine is used to control the data loading process of the OTP module according to this working sequence. The OTP memory 130 is disposed within the control unit, and the control unit is used to manage the read and write operations of the OTP memory 130. The finite state machine is connected to the control unit through an internal signal line, and the control unit is connected to the register 120 through an internal signal line. At this time, the finite state machine reads the working sequence stored in the register 120 through the control unit, and reads the target data stored in the OTP memory 130 through the control unit at each working stage in the working sequence.

[0079] In actual implementation, the connection relationship among the finite state machine, the control unit, the OTP memory 130, and the register 120 can also be in other ways, which is not limited in this embodiment.

[0080] Exemplarily, when the OTP module is disposed in the chip, the OTP module can be connected to the bus of the chip. At this time, the OTP module can either be a master node on the bus system or a slave node on the bus system. Correspondingly, the OTP module includes a first bus interface and a second bus interface. When the OTP module is a master node, data is sent to the bus of the chip through the first bus interface to configure the chip; when the OTP module is a slave node, data is received through the second bus interface to burn data in the OTP module or debug the OTP module.

[0081] For example: Figure 1 In, the first bus interface is the Master BUS, and the first bus interface includes an address interface otp_addr_m, a data interface otp_dout_m, and an enable interface otp_wr_en_m. The second bus interface is the Slave BUS, and the second bus interface includes a write enable interface otp_wr_en_s, a read enable interface otp_rd_en_s, an address interface otp_addr_s, a data input interface otp_din_s, a data interface otp_dout_s, an operation completion interface otp_op_done_s, and a byte write completion interface otp_byte_wr_done_s.

[0082] In actual implementation, the OTP module can also be provided with other interfaces required during use, or fewer interfaces can be provided. For example: Figure 1 In, the OTP module further includes a data interface otp_trim_value, a clock signal input interface i_clk, a reset signal interface i_rst_n, etc. This embodiment does not limit the interfaces of the OTP module for communicating with other devices.

[0083] In one example, the OTP module is used as a master node during the configuration phase of the chip. At this time, the OTP controller 110 (specifically, the finite state machine in the OTP controller 110) is configured to at least perform the following steps when executing the instructions stored in the register 120:

[0084] After the chip is powered on, load the target data stored in the OTP memory 130 according to a preset working sequence;

[0085] In the case of loading the first data, send the first data to the corresponding target register 120 to configure the target register 120;

[0086] When the preset reloading condition is satisfied, the first data is reloaded to trigger the execution of the steps of sending the first data to the corresponding target register 120 and subsequent steps when the first data is loaded, so as to reconfigure the target register 120 again.

[0087] For relevant details, please refer to the method embodiments of the following data loading method.

[0088] In another example, the OTP module is used as a slave node when it is in the programming stage or the debugging stage itself. At this time, in the programming stage, the OTP controller 110 (specifically, the control unit in the OTP controller 110) is configured to at least implement the following steps when executing the instructions stored in the execution register 120:

[0089] Obtain the target data sent by the programming device;

[0090] Store the target data in the OTP memory 130.

[0091] For relevant details, please refer to the method embodiments of the following data programming method.

[0092] In summary, the OTP module provided in this embodiment, on the one hand, can ensure that the target data stored in the OTP memory cannot be cracked by burning the target data into the OTP memory; on the other hand, after the target register is configured by loading the first data, if the preset reloading condition is satisfied, the first data is reloaded to configure the target register again. Even if the configuration data in the target register is tampered with briefly, the configuration data in the target register will be reconfigured due to the reloading mechanism later, so as to ensure that the configured target register cannot be cracked and ensure the security of the chip operation.

[0093] To understand the relationship between the OTP module and the chip more clearly, the structure of the chip will be exemplarily described below. Figure 2 The structural diagram of a chip according to an embodiment of the present disclosure is shown. As Figure 2 shown, the chip includes: an OTP module 100 and a plurality of functional modules 200.

[0094] Each functional module 200 includes at least one target register 210. As Figure 2 shown, the functional modules include but are not limited to: the microprocessor, analog unit, and digital unit in the chip, etc.

[0095] Among them, the microprocessor is the control unit of the chip and is used to control the chip as a whole. The analog unit is used to manage the clock, voltage, etc. of the chip. The analog unit includes analog IP. Usually, the key parameters related to analog have high requirements for timing, and it is necessary to complete the configuration within a short time in the early stage of chip power-on to prevent abnormal chip operation.

[0096] In actual implementation, the type and implementation manner of the functional module 200 are not limited in this embodiment.

[0097] The OTP module 100 is connected to each functional module 200 in the chip through a bus, so as to configure the target registers in each functional module 200 during the chip power-on initialization process.

[0098] In actual implementation, the bus of the chip can also be connected to other devices and interfaces. For example, it can be connected to a storage medium (such as a flash memory Flash) through a Serial Peripheral Interface (SPI), and an IIC SLAVE interface of a slave node based on an Inter-Integrated Circuit (IIC). The implementation manner of the devices and interfaces of the chip is not limited in this embodiment.

[0099] Optionally, since the storage space of the OTP memory in the OTP module 100 is limited, the amount of target data that can be stored is limited. Based on this, the chip in this embodiment is a small-scale chip, that is, the number of functions that the chip can implement is less than or equal to a preset number of functions, or the number of microelectronic devices integrated in the chip is less than a preset number of devices, or the amount of target data required for chip power-on initialization is less than a preset amount of data. The definition method of the small-scale chip is not limited in this embodiment.

[0100] In this application, the target data required during the chip power-on initialization process is pre-burned in the OTP memory in the OTP module. After that, after the chip is powered on, the chip can be configured by loading the target data in the OTP memory. The data burning method and data loading method involved in this application are introduced below in sequence.

[0101] Figure 3 The flowchart of a data burning method according to an embodiment of the present disclosure is shown. This embodiment is described by taking this method as an example for Figure 1 the OTP module shown. As Figure 3 shown, the method includes:

[0102] Step 301, obtain the target data sent by the burning device.

[0103] Before the chip leaves the factory, it is necessary to burn the OTP module used to configure the chip to burn target data in the OTP memory in the OTP module. Among them, the target data includes first data, and the first data is used to configure at least one target register in the chip.

[0104] The burning device interacts with the OTP module through the second bus interface of the OTP module to send the target data to the OTP module through the second bus interface; correspondingly, the OTP module receives the target data sent by the burning device through the second bus interface.

[0105] Exemplarily, the burning device can be connected to the IIC SLAVE interface in the chip and directly access the OTP module through the IIC SLAVE interface in the chip, so as to burn the target data in the OTP memory inside the OTP module. At this time, the IIC SLAVE interface can be connected to the second bus interface of the OTP module.

[0106] Among them, the burning device can be an OTP burner, or a programmer (or called a burner), etc. The implementation manner of the burning device is not limited in this embodiment.

[0107] Step 302, store the target data in the OTP memory.

[0108] The target data is used to reload the first data again when the preset reloading condition is met, so as to trigger the execution of the steps of sending the first data to the corresponding target register and subsequent steps when the first data is loaded, so as to reconfigure the target register. For the relevant description of data loading, please refer to the following data loading embodiment.

[0109] After the OTP module obtains the target data, it stores the target data in the OTP memory according to the instructions of the burning device.

[0110] Optionally, the target data burned into the OTP memory is stored according to a preset storage structure. Exemplarily, the preset storage structure includes: storing according to the loading order during the data loading process, and / or arranging the data with a fixed length before the data with an unfixed length.

[0111] Optionally, if the OTP memory also stores fourth data used when acting as a slave node, the fourth data is stored after the target data. For example: the fourth data is used to indicate chip information, and the fourth data is used to be read by the OTP module when acting as a slave node. The chip information includes but is not limited to: the unique serial number of the chip, and / or production information, etc. The content of the chip information is not limited in this embodiment.

[0112] For example, the target data includes, in addition to the first data, the second data and the third data; meanwhile, the OTP memory also stores the fourth data. Among them, the second data is used to identify whether to start the reloading mechanism, and the data loading order of the second data is before the data loading order of the first data. The third data is used to calibrate the target parameters in the chip, and the data loading order of the third data is before the data loading order of the second data. Storing the target data based on the above preset storage structure can obtain Figure 4 the storage structure shown. According to Figure 4 it can be known that the first data 410, the second data 420, and the third data 430 are before the fourth data 440. The second data 420 is the data loaded first, so the second data 420 is before the first data 410 and the third data 430. The third data 430 is the data loaded after the second data 420 but before the first data 410, so the third data 430 is after the second data 420. At the same time, the lengths of the second data 420 and the third data 430 are usually fixed. For example, the length of the second data 420 can be 1 byte, and the total length of the third data 430 can be 16 bytes; while the length of the first data 410 is not fixed. At this time, the third data 430 is after the second data 420 and the first data 410, so that the design difficulty of the storage structure can be simplified.

[0113] In summary, the data burning method provided in this embodiment obtains the target data sent by the burning device; stores the target data in the OTP memory, so that after the chip to which the OTP memory belongs is powered on, the target data stored in the OTP memory is loaded according to the preset working order; when the first data is loaded, the first data is sent to the corresponding target register to configure the target register; and when the preset reloading condition is met, the step of sending the first data to the corresponding target register and the subsequent steps when the first data is loaded are executed again to configure the target register again; it can ensure that the target data stored in the OTP memory is not cracked and improve the security of chip operation.

[0114] Since the chip may need to be returned to the factory for inspection and evaluation after it is manufactured; or, it is necessary to debug when the chip has problems. At this time, it may be necessary to change the target data stored in the OTP memory.

[0115] In a possible implementation manner, after storing the target data in the OTP memory, it further includes: when it is necessary to update the first data, obtaining the updated first data; storing the updated first data in the OTP memory. At this time, a storage space for storing the updated first data is reserved in the OTP memory to increase the updated first data.

[0116] For example, in the debugging stage after the chip is returned, a patch (i.e., the updated first data) can be sent to the OTP module through a debugging device to enable or disable certain functional modules, or to debug the functional modules with anomalies, so as to solve the anomaly problems. Among them, the debugging device can be the programming device in the above text, or it can also be other devices different from the programming device. The implementation manner of the debugging device is not limited in this embodiment.

[0117] Exemplarily, the first data includes the register address and register data of the target register. Correspondingly, the updated first data includes the updated register data corresponding to any register address; or, the updated first data includes the newly added register address and the newly added register data corresponding to the newly added register address.

[0118] Optionally, the debugging device can interact with the OTP module through the second bus interface of the OTP module to send the updated first data to the OTP module through the second bus interface; correspondingly, the OTP module receives the updated first data through the second bus interface. Before the debugging device sends the updated first data to the OTP module, it can also read the chip information stored in the OTP module to verify the chip.

[0119] In this implementation manner, by storing the updated first data in the OTP memory, patches can be added, so as to achieve flexible control and anomaly debugging of functional modules.

[0120] In another possible implementation manner, the target data further includes third data, and the third data is used to calibrate the target parameters in the chip; the OTP memory includes a storage space for storing at least two groups of third data, and the currently effective third data further has a flag bit. Correspondingly, after storing the target data in the OTP memory, it further includes:

[0121] In the case where it is necessary to update the currently effective third data in the OTP memory, destroy the flag bit of the currently effective third data; obtain the updated third data; set a flag bit for the updated third data, and store the updated third data with the flag bit in the storage space.

[0122] For example, after the chip is manufactured, if the calibration value changes accidentally or the programming fails due to programming errors, the updated third data can be sent to the OTP module through the debugging device to update the calibration parameters. The connection manner between the debugging device and the OTP module and the implementation manner of the debugging device refer to the above embodiments, and will not be elaborated in this embodiment.

[0123] Among them, the methods for destroying the flag bit of the currently effective third data include, but are not limited to: changing the physical structure of the storage location where the flag bit is located in the OTP memory, such as changing the physical structure by fusing a fuse, so as to destroy the flag bit of the third data; or applying a voltage or current greater than a preset threshold to the storage location where the flag bit is located in the OTP memory to destroy the storage location. The present embodiment does not limit the method for destroying the flag bit.

[0124] In this implementation manner, by changing the currently effective third data in the OTP memory, more flexible parameter calibration can be achieved without scrapping the chip.

[0125] Figure 5 The flowchart of a data loading method according to an embodiment of the present disclosure is shown. In this embodiment, it is used as an example for Figure 1 the OTP module shown. As Figure 5 shown, the method includes:

[0126] Step 501, after the chip is powered on, load the target data stored in the OTP memory according to a preset working sequence.

[0127] Among them, the target data includes first data, and the first data is used to configure at least one target register in the chip.

[0128] Exemplarily, the chip is provided with an OTP memory, and the OTP module can obtain the power-on signal of the chip through a pre-set interface, so as to determine whether the chip is powered on. For example: in Figure 1 it, the OTP module includes a reset signal interface i_rst_n. When the chip is not powered on successfully (including not powered on or the power is not stable), the reset signal interface i_rst_n remains low; when the chip is powered on successfully, the reset signal interface i_rst_n releases a high level; in response to the reset signal interface i_rst_n releasing a high level, the finite state machine OTP_Loader FSM in the OTP module starts to work, so as to read the working sequence stored in the register in the OTP module and load the target data stored in the OTP memory according to the working sequence.

[0129] In other embodiments, the OTP module can also determine whether the chip is powered on through other interfaces. The present embodiment does not limit the method for the OTP module to determine whether the chip is powered on.

[0130] Step 502, when the first data is loaded, send the first data to the corresponding target register to configure the target register.

[0131] Exemplarily, the first data includes the register address and register data of the target register; correspondingly, sending the first data to the corresponding target register includes: for each set of first data, driving the read register address to the address interface connected to the bus, and driving the read register data to the data interface connected to the bus; after the first data is read, triggering the enable interface connected to the bus to generate an enable signal to send the memory data at the data interface to the target register indicated by the register address at the address interface.

[0132] According to Figure 1 As can be seen from the OTP module shown, when the OTP module is used as the main node, it sends data to the bus through the first bus interface. The first bus interface includes the address interface otp_addr_m, the data interface otp_dout_m, and the enable interface otp_wr_en_m. At this time, for each set of first data corresponding to each target register, the register address in this set of first data is driven to the address interface otp_addr_m, the register data in this set of first data is driven to the data interface otp_dout_m, and after this set of first data is read, the enable interface otp_wr_en_m is triggered to generate an enable signal, so as to be sent to the target register in the chip through the bus to complete the configuration of the target register; then, for the next set of first data corresponding to the next target register, the above operations are repeated until the first data in the OTP module is read and completed.

[0133] Optionally, since the length of the first data is not fixed, for example: for different chips or different users, the length of the first data may be different. Therefore, in order to be able to indicate whether the first data is read and completed, an end flag can be set at a storage location after each set of first data in the OTP memory. In this way, when the OTP module reads this end flag, it can determine that all the first data has been read and completed, and the configuration of each target register is ended.

[0134] Among them, the end flag can be implemented by an empty ID. For example: the end flag is 0XA0. At this time, when the OTP module reads the ID value of the register address, if the returned value is equal to 0XA0, it means that the register configuration is ended, and the finite state machine automatically enters the next state.

[0135] Optionally, referring to Figure 6 the first data corresponding to each target register shown, according to Figure 6It can be known that the first data register address in a group of first data corresponding to the target register can be split into a register identity (ID) and an offset address Offset. At this time, a group of first data corresponding to each target register forms a data packet, and this data packet contains an ID value, an offset address, and register data. The ID value of the register identity is usually fixed, but the offset address and register data are usually not fixed. In actual use, according to the offset address bit width and the register data bit width, the packet byte bit width is adjusted. At this time, how many target registers in the chip can be specifically configured depends on the capacity of the OTP memory. That is, in this embodiment, for each target register configured through the OTP module, the data volume of the first data corresponding to each target register is less than the capacity of the OTP memory.

[0136] Step 503, when the preset reloading condition is satisfied, reload the first data again to trigger the execution of the step of sending the first data to the corresponding target register and subsequent steps when the first data is loaded, so as to reconfigure the target register.

[0137] The reloading condition at least includes that the target data is loaded once. Optionally, the reloading condition may further include: the timer duration triggered after the chip is powered on reaches a preset duration, and this preset duration is greater than the total duration of the target data being loaded once; at this time, the OTP module does not need to immediately reload the first data every time the data loading is completed, which can save the chip power consumption and also save the bus occupancy rate.

[0138] Optionally, the preset duration is less than the shortest duration that the user can perceive that the target register is rewritten. For example: the preset duration can be a value between 100 us and 1 ms, serving as the excitation signal for the OTP module to reload the target data.

[0139] In this embodiment, taking the reloading condition including that the target data is loaded once and the timer duration triggered after the chip is powered on reaches the preset duration as an example for illustration. At this time, before step 503, the OTP module also needs to determine whether the preset reloading condition is satisfied, that is, to determine whether the target data is loaded once and whether the timer duration reaches the preset duration; if the target data is loaded once and the timer duration reaches the preset duration, then the preset reloading condition is satisfied, and the steps of loading the target data stored in the OTP memory according to the preset loading order in step 501 and subsequent steps are executed again.

[0140] Exemplarily, the first data is the last loaded data of the work order indication. Correspondingly, determining whether the target data is loaded includes: if an end flag is read, it is determined that the target data is loaded.

[0141] In other embodiments, if the first data is not the last-loaded data indicated by the working order, a load completion flag may be set after the last-loaded data, and the load completion flag is different from the end flag; or, if the length of the last-loaded data is fixed, when the finite state machine is in the stage of the last-loaded data and the corresponding length of data is read, it is determined that the target data loading is completed. This embodiment does not limit the determination method for the completion of the target data loading.

[0142] In one example, after the chip is powered on and it is determined to start the reloading mechanism, the timer starts timing, and when the timer duration reaches the preset duration, the rising edge of the timing signal is output to trigger the finite state machine to reload the target data. At this time, the target data further includes second data, which is used to identify whether to start the reloading mechanism, and the data loading order of the second data is before the data loading order of the first data. Accordingly, before step 502, it further includes:

[0143] When the second data is loaded, it is determined whether the second data is the same as a preset identifier; when the second data is the same as the preset identifier, the reloading mechanism is started to reload the first data again when the preset reloading conditions are met, so as to trigger the execution of the step of sending the first data to the corresponding target register and subsequent steps when the first data is loaded.

[0144] In this embodiment, whether to start the reloading mechanism is determined by the second data, so that the OTP module can flexibly set the second data according to the reloading requirements of the chip to meet various requirement scenarios.

[0145] In this embodiment, the preset identifier (or password) is stored in a register. When the finite state machine runs to the stage of loading the second data, the preset identifier can be read from the register and the second data is compared with the preset representation.

[0146] Among them, the preset identifier may be one byte. For example, the preset identifier is 0XF0. In actual implementation, the preset identifier may also be more bytes or other implementation manners. This embodiment does not limit the implementation manner of the preset identifier.

[0147] Exemplarily, starting the reloading mechanism includes: starting the timer to obtain the timer duration; when the timer duration of the timer reaches the preset duration, timing starts again. Since the target data has been fully loaded once, each time the timer duration reaches the preset duration, the OTP module is triggered to reload the first data, thereby realizing repeated configuration of the target register.

[0148] Optionally, when the second data is different from the preset identifier, the reloading mechanism is not started. After the target data is loaded once, the process ends, and step 501 is executed again until the chip is powered on again.

[0149] In other implementation manners, the OTP module may also not set the second data, but default that the reloading mechanism is always started. At this time, the timer may also start timing after the chip is powered on. This embodiment does not limit the implementation manner of the reloading mechanism and the starting timing of the timer.

[0150] In summary, the data loading method provided in this embodiment loads the target data stored in the OTP memory according to a preset working order after the chip is powered on; when the first data in the target data is loaded, the first data is sent to the corresponding target register to configure the target register; when the preset reloading condition is met, the first data is loaded again to trigger the execution of the step of sending the first data to the corresponding target register and subsequent steps when the first data is loaded, so as to configure the target register again; on the one hand, by burning the target data into the OTP memory, it can be ensured that the target data stored in the OTP memory cannot be cracked; on the other hand, the first data in the OTP memory can be repeatedly used to configure the target register. In this way, even if the configuration data in the target register is tampered with briefly, the configuration data in the target register will be reconfigured due to the reloading mechanism. Without scrapping the chip, it is ensured that the configured target register cannot be cracked, thereby ensuring the security of the chip operation.

[0151] In addition, by setting the second data to identify whether to start the reloading mechanism, the OTP module can flexibly set the second data according to the reloading requirements of the chip to meet various requirement scenarios.

[0152] In addition, by setting the reloading condition to include that the target data is loaded and the timer duration triggered after the chip is powered on reaches the preset duration, the OTP module does not need to reload immediately every time the target is loaded, which can save chip power consumption and also save the bus occupancy rate.

[0153] In a possible implementation manner, the target data further includes third data, and the third data is used to calibrate the target parameters in the chip. Correspondingly, after step 501, it further includes:

[0154] When the third data is loaded, the third data is sent to the parameter interface corresponding to the target parameter in the chip to calibrate the target parameter. Generally, the default value of the target parameter is stored in the chip. After the parameter interface of the chip obtains the third data, the third data is used for parameter calibration on the basis of the default value.

[0155] Since the target parameters are used to ensure the stable operation of the chip, such as the voltage, clock, and related analog interfaces of the precision chip, so as to ensure the normal operation of the chip. Therefore, in order to ensure the stable progress of the subsequent data loading process, in one example, the loading order of the third data is before the loading order of the first data.

[0156] When loading the third data, exemplarily, the third data is sent to the parameter interface corresponding to the target parameter in the chip, including: driving the third data to the data interface connected to the dedicated line, so as to send the third data to the parameter interface through the dedicated line.

[0157] According to Figure 1 it is known that the OTP module further includes a data interface otp_trim_value, and this data interface is connected to the parameter interface through a dedicated line (i.e., non-bus), so that the third data can be sent to the parameter interface through the dedicated line. At this time, the transmission of the third data does not need to pass through the bus, which can avoid the processes of bus decoding and arbitration, thereby reducing the configuration time of the calibration parameters.

[0158] In other embodiments, the third data can also be sent to the parameter interface through the data interface otp_dout_m in the first bus interface. This embodiment does not limit the sending method of the third data.

[0159] Optionally, in order to avoid the need to adjust the calibration value again due to special circumstances, the OTP memory includes a storage space for storing at least two groups of third data. Correspondingly, the currently effective third data also has a flag bit, and the flag bit is used to identify that the third data is currently effective; correspondingly, when the OTP module loads the third data, it loads the third data with the flag bit in the storage space for storing at least two groups of third data.

[0160] For example: referring to Figure 4 , storage spaces Group1 and Group2 for two groups of third data are set. If the OTP module burns the third data in Group1 during the burning stage, then Group1 has a flag bit, and the chip uses the third data in Group1 for parameter calibration. After that, according to the above embodiments, it is known that the OTP module can receive the updated third data. At this time, the updated third data can be burned into Group2, and the flag bit of Group1 is destroyed, and a flag bit is written in Group2 to complete the activation of Group2. The bit width and value of the flag bit can be set according to requirements. For example, the flag bit is a random byte.

[0161] Optionally, if the target data further includes third data and the loading order of the third data is before the loading order of the first data, then when the reloading condition in the above embodiments is satisfied (for example: after the target data is loaded once and the timer duration triggered after the chip is powered on reaches the preset duration), the OTP module can also reload the third data again to trigger the execution of the steps of sending the third data to the parameter interface corresponding to the target parameter in the chip when the third data is loaded and subsequent steps, so as to calibrate the parameters in the chip again. At this time, after the OTP module finishes loading the third data, it will continue to reload the first data again, and when the first data is loaded and the timer duration of the timer reaches the preset duration, it will reload the third data again.

[0162] In other embodiments, the loading order of the third data can also be after the loading order of the first data. At this time, when the preset reloading condition is satisfied, the OTP module reloads the first data again. After finishing loading the third data, it will continue to reload the third data again, and when the third data is loaded and the timer duration of the timer reaches the preset duration, it will reload the first data again. This embodiment does not limit the loading order between the first data and the third data.

[0163] In this embodiment, by setting two groups of third data through redundant design and flagging the currently valid third data with a flag bit, the parameter calibration value can be adjusted without scrapping the chip, which can improve the flexibility of parameter calibration.

[0164] In a possible implementation manner, loading the target data stored in the OTP memory according to the preset working order further includes: reading the target data; performing data verification on the target data; after the data verification passes, triggering the execution of the steps after step 501 in the above embodiments, including triggering the execution of the steps of sending the first data to the corresponding target register to configure the target register when the first data is loaded and subsequent steps.

[0165] Among them, the data verification can be Cyclic Redundancy Check (CRC). Correspondingly, performing data verification on the target data includes: substituting the target data into a preset verification polynomial to obtain a verification value. Optionally, the verification value can be stored in the register of the OTP module to determine whether there is an abnormality in the target data when debugging the chip.

[0166] In this embodiment, by performing chip configuration only after the data verification of the target data passes, it can be determined whether there is an abnormality in the target data, improving the efficiency of subsequent determination of target data abnormalities.

[0167] To better understand the data loading method provided in this embodiment, the following example is given where the target data includes first data, second data, and third data, the working order is to load the second data first, then the third data, and finally the first data, and data verification needs to be performed on the target data. At this time, refer to Figure 7 , the finite state machine in the OTP module includes 6 states, namely: idle state IDLE, data verification state CRC_CHECK, second data reading state RELOAD_FLAG, third data reading state CHIP_TRIM, first data packetizing state REG_ADDR, and REG_DATA. The state transition process of the finite state machine includes:

[0168] 1) The finite state machine in the chip is default in IDLE. After the chip is powered on and the OTP module receives the signal indicating that the chip power-on is complete, it jumps to CRC_CHECK.

[0169] 2) In the CRC_CHECK state, all data (including target data) inside the OTP memory is read to complete data CRC verification, and the verification value is written into the register, then it jumps to RELOAD_FLAG.

[0170] 3) In the RELOAD_FLAG state, the second data at a specific position inside the OTP memory is read, and the value of the second data is compared with a preset identifier to determine whether the chip starts the reloading mechanism, then it jumps to RELOAD_FLAG. If the chip starts the reloading mechanism, each time the chip reads the end flag in the REG_DATA state, it switches to the CHIP_TRIM state to trigger a new round of register configuration and chip parameter calibration.

[0171] 4) After the data comparison is completed in the RELOAD_FLAG state, it jumps to CHIP_TRIM.

[0172] 5) In the CHIP_TRIM state, the third data stored inside the OTP memory is read and directly reaches the target parameter interface through the data interface "otp_trim_value", so that the chip calibrates the parameters based on the default value, accurately adjusts the voltage, clock, and related analog interfaces of the chip, and ensures the normal operation of the chip, then it jumps to REG_ADDR.

[0173] 6) In the REG_ADDR state, after reading a register address, it jumps to REG_DATA to read the register data corresponding to the register address; after REG_DATA reads the register data, it jumps to REG_ADDR, reads the next register address, and then jumps to REG_DATA again to read the register data corresponding to the next register address, and so on in a loop. When the reload mechanism RELOAD is started, when REG_ADDR reads the end flag, if the timer duration reaches the preset duration, it switches to the CHIP_TRIM state and executes step 4) and subsequent state transitions again. If the reload mechanism RELOAD is turned off, it switches to the IDLE state when REG_ADDR reads the end flag, and the process ends.

[0174] According to the above process, it can be seen that the OTP module is periodically reloaded, and the target register can be repeatedly configured. Therefore, no matter how the target register is modified, the OTP module will periodically overwrite the configuration data in the target register, making the values of these target registers unable to be modified, fundamentally ensuring that the target register cannot be cracked, thereby ensuring the security of the chip operation.

[0175] Although the steps and the order of the steps of the embodiments of the present invention are given in the method and the method diagram, the executable instructions for implementing the specified logical functions of the steps can be recombined to generate new steps. The order of the steps should not be limited only to the order of the steps in the method and the method diagram, and can be adjusted at any time according to the needs of the function. For example, some of the steps can be executed in parallel or in the reverse order.

[0176] Figure 8 The block diagram of a data loading device according to an embodiment of the present disclosure is shown. A one-time programmable OTP memory is provided in the chip, such as Figure 8 shown, the device includes: a data reading module 810, a data sending module 820, and a reload module 830.

[0177] The data reading module 810 is configured to load the target data stored in the OTP memory according to a preset working order after the chip is powered on; wherein, the OTP memory is provided in the chip, and the target data includes first data, and the first data is used to configure at least one target register in the chip;

[0178] The data sending module 820 is configured to send the first data to the corresponding target register to configure the target register when the first data is loaded;

[0179] Reload module 830 is used to reload the first data again when a preset reloading condition is met, so as to trigger the execution of the step of sending the first data to the corresponding target register and subsequent steps when the first data is loaded, so as to reconfigure the target register.

[0180] Optionally, the target data further includes second data, which is used to identify whether to start the reloading mechanism, and the data loading order of the second data is before the data loading order of the first data; correspondingly, the device further includes: a data comparison module and a mechanism start module.

[0181] The data comparison module is used to determine whether the second data is the same as a preset identifier when the second data is loaded;

[0182] The mechanism start module is used to start the reloading mechanism when the second data is the same as the preset identifier, so as to trigger the execution of the step of reloading the first data again when a preset reloading condition is met and subsequent steps.

[0183] Optionally, the reloading condition includes: the target data is loaded once, and the timer duration triggered after the chip is powered on reaches a preset duration; wherein, the preset duration is greater than the total duration of the target data being loaded once;

[0184] Correspondingly, the mechanism start module is used for:

[0185] Start a timer to obtain the timer duration; when the timer duration of the timer reaches the preset duration, the timer starts timing again.

[0186] Optionally, the first data includes the register address and register data of the target register; correspondingly, the data sending module 820 is used for:

[0187] For each group of first data, drive the read register address to the address interface connected to the bus, and drive the read register data to the data interface connected to the bus;

[0188] After the first data is read, trigger the enable interface connected to the bus to generate an enable signal, so as to send the memory data at the data interface to the target register indicated by the register address at the address interface.

[0189] Optionally, the target data further includes third data, which is used to calibrate the target parameters in the chip; correspondingly,

[0190] The data sending module 820 is further configured to, when the third data is loaded, send the third data to the parameter interface corresponding to the target parameter in the chip to calibrate the target parameter;

[0191] The reloading module 830 is further configured to, when a preset reloading condition is satisfied, reload the third data to trigger the execution of the step of sending the third data to the parameter interface corresponding to the target parameter in the chip and subsequent steps when the third data is loaded, so as to calibrate the target parameter again.

[0192] Optionally, the OTP memory includes a storage space for storing at least two sets of third data. Correspondingly, the currently effective third data also has a flag bit, and the flag bit is used to identify that the third data is currently effective;

[0193] Correspondingly, the data reading module 810 is further configured to:

[0194] Load the third data with the flag bit in the storage space.

[0195] Optionally, the data sending module 820 is specifically configured to:

[0196] Drive the third data to a data interface connected to a dedicated line, and send the third data to the parameter interface through the dedicated line.

[0197] Optionally, the data reading module is further configured to:

[0198] Read the target data;

[0199] Perform data verification on the target data and store the verification value obtained from the data verification.

[0200] For the relevant description of this embodiment, see the embodiment of the above data loading method.

[0201] Figure 9 The block diagram of a data programming device according to an embodiment of the present disclosure is shown. As Figure 9 shown, the device includes: a data acquisition module 910 and a data storage module 920.

[0202] The data acquisition module 910 is configured to acquire target data sent by a programming device; wherein, the target data includes first data, and the first data is used to configure at least one target register in the chip;

[0203] A data storage module 920 is configured to store the target data in an OTP memory, so that after the chip to which the OTP memory belongs is powered on, the target data stored in the OTP memory is loaded according to a preset working sequence; when the first data is loaded, the first data is sent to a corresponding target register to configure the target register; and when a preset reloading condition is satisfied, the first data is loaded again to trigger the execution of the step of sending the first data to the corresponding target register and subsequent steps when the first data is loaded, so as to configure the target register again.

[0204] Optionally, after storing the target data in the OTP memory,

[0205] the data acquisition module 910 is further configured to acquire updated first data when the first data needs to be updated;

[0206] the data storage module 920 is further configured to store the updated first data in the OTP memory.

[0207] Optionally, the target data further includes third data for calibrating target parameters in the chip; the OTP memory includes a storage space for storing at least two groups of third data, and the currently effective third data further has a flag bit;

[0208] Accordingly, after storing the target data in the OTP memory,

[0209] a data destruction module is configured to destroy the flag bit of the currently effective third data in the OTP memory when the currently effective third data in the OTP memory needs to be updated;

[0210] the data acquisition module 910 is further configured to acquire updated third data;

[0211] the data storage module 920 is further configured to set a flag bit for the updated third data and store the updated third data with the flag bit in the storage space.

[0212] For the relevant description of this embodiment, see the embodiment of the above data burning method.

[0213] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the methods described in the method embodiments above. The specific implementation can refer to the description of the method embodiments above. For the sake of brevity, it will not be repeated here.

[0214] In one example, the present embodiment further provides a display device, which includes a plurality of display units and at least one chip including the OTP module in the above embodiment.

[0215] Optionally, the display unit includes a display panel, and the display panel includes at least one of a liquid crystal display panel, a micro light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electro-wetting display panel, and a small-pitch display panel.

[0216] Optionally, the above chip and display device can be applied to an electronic device. Exemplarily, the electronic device in the present embodiment includes, but is not limited to, a desktop computer, a television, a mobile device with a large-size screen such as a mobile phone, a tablet computer, and other common electronic devices that require multiple chips to be cascaded and connected to achieve driving.

[0217] Exemplarily, the electronic device can also be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device, or a vehicle-mounted device, etc. Exemplarily, some examples of terminals are: a display, a smart phone or a portable device, a mobile phone, a tablet computer, a laptop computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, a wireless terminal in a vehicle-to-everything network, etc. For example, the server can be a local server or a cloud server.

[0218] In an exemplary embodiment, a non-volatile computer-readable storage medium is further provided, such as a register including computer program instructions, and the above computer program instructions can be executed by an OTP controller to complete the above method.

[0219] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

[0220] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0221] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0222] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0223] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A data loading method, characterized in that: The method comprises: After the chip is powered on, target data stored in a one-time programmable (OTP) memory is loaded according to a preset working order; wherein the OTP memory is provided in the chip, and the target data includes first data, and the first data is used to configure at least one target register in the chip; In the case of loading the first data, sending the first data to the corresponding target register to configure the target register; When a preset reloading condition is met, the first data is loaded again to trigger the step of sending the first data to the corresponding target register when the first data is loaded and subsequent steps to configure the target register again.

2. The method according to claim 1, characterized in that The target data further includes second data, the second data being used to identify whether to start the reloading mechanism, and the data loading sequence of the second data being before the data loading sequence of the first data; Accordingly, the method further comprises: In the case of loading the second data, determining whether the second data is identical to a preset identifier; When the second data is identical to the preset identifier, the reloading mechanism is started to trigger the step of reloading the first data and subsequent steps when the preset reloading condition is met.

3. The method according to claim 2, characterized in that The reloading condition includes: the target data is loaded once, and the timer triggered after the chip is powered on reaches a preset time; wherein the preset time is greater than the total time of the target data loading once; Accordingly, starting the reloading mechanism includes: Start the timer to obtain the timer duration; restart the timer when the timer duration reaches the preset duration.

4. The method according to claim 1, characterized in that The first data includes a register address and register data of the target register; Accordingly, sending the first data to the corresponding target register includes: For each set of first data, the read register address is driven to an address interface connected to the bus, and the read register data is driven to a data interface connected to the bus; After the first data is read, an enable interface connected to the bus is triggered to generate an enable signal to send the memory data at the data interface to the target register indicated by the register address at the address interface.

5. The method according to claim 1, characterized in that The target data also includes third data, and the third data is used to calibrate the target parameters in the chip; Accordingly, the method further comprises: When the third data is loaded, the third data is sent to a parameter interface corresponding to the target parameter in the chip to calibrate the target parameter; When the reloading condition is met, the third data is loaded again to trigger the step of sending the third data to the parameter interface corresponding to the target parameter in the chip when the third data is loaded and subsequent steps to calibrate the target parameter again.

6. The method according to claim 5, characterized in that The OTP memory includes a storage space for storing at least two sets of third data. Accordingly, the currently effective third data also has a flag bit, and the flag bit is used to identify that the third data is currently effective; Accordingly, the method further comprises: The third data having the flag bit is loaded into the storage space.

7. The method according to claim 5, characterized in that The sending the third data to a parameter interface corresponding to the target parameter in the chip includes: The third data is driven to a data interface connected to a dedicated line, so as to send the third data to the parameter interface through the dedicated line.

8. The method according to any one of claims 1 to 7, characterized in that: The loading of the target data stored in the OTP memory according to a preset working order includes: Reading the target data; Perform data verification on the target data, and store a verification value obtained by the data verification.

9. A data burning method, characterized in that: The method comprises: Acquire target data sent by the burning device; wherein the target data includes first data, and the first data is used to configure at least one target register in the chip; The target data is stored in an OTP memory, so that after the chip to which the OTP memory belongs is powered on, the target data stored in the OTP memory is loaded according to a preset working order; when the first data is loaded, the first data is sent to a corresponding target register to configure the target register; and when a preset reloading condition is met, the first data is loaded again to trigger the execution of the step of sending the first data to the corresponding target register when the first data is loaded and subsequent steps to configure the target register again.

10. The method according to claim 9, characterized in that After storing the target data in the OTP memory, the method further includes: When the first data needs to be updated, obtaining the updated first data; The updated first data is stored in the OTP memory.

11. The method according to claim 9, characterized in that The target data also includes third data, and the third data is used to calibrate the target parameters in the chip; the OTP memory includes a storage space for storing at least two sets of third data, and the currently effective third data also has a flag bit; Correspondingly, after storing the target data in the OTP memory, the method further includes: When the third data currently in effect in the OTP memory needs to be updated, destroying the flag bit of the third data currently in effect; Obtain updated third data; A flag bit is set for the updated third data, and the updated third data with the flag bit is stored in the storage space.

12. An OTP module, characterized in that: The OTP module includes: OTP controller; A register for storing executable instructions of the OTP controller; An OTP memory, the OTP memory being used to store target data, the target data comprising first data, the first data being used to configure at least one target register in a chip to which the OTP module belongs; The OTP controller is configured to implement the method described in any one of claims 1 to 8 when executing the instruction stored in the register; or to implement the method described in any one of claims 9 to 11.

13. A chip, characterized in that: The chip comprises the OTP module according to claim 12.

14. A display device, characterized in that: The device comprises a plurality of display units and at least one chip according to claim 13 .

15. The display device according to claim 14, characterized in that The display unit includes a display panel, and the display panel includes at least one of a liquid crystal display panel, a micro light emitting diode display panel, a light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel and a small pitch display panel.

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