Clock grid structure design method with two-level clock spine

Abstract

A clock grid structure design method for a two-level clock spine comprises: constructing a first-level master clock spine structure in a grid clock usage area; wherein the area includes multiple grid clock domain timing devices; the first-level master clock spine structure includes a balancing tree and a master clock spine line driven by it, the master clock spine line extending as a whole along a first direction and running through the entire grid clock usage area; constructing a second-level slave clock spine structure group; the second-level slave clock spine structure group includes a plurality of second-level slave clock spine structures, the second-level slave clock spine structure includes a balancing tree and a slave clock spine line driven by it, the slave clock spine lines being generally perpendicular to the first direction; short-circuiting the second-level slave clock spine structure group via multiple metal short-circuit lines to form a clock grid structure; the clock grid structure of the present invention is simple to implement, occupies less layout and wiring resources, and has low power consumption, while also having the advantages of strong chip layout adaptability and good scalability.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit clock grid design, and in particular to a clock grid structure design method for a two-level clock spine. Background Art

[0002] In advanced semiconductor processes, such as FinFET / GAA, process fluctuations significantly impact the performance and yield of integrated circuits. Clock mesh technology effectively suppresses the impact of on-chip fluctuations on clock paths and is a crucial clock structure in high-performance integrated circuit design. Existing clock mesh technology has the following limitations: 1) Clock meshes utilize one or more multi-layered mesh structures, each typically a two-dimensional uniform structure consisting of two perpendicularly intersecting metal layers. This consumes significant layout and routing resources during implementation, resulting in significant power consumption. 2) To reduce clock skew and short-circuit current on the clock mesh, strict requirements are placed on the regularity of the clock mesh driver components and their interconnects. For example, H-tree / X-tree structures are required as driver circuits to uniformly cover the entire clock mesh area. However, this type of structure is too idealistic. In complex, high-performance integrated circuits, there are a wide range of functional units, including memories, hardened sub-modules, PLL / PHY and other IP modules, that vary in size, shape, and layout and routing requirements. This makes achieving the aforementioned regularity very difficult. 3) Existing clock grid solutions have poor flexibility and scalability. Once the chip layout changes during the design process, complex adjustments to the clock grid lines and their drive circuits are required to restore their regularity. In certain cases, it is even difficult to converge to the ideal result. Summary of the Invention

[0003] The purpose of the present invention is to provide a clock grid structure design method for a two-level clock spine. The clock grid structure based on this method is simple to implement, occupies less layout and wiring resources, and has low power consumption. At the same time, it has the advantages of strong chip layout adaptability and good scalability.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions:

[0005] A method for designing a clock grid structure of a two-level clock spine, the method comprising:

[0006] Constructing a primary master clock spine structure in a grid clock usage area; wherein the grid clock usage area includes multiple grid clock domain timing devices including registers, memories, etc.; the primary master clock spine structure includes a balancing tree and a master clock spine line driven by the balancing tree, wherein the master clock spine line generally extends along a first direction and runs through the entire grid clock usage area;

[0007] Constructing a secondary slave clock spine structure group; the secondary slave clock spine structure group includes a plurality of secondary slave clock spine structures, each of which includes an independent balancing tree and a slave clock spine line driven by the tree, wherein the slave clock spine line extends in a direction generally perpendicular to the first direction and runs through the entire grid clock usage area; the root nodes of each balancing tree driving the slave clock spine structure group are respectively connected to the master clock spine line as loads;

[0008] Short-circuiting the secondary slave clock spine structure group through a plurality of metal short-circuit lines and running through the entire grid clock use area to form a clock grid structure;

[0009] The clock spine line is constructed as follows:

[0010] Obtaining a timing graph (Timing Graph) of the grid clock domain timing device in a static timing analysis phase;

[0011] Obtaining a distribution area of each sequential device according to the timing diagram, so that the device can meet the requirements of path timing constraints when serving as a capture path node and a launch path node within the distribution area, and calculating the center point of each sequential device distribution area;

[0012] The multiple center points are divided into K groups using the K-Means clustering algorithm, and a slave clock spine line is assigned to each group of center points so that the mean square error of the distance from each group of center points to the corresponding slave clock spine line is minimized.

[0013] Preferably, the number K of slave clock spine lines and the number of equalizing tree buffer device stages driving the slave clock spine lines are simulated using EDA tools such as Spectre / FineSim to obtain minimum clock skew and minimum clock path delay as optimization targets.

[0014] Preferably, the extension direction of the metal short-circuit line is generally perpendicular to the extension direction of the clock spine line;

[0015] The metal short-circuit strip is constructed as follows:

[0016] Obtaining a timing diagram of the grid clock domain timing device in a static timing analysis phase;

[0017] Obtaining a distribution area of each sequential device according to the timing diagram, so that the device can meet the requirements of the path timing constraints when serving as a capture path node and a load path node within the distribution area, and calculating the center point of each sequential device distribution area;

[0018] The multiple center points are divided into N groups using the K-Means clustering algorithm, and a metal short-circuit line is assigned to each group of center points so that the mean square error of the distance from each group of center points to the corresponding metal short-circuit line is minimized.

[0019] After the step of “short-circuiting the secondary slave clock spine structure group through a plurality of metal short-circuit lines and running through the grid clock use area to form a clock grid structure”, the method further includes:

[0020] A plurality of multi-source clock tree subtrees are mounted on the back end of the clock grid to drive a plurality of the grid clock domain timing devices, and the root nodes of the plurality of multi-source clock tree subtrees are respectively mounted on a plurality of the metal short-circuit lines as loads.

[0021] Preferably, the root node of the multi-source clock tree subtree is located near the intersection of the slave clock spine line and the metal short-circuit line.

[0022] Preferably, the balancing trees driving the master / slave clock spine lines are distributed along the master / slave clock spine lines, and the final buffer device of each balancing tree is located directly below the master / slave clock spine lines and directly drives the master / slave clock spine lines.

[0023] A computing device includes: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, the clock grid structure design method of the two-level clock spine is implemented.

[0024] A computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the clock grid structure design method for the two-stage clock spine.

[0025] The advantages of the present invention are:

[0026] The present invention provides a two-level clock spine design method for a clock grid structure. This approach employs a two-level grid consisting of a master clock spine and multiple slave clock spines. Each spine in the master / slave clock spine is a one-dimensional structure driven by its own balancing tree. Compared to traditional clock grid structures, this approach offers the advantages of simpler implementation, reduced layout and routing resources, and lower power consumption. It also offers strong adaptability to chip layouts and excellent scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the main process of a method for designing a clock grid structure of a two-stage clock spine in an embodiment of the present invention;

[0028] Figure 2This is a circuit schematic diagram of a primary master clock spine structure in an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of a layout of a primary master clock spine structure under a regular chip layout according to an embodiment of the present invention;

[0030] Figure 4 1. It is a schematic diagram of the layout of a primary master clock spine structure under a non-regular chip layout according to an embodiment of the present invention;

[0031] Figure 5 1 is a schematic diagram of a layout of a balancing tree root node corresponding to a secondary slave clock spine structure group in an embodiment of the present invention;

[0032] Figure 6 is a schematic diagram of a layout of a secondary slave clock spine structure group in an embodiment of the present invention;

[0033] Figure 7 is a circuit schematic diagram of a capture / load path in an embodiment of the present invention;

[0034] Figure 8 This is a schematic diagram of a distribution area of sequential devices in which a capture / load path satisfies timing constraints in an embodiment of the present invention;

[0035] Figure 9 1 is a schematic diagram of a layout of a metal short-circuit line connection structure according to an embodiment of the present invention;

[0036] Figure 10 It is a schematic diagram of the layout of a multi-source clock tree subtree root node mounting structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] See Figure 1 , which is the main process of a two-level clock spine clock grid structure design method. Figure 1 As shown, the clock grid structure design method of the two-level clock spine provided in this embodiment includes:

[0038] Step S1: Construct a first-level master clock spine structure in the grid clock usage area.

[0039] Specifically, the grid clock signal is sent from the corresponding clock port through the buffer chain to the grid clock use area, and a first-level master clock spine structure is constructed in this area. The master clock spine structure includes a balance tree 1 and a master clock spine line 2 driven by it. The circuit schematic is shown in the figure. Figure 2As shown, the balancing tree 1 is constructed using inverter devices dedicated to the clock grid, and the main clock spine line 2 is constructed using a high-level low-resistance metal layer. The main clock spine line 2 extends along the first direction and runs through the entire grid clock usage area. The balancing tree 1 is distributed along the main clock spine line 2. The final stage device of the balancing tree 1 is located directly below the main clock spine line 2 and directly drives the spine line. The first-level main clock spine can be designed as follows when the layout and routing resources of the main clock spine line 2 and the balancing tree 1 are sufficient and unobstructed. Figure 3 The regular structure shown in the figure (Note: the main clock spine line 2 can pass directly over the hard core module 3 when the wiring resources on the metal layer are sufficient and unobstructed), or it can be designed as follows when resources are limited (for example, the hard core module itself cannot insert the driver devices required by the balance tree 1, or its power / signal lines occupy the wiring resources of the metal layer where the clock grid is located). Figure 4 The irregular structure shown bypasses the resource-constrained area to insert driver devices and lines. In the latter case, only fine-tuning the structure of the single balanced tree 1 itself can maintain the driving capability of the main clock spine line 2.

[0040] Step S2: Construct a secondary slave clock spine structure group.

[0041] Specifically, the secondary slave clock spine structure group includes several secondary slave clock spine structures, and the secondary slave clock spine structure includes a balancing tree 1 and a slave clock spine line 4 driven by the balancing tree 1. Figure 6 The extension direction of the slave clock spine line 4 is generally perpendicular to the first direction and runs through the entire grid clock usage area, that is, the direction of the slave clock spine line 4 is generally perpendicular to the master clock spine line 2. The slave clock spine lines 4 do not need to be completely evenly distributed in space. A single slave clock spine line 4 can also be formed as shown in the following example under resource constraints. Figure 4 The irregular structure of the master clock spine line 2 is shown.

[0042] The slave clock spine line 4 also uses a high-level low-resistance metal layer. Each slave clock spine line 4 is driven by its own independent equalization tree 1 structure. Figure 2 As shown. The root nodes of the balancing trees 1 corresponding to the slave clock spine lines 4 are respectively connected to the master clock spine line 2 as loads. Figure 5 and Figure 6 The black buffer unit in FIG. The construction method of the secondary slave clock spine structure group includes:

[0043] Step S21: Obtaining a timing diagram of a grid clock domain sequential device during a static timing analysis phase. These grid clock domain sequential devices include registers, memories, IP modules, and the like.

[0044] Step 22: Obtain the distribution area of each sequential device in the grid clock domain according to the timing diagram, so that the sequential device can meet the path timing constraint requirements when serving as a capture path node and a load path node within the area, and calculate the center point of the distribution area of each sequential device;

[0045] Step S23: Use the K-Means clustering algorithm to divide multiple center points into K groups, and assign one of the slave clock spine lines 4 to each group of center points, so that the mean square error of the distance from each group of center points to the corresponding slave clock spine line 4 is minimized.

[0046] See Figure 7 and Figure 8 , the construction method of the secondary slave clock spine structure group is explained with an example. Figure 7 is a set of representative timing paths: for register A, the timing path from register B to A constitutes a capture path; the timing paths from register A to C and A to D constitute two loading paths. In order to achieve performance indicators, both the capture path and the loading path must meet the corresponding timing constraints. If there is a margin in the path timing relative to the timing constraint, then register A can find an associated area of the capture path relative to register B, so that the timing change caused by register A moving a certain Manhattan distance within the area will not cause a timing violation; similarly, the associated area of register A relative to the two loading paths of registers C and D can also be found. The overlapping area of the three is the feasible distribution area where register A meets the capture / load timing constraints at the same time ( Figure 8 The green part in the grid clock domain). For each timing device in the grid clock domain, the feasible distribution area is found according to the timing diagram of the static timing analysis phase and the center point of the corresponding distribution area is obtained. Given K slave clock spine lines 4, the center points of each distribution area are divided into K groups through the K-Means clustering algorithm, and each group is assigned a slave clock spine line 4 so that the mean square error of the distance from the center point of each distribution area in the group to the slave clock spine line 4 is minimized (the above ideal position may have physical design rule violations or layout and routing resources have been occupied. In this case, it is necessary to make small adjustments to the spine line in space to obtain a near-optimal result). The number K of slave clock spine lines 4 and the number of buffer levels of the balancing tree 1 that drives the slave clock spine are optimized to obtain the minimum clock skew and the minimum clock path delay. The specific values are obtained through simulation with EDA tools such as Spectre / FineSim.

[0047] Further incremental optimization in the later stages of chip design will cause changes in the positions of timing devices, but most of these changes fall within the corresponding distribution area. Therefore, the center point of the timing device distribution area is selected as the processing object so that the subsequent incremental optimization process will not cause significant fluctuations in design performance and clock grid quality.

[0048] The first-level master clock spine structure and the second-level slave clock spine structure group effectively reduce the number of clock grid lines and weaken the requirements for grid regularity. At the same time, the global optimization adjustment of traditional clock grid lines and driver devices is transformed into local adjustments to multiple independent one-dimensional clock spines, thereby greatly improving the adaptability and scalability of the structure in the design.

[0049] Step S3: short-circuit the secondary slave clock spine structure group through a plurality of metal short-circuit lines to form a clock grid structure.

[0050] Specifically, the extension direction of the metal short-circuit line 5 used for short-circuit connection is generally perpendicular to the extension direction of the clock spine line 4 and runs through the entire grid clock use area, such as Figure 9 and Figure 10 As shown by the green line in , the metal short-circuit line 5 is constructed as follows:

[0051] Step S31: obtaining a timing diagram of a grid clock domain timing device in a static timing analysis phase;

[0052] Step S32: Obtaining the distribution area of each sequential device according to the timing diagram, so that the sequential device can meet the path timing constraint requirements when serving as a capture path node and a load path node within the area, and calculating the center point of each sequential device distribution area;

[0053] Step S33: Use the K-Means clustering algorithm to divide the multiple center points into N groups, and assign a metal short-circuit line 5 to each group of center points, so that the mean square error of the distance from each group of center points to the corresponding metal short-circuit line 5 is minimized.

[0054] The metal short-circuit line 5 is constructed in a similar manner to the slave clock spine line 4 , except that the extension direction of the metal short-circuit line 5 is generally perpendicular to the extension direction of the slave clock spine line 4 .

[0055] Step S4: Connect multiple multi-source clock tree subtrees to the back end of the clock grid to drive multiple grid clock domain timing devices.

[0056] See Figure 10 , the multi-source clock tree subtree 6 is used to drive the corresponding timing device. The root nodes of the multiple multi-source clock tree subtrees 6 (such as Figure 10The orange buffer units in the middle are respectively hung on multiple metal short-circuit lines 5 as loads. Since the construction of the clock spine line 4 and the short-circuit connection line adopts K-Means clustering and achieves the minimum mean square error of the distance between the line and the center point of the corresponding timing device distribution area, it can be considered that these lines are in a relatively central position of each group of timing devices. Preferably, the root node of the multi-source clock tree subtree 6 is hung near the intersection of the clock spine line and the short-circuit connection line. The corresponding generated subtree only drives local timing devices to further reduce on-chip process fluctuations. The transistor-level simulation results of this embodiment show that the clock skew of the root node of each subtree of the multi-source clock tree can be controlled within 10ps under all process corners (Corner).

[0057] An embodiment of the present invention also provides a computing device, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute computer-executable instructions. When the computer-executable instructions are executed by the processor, the clock grid structure design method of the above-mentioned two-level clock spine is implemented.

[0058] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the clock grid structure design method for the two-stage clock spine.

[0059] Those skilled in the art should be able to appreciate that the method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of electronic hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0060] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a parameter, method or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed or inherent to those parameters, methods or apparatus.

[0061] The above are preferred embodiments of the present invention and the technical principles used therein. For those skilled in the art, any obvious changes such as equivalent transformations, simple replacements, etc. based on the technical solution of the present invention, without departing from the spirit and scope of the present invention, are within the scope of protection of the present invention.

Claims

1. A clock grid structure design method for a two-level clock spine, characterized in that: The method comprises: Constructing a primary master clock spine structure in a grid clock usage area; wherein the grid clock usage area includes a plurality of grid clock domain timing devices; the primary master clock spine structure includes a balancing tree and a master clock spine line driven by the balancing tree, the master clock spine line generally extending along a first direction and passing through the entire grid clock usage area; Constructing a secondary slave clock spine structure group; the secondary slave clock spine structure group includes a plurality of secondary slave clock spine structures, each secondary slave clock spine structure including an independent balancing tree and a slave clock spine line driven by the tree, wherein the slave clock spine line extends in a direction generally perpendicular to the first direction; the root nodes of each balancing tree driving the slave clock spine line are respectively connected to the master clock spine line as loads; Short-circuiting the secondary slave clock spine structure group through a plurality of metal short-circuit lines and running through the entire grid clock use area to form a clock grid structure; The clock spine line is constructed as follows: Obtaining a timing diagram of the grid clock domain timing device in a static timing analysis phase; Obtaining the distribution area of each sequential device in the grid clock domain according to the timing diagram, so that the device can meet the requirements of the path timing constraints when serving as a capture path node and a load path node within the region, and calculating the center point of each sequential device distribution area; The multiple center points are divided into K groups using the K-Means clustering algorithm, and a slave clock spine line is assigned to each group of center points so that the mean square error of the distance from each group of center points to the corresponding slave clock spine line is minimized.

2. The clock grid structure design method of the two-level clock spine according to claim 1, characterized in that: The number K of slave clock spine lines and the number of balancing tree buffer levels driving the slave clock spine lines are simulated using transistor-level EDA tools to obtain minimum clock skew and minimum clock path delay as optimization targets.

3. The clock grid structure design method of the two-level clock spine according to claim 1, characterized in that: The extension direction of the metal short-circuit line is generally perpendicular to the extension direction of the clock spine line; The metal short-circuit strip is constructed as follows: Obtaining a timing diagram of the grid clock domain timing device in a static timing analysis phase; Obtaining the distribution area of each sequential device in the grid clock domain according to the timing diagram, so that the device can meet the requirements of the path timing constraints when serving as a capture path node and a load path node within the distribution area, and calculating the center point of each of the sequential device distribution areas; The multiple center points are divided into N groups using the K-Means clustering algorithm, and one metal short-circuit line is assigned to each group of center points so that the mean square error of the distance from each group of center points to the corresponding metal short-circuit line in the group is minimized.

4. The clock grid structure design method of the two-level clock spine according to claim 1, characterized in that: After the step of “short-circuiting the secondary slave clock spine structure group through a plurality of metal short-circuit lines and running through the grid clock use area to form a clock grid structure”, the method further includes: A plurality of multi-source clock tree subtrees are mounted on the back end of the clock grid to drive a plurality of the grid clock domain timing devices, and the root nodes of the plurality of multi-source clock tree subtrees are respectively mounted on a plurality of the metal short-circuit lines as loads.

5. The clock grid structure design method of the two-level clock spine according to claim 4, characterized in that: The root node of the multi-source clock tree subtree is located near the intersection of the slave clock spine line and the metal short-circuit line.

6. The clock grid structure design method of the two-stage clock spine according to claim 1, characterized in that: The balancing tree driving the master / slave clock spine line is distributed along the master / slave clock spine line. The final stage device of the balancing tree is located directly below the master / slave clock spine line and directly drives the master / slave clock spine line.

7. A computing device comprising: memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, the clock grid structure design method of the two-level clock spine described in any one of claims 1 to 6 is implemented.

8. A computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions, when executed by a processor, implement the clock grid structure design method of the two-stage clock spine according to any one of claims 1 to 6.

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