Structure, method and device for monitoring electrical thickness of gate oxide layer and computer equipment

Abstract

The invention provides a gate oxide electrical thickness monitoring structure, method and device and computer equipment, the structure comprises a first MOS structure and a second MOS structure which are arranged at an interval, in the first MOS structure, a first polar plate is formed above a source drain region, a second polar plate is formed above a channel region, and a gate on the second polar plate and the source drain region have a first overlapping region; in the second MOS structure, a third polar plate is formed above the source-drain region, a fourth polar plate is formed above the channel region, and a grid on the fourth polar plate and the source-drain region have a second overlapping region; in the channel direction, the distance between any point on the first pole plate and the second pole plate is the same as the distance between a corresponding point on the third pole plate and the fourth pole plate, the area of the first overlapping region is the same as that of the second overlapping region, and compared with the grid region on the fourth pole plate, the grid region on the second pole plate is the same in grid width and different in grid length. According to the invention, the accurate electrical thickness of the gate oxide layer can be calculated.

Description

Technical Field

[0001] This application belongs to the technical field of semiconductor design and production, and particularly relates to a structure, method, device, and computer equipment for monitoring the electrical thickness of a gate oxide layer. Background Art

[0002] With the development of semiconductor manufacturing processes, device sizes are continuously shrinking, and the thickness of the gate oxide layer is also becoming smaller and smaller. This parameter has a great impact on device performance. Therefore, strict requirements are imposed on the precise control of the physical thickness of the gate oxide layer in the process, and correspondingly, effective and accurate monitoring is particularly important for judging the process capabilities.

[0003] Generally, the method for monitoring the thickness of the gate oxide layer is usually to measure the thickness using an optical method after the gate oxide layer deposition process. In the actual process, the gate oxide layer may regrow during other processes after deposition, resulting in a greater thickness of the final gate oxide layer than when it was just deposited. Therefore, since this measurement method can only be directly performed after deposition, it cannot characterize the final thickness of the gate oxide layer.

[0004] Another method for monitoring the thickness of the gate oxide layer is to measure the capacitance of the MOS device in the strong inversion state and calculate the equivalent thickness of the gate oxide layer, that is, the electrical thickness of the gate oxide layer. This measurement is performed after all processes are completed. Therefore, it can truly reflect the final thickness of the gate oxide layer. However, due to the presence of parasitic capacitance in the MOS device in addition to the gate oxide capacitance, the measured gate oxide capacitance will have a deviation, resulting in an inaccurate calculation result of the electrical thickness of the gate oxide layer.

[0005] Currently, no effective solution has been proposed for the problem of the influence of parasitic capacitance on the measurement accuracy of the gate oxide layer thickness in the related art. Summary of the Invention

[0006] This application provides a structure, method, device, and computer equipment for monitoring the electrical thickness of a gate oxide layer to accurately monitor the electrical thickness of the gate oxide layer.

[0007] To achieve the above object, a structure for monitoring the electrical thickness of a gate oxide layer provided by this application includes: a first MOS structure and a second MOS structure arranged at intervals, wherein, in the first MOS structure, a first electrode plate is formed above the source-drain region, and a second electrode plate is formed above the channel region, and the gate electrode on the second electrode plate has a first overlapping region with the source-drain region; In the second MOS structure, a third electrode plate is formed above the source-drain region, and a fourth electrode plate is formed above the channel region, and the gate electrode on the fourth electrode plate has a second overlapping region with the source-drain region; In the channel direction, the distance between any point on the first electrode plate and the second electrode plate is the same as the distance between the corresponding point on the third electrode plate and the fourth electrode plate. The areas of the first overlapping region and the second overlapping region are the same. Compared with the gate region on the fourth electrode plate, the gate region on the second electrode plate has the same gate width but different gate lengths.

[0008] In some embodiments, the first MOS structure includes: A first source electrode and a first drain electrode, which are respectively connected to a first metal wire through a first contact hole; and a first gate electrode, which is connected to a second metal wire through a second contact hole; The second MOS structure includes: A second source electrode and a second drain electrode, which are respectively connected to a third metal wire through a third contact hole; and a second gate electrode, which is connected to a fourth metal wire through a fourth contact hole; The distance between the first metal wire and the second metal wire is the same as the distance between the third metal wire and the fourth metal wire; the distance between the first contact hole and the second contact hole is the same as the distance between the third contact hole and the fourth contact hole; the distance between the first contact hole and the first gate electrode is the same as the distance between the third contact hole and the second gate electrode; The width of the first gate electrode is equal to the width of the second gate electrode, the length of the first gate electrode is greater than the length of the second gate electrode, and the number of the second contact holes is greater than the number of the fourth contact holes.

[0009] In some embodiments, the first gate electrode has overlapping regions A1 and A2 with the first source electrode and the first drain electrode respectively, and the second gate electrode has overlapping regions B1 and B2 with the second source electrode and the second drain electrode respectively; the areas of the overlapping region A1 and the overlapping region B1 are the same, and the areas of the overlapping region A2 and the overlapping region B2 are the same; The width of the first gate electrode is the same as the width of the second gate electrode, and the length of the first gate electrode is greater than the length of the second gate electrode.

[0010] The present application also provides a method for monitoring the electrical thickness of a gate oxide layer, which is applied to the gate oxide layer electrical thickness monitoring structure as described above, and includes: Determine the area of the first gate oxide layer under the gate region on the second electrode plate and the area of the second gate oxide layer under the gate region on the fourth electrode plate; Determine the first total capacitance of the first MOS structure and the second total capacitance of the second MOS structure; Based on the first total capacitance, the area of the first gate oxide layer, the second total capacitance, and the area of the second gate oxide layer, calculate the electrical thickness of the gate oxide layer of the first MOS structure and the second MOS structure.

[0011] In some embodiments, determining the first total capacitance of the first MOS structure includes: Obtaining a current signal of the first MOS structure, wherein a scan voltage is applied above the gate in the first MOS structure, and the source-drain region is grounded; Integrating the current signal with respect to time to determine the charge quantity; Calculating the first total capacitance according to the scan voltage and the charge quantity.

[0012] In some embodiments, determining the second total capacitance of the second MOS structure includes: Obtaining a current signal of the second MOS structure, wherein a scan voltage is applied above the gate in the second MOS structure, and the source-drain region is grounded; Integrating the current signal with respect to time to determine the charge quantity; Calculating the second total capacitance according to the scan voltage and the charge quantity.

[0013] In some embodiments, calculating the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area includes: Determining a third equivalent capacitance according to the first total capacitance and the second total capacitance, and the third equivalent capacitance does not include parasitic capacitance; Determining a third equivalent gate oxide layer area according to the first gate oxide layer area and the second gate oxide layer area, and the thickness of the third equivalent gate oxide layer is the same as that of the first gate oxide layer and the second gate oxide layer; Calculating the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the third equivalent capacitance, the third equivalent gate oxide layer area, and the capacitance formula.

[0014] In some embodiments, calculating the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area includes: Determining a first parasitic capacitance and a second parasitic capacitance based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area; Determining the electrical thickness of the gate oxide layer of the first MOS structure based on the first total capacitance, the first gate oxide layer area, and the first parasitic capacitance, or determining the electrical thickness of the gate oxide layer of the second MOS structure based on the second total capacitance, the second gate oxide layer area, and the second parasitic capacitance.

[0015] The present application also provides a device for monitoring the electrical thickness of a gate oxide layer, including: a gate oxide layer area determination unit configured to determine a first gate oxide layer area under the gate region on the second electrode plate and a second gate oxide layer area under the gate region on the fourth electrode plate; a total capacitance determination unit configured to determine a first total capacitance of the first MOS structure and a second total capacitance of the second MOS structure; a gate oxide layer electrical thickness calculation unit configured to calculate the electrical thicknesses of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area.

[0016] The present application also provides a computer device, including a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, the steps of the method described above are implemented.

[0017] For the above-mentioned gate oxide layer electrical thickness monitoring structure, method, device, and computer device, by arranging the first MOS structure and the second MOS structure at intervals, the heights of each process section of the first MOS structure and the second MOS structure are made consistent; in the channel direction, the distance between any point on the first electrode plate and the second electrode plate is the same as the distance between the corresponding point on the third electrode plate and the fourth electrode plate, and the gate on the second electrode plate and the source / drain region have a first overlapping region, and the gate on the fourth electrode plate and the source / drain region have a second overlapping region, and the areas of the first overlapping region and the second overlapping region are the same, so that the parasitic capacitances in the first MOS structure and the second MOS structure are kept consistent, including the capacitance C between the gate and the source / drain of , the capacitance C between the contact hole and the gate c2p , the capacitance C between the contact holes c2c , the capacitance C between the metal wire and the contact hole m2c , the C between the metal wire and the gate m2p , the capacitance C between the metal wires m2m , and the over-coverage capacitance C of the gate ov .

[0018] By setting that the gate width of the gate region on the second electrode plate is the same as that of the gate region on the fourth electrode plate, and the gate lengths are different, the difference between the first MOS structure and the second MOS structure lies only in the gate length. Therefore, the parasitic capacitances can be cancelled out by the capacitance measurement results of the first MOS structure and the second MOS structure, and thus the accurate electrical thickness of the gate oxide layer can be calculated. This monitoring structure does not require additional process steps, has good compatibility with the actual semiconductor manufacturing process, and can effectively monitor the final thickness of the gate oxide layer by monitoring the capacitance value, improving the accuracy and efficiency of process monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following-described drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 It is a schematic diagram of the capacitance distribution of the MOS structure in the related art.

[0021] Figure 2 It is a schematic diagram of the gate oxide layer electrical thickness monitoring structure provided in the first embodiment of the present application.

[0022] Figure 3 It is a top view of the first MOS structure in the gate oxide layer electrical thickness monitoring structure provided in the first embodiment of the present application.

[0023] Figure 4 It is a top view of the second MOS structure in the gate oxide layer electrical thickness monitoring structure provided in the first embodiment of the present application.

[0024] Figure 5 It is a schematic flowchart of the gate oxide layer electrical thickness monitoring method provided in the second embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The foregoing and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present application.

[0026] Embodiment 1 Please refer to Figures 2 to 4, this application provides a monitoring structure for the electrical thickness of a gate oxide layer, including a first MOS structure. The first MOS structure is provided with: a substrate, on which a source-drain region (including a first source and a first drain disposed in the active region) is provided; a channel region is disposed between the first source and the first drain; a first gate oxide layer and a first gate are sequentially disposed above the channel region, and contact holes CT are disposed above the first gate, the first source, and the first drain for connecting the first gate, the first source, and the first drain to a metal layer located on the contact holes CT respectively. Specifically, the first source and the first drain are respectively connected to a first metal wire through a first contact hole, and the first gate is connected to a second metal wire through a second contact hole. By applying a voltage signal to the second metal wire connected to the first gate, the conduction state of the channel region can be controlled, so as to measure the capacitance of the first MOS device in the strong inversion state, and then calculate the electrical thickness of the first gate oxide layer.

[0027] In the first MOS structure, a first electrode plate is formed above the source-drain region. The first electrode plate may include the first source, the first contact hole above the first source, and the first metal wire above the first contact hole, or may include the first drain, the first contact hole, and the first metal wire. A second electrode plate is formed above the channel region. The second electrode plate includes the first gate oxide layer, and the first gate, the second contact hole, and the second metal wire sequentially disposed above the first gate oxide layer. The first gate and the source-drain region have a first overlapping region. Specifically, the first gate respectively has an overlapping region A1 and an overlapping region A2 with the first source and the first drain.

[0028] In this embodiment, the monitoring structure for the electrical thickness of the gate oxide layer further includes a second MOS structure arranged at an interval from the first MOS structure. The setting of the second MOS structure can refer to the above embodiment. For a brief description, for the parts not mentioned in the setting of the second MOS structure, the corresponding content in the first MOS structure can be referred to. Among them, one or more first MOS structures and second MOS structures can be provided. The difference between the second MOS structure and the first MOS structure is that: In the second MOS structure, a third electrode plate is formed above the source-drain region. The third electrode plate may include the second source, the third contact hole above the second source, and the third metal wire above the third contact hole, or may include the second drain, the third contact hole above the second drain, and the third metal wire above the third contact hole. A fourth electrode plate is formed above the channel region. The fourth electrode plate includes the second gate oxide layer, and the second gate, the fourth contact hole, and the fourth metal wire sequentially disposed above the second gate oxide layer. The second gate and the source-drain region have a second overlapping region. Specifically, the second gate respectively has an overlapping region B1 and an overlapping region B2 with the second source and the second drain.

[0029] In the semiconductor manufacturing process, when the first MOS structure and the second MOS structure are arranged at intervals on the same wafer, through careful design and strict process condition control, the two structures can achieve the same process height in each process step. Specifically, the manufacturing of the MOS structure involves multiple process steps, including lithography, etching, ion implantation, deposition, annealing, etc. To achieve a high degree of process consistency, precise control measures need to be taken in each process step. For example, in the lithography process, by strictly controlling the alignment accuracy and light dose of the wafer, the pattern sizes of the first MOS structure and the second MOS structure can be ensured to be the same; in the etching process, by optimizing the etching parameters (such as etching gas flow rate, power, and time), the etching depths and shapes of the two structures can be guaranteed to be the same; in the ion implantation process, by precisely controlling the implantation dose and energy, the doping concentrations of the two structures can be ensured to be the same. In addition, regular calibration of equipment, optimization of process parameters, and real-time monitoring of process conditions (such as deposition rate, temperature distribution, annealing time) are also the keys to achieving a high degree of consistency. In this embodiment, by arranging the first MOS structure and the second MOS structure at intervals, the process heights of each section of the first MOS structure and the second MOS structure can be made the same.

[0030] As Figures 1 - 4 shown, in this embodiment, along the channel direction, the distance between any point on the first electrode plate and the second electrode plate is the same as the distance between the corresponding point on the third electrode plate and the fourth electrode plate. Specifically, the distance between the first metal wire and the second metal wire is the same as the distance between the third metal wire and the fourth metal wire (D m2m ); the distance between the first contact hole and the second contact hole is the same as the distance between the third contact hole and the fourth contact hole (D c2c ); the distance between the first contact hole and the first gate is the same as the distance between the third contact hole and the second gate (D c2p ). With such a setting, due to the high consistency of each section of the process of the first MOS structure and the second MOS structure, the distance between any point on the first electrode plate and the second electrode plate along the channel direction is the same as the distance between the corresponding point on the third electrode plate and the fourth electrode plate, so that the parasitic capacitances in the first MOS structure and the second MOS structure include the capacitance C c2p between the contact hole and the gate, the capacitance C c2c between the contact holes, the capacitance C m2c between the metal wire and the contact hole, the capacitance C m2p between the metal wire and the gate, the capacitance C m2m between the metal wires, and the capacitance C of between the gate and the source / drain.remain consistent. In addition, since the areas of the first overlapping region and the second overlapping region are the same, the over-coverage capacitance C of the gates in the first MOS structure and the second MOS structure ov is the same. In this way, all the parasitic capacitances in the first MOS structure and the second MOS structure remain consistent.

[0031] In this embodiment, the area of the overlapping region A1 is the same as that of the overlapping region B1, and the area of the overlapping region A2 is the same as that of the overlapping region B2. With such a setting, and since the heights of each process segment of the first MOS structure and the second MOS structure are highly consistent, the over-coverage capacitance C of the gates in the first MOS structure and the second MOS structure ov remains consistent.

[0032] In this embodiment, compared with the gate region on the fourth electrode plate, the gate region on the second electrode plate has the same gate width but different gate lengths. In some embodiments, the width of the first gate is the same as that of the second gate, and the length of the first gate is greater than that of the second gate. By setting the gate region on the second electrode plate to have the same gate width but different gate lengths compared with the gate region on the fourth electrode plate, the difference between the first MOS structure and the second MOS structure lies only in the gate length. Thus, the parasitic capacitance can be cancelled out through the capacitance measurement results of the first MOS structure and the second MOS structure, and then the accurate electrical thickness of the gate oxide layer can be calculated. This monitoring structure does not require additional process steps and has good compatibility with the actual semiconductor manufacturing process. By monitoring the capacitance value, the final thickness of the gate oxide layer can be effectively monitored, improving the accuracy and efficiency of process monitoring.

[0033] It should be noted that along the channel direction, to ensure that the distance between any point on the first electrode plate and the second electrode plate is the same as the distance between the corresponding point on the third electrode plate and the fourth electrode plate, while the length of the first gate is greater than that of the second gate, the number of the second contact holes is greater than that of the fourth contact holes. In some embodiments, the number of the second contact holes is at least 2, and the number of the fourth contact holes is at least 1. With such a setting, when the length of the first gate is greater than that of the second gate, the distance between the first contact hole and the nearest second contact hole is the same as the distance between the third contact hole and the nearest fourth contact hole, ensuring that the distance between any point on the first electrode plate and the second electrode plate is the same as the distance between the corresponding point on the third electrode plate and the fourth electrode plate, so that the parasitic capacitances in the first MOS structure and the second MOS structure remain consistent.

[0034] Of course, in other embodiments, the number of the second contact holes and the fourth contact holes can be adaptively set according to the specific settings of the first MOS structure and the second MOS structure, which is not limited in this application.

[0035] Example 2 As Figure 5 shown, this embodiment provides a method for monitoring the electrical thickness of a gate oxide layer, which is applied to the gate oxide layer electrical thickness monitoring structure as described in Example 1. For the parts not mentioned in this embodiment, reference can be made to the relevant content in Example 1, and this embodiment will not be elaborated. This method for monitoring the electrical thickness of the gate oxide layer can be executed by a computer. Specifically, it is executed by one or more processors in the computer, and includes the following steps S101 - S103.

[0036] Step S101: Determine the area A1 of the first gate oxide layer under the gate region on the second electrode plate and the area A2 of the second gate oxide layer under the gate region on the fourth electrode plate.

[0037] In this embodiment, the area A1 of the first gate oxide layer under the gate region on the second electrode plate can be calculated by multiplying the length L1 of the first gate in the channel direction by the width W1 perpendicular to the channel direction: A1 = L1 * W1; the area A2 of the second gate oxide layer under the gate region on the fourth electrode plate can be calculated by multiplying the length L2 of the second gate in the channel direction by the width W2 perpendicular to the channel direction: A2 = L2 * W2.

[0038] Step S102: Determine the first total capacitance of the first MOS structure and the second total capacitance of the second MOS structure.

[0039] In this embodiment, both the first total capacitance of the first MOS structure and the second total capacitance of the second MOS structure are the capacitances of the corresponding MOS structures in the strong inversion state.

[0040] In this embodiment, determining the first total capacitance C1 of the first MOS structure includes: connecting the metal wire connected to the first gate to a voltage source and applying a scanning voltage, grounding or floating the metal wires connected to the first source and the first drain, and collecting current signals. Integrating the collected current with respect to time to calculate the charge dt. Then, according to the relationship between the scanning voltage U1 and the charge Q1, calculate the first total capacitance .

[0041] Determining the second total capacitance C2 of the second MOS structure includes: connecting the metal wire connected to the second gate to a voltage source and applying a scanning voltage, grounding or floating the metal wires connected to the second source and the second drain, and collecting current signals. Integrating the collected current with respect to time to calculate the charge dt. Then, according to the relationship between the scanning voltage U2 and the charge Q2, calculate the first total capacitance .

[0042] It can be understood that the first total capacitance of the first MOS structure and the second total capacitance of the second MOS structure can also be obtained by analyzing the C-V characteristic curve through the C-V measurement method or measured by other methods, and can be adaptively selected according to the measurement frequency range, accuracy requirements, and equipment availability. This application does not limit this here.

[0043] In this embodiment, the first total capacitance C1 of the first MOS structure includes the first gate oxide capacitance C ox1 and the first parasitic capacitance C x1 , and the first parasitic capacitance C x1 includes, in the first MOS structure, the capacitance C c2p between the contact hole and the gate, the capacitance C c2c between the contact holes, the capacitance C m2c between the metal wire and the contact hole, the capacitance C m2p between the metal wire and the gate, the capacitance C m2m between the metal wires, the capacitance C of between the gate and the source / drain, and the over-coverage capacitance C ov of the gate. The second total capacitance C2 of the second MOS structure includes the second gate oxide capacitance C ox2 and the second parasitic capacitance C x2 , and the second parasitic capacitance C x2 includes, in the second MOS structure, the capacitance C c2p between the contact hole and the gate, the capacitance C c2c between the contact holes, the capacitance C m2c between the metal wire and the contact hole, the capacitance C m2p between the metal wire and the gate, the capacitance C m2m between the metal wires, the capacitance C of between the gate and the source / drain, and the over-coverage capacitance C ov .

[0044] Due to the high consistency of each process segment of the first MOS structure and the second MOS structure, along the channel direction, the distance between any point on the first electrode plate and the second electrode plate is the same as the distance between the corresponding point on the third electrode plate and the fourth electrode plate, and the areas of the first overlapping region and the second overlapping region are the same, so that the above-mentioned first parasitic capacitance C x1 is equal to the second parasitic capacitance C x2 .

[0045] Step S103, based on the first total capacitance C1, the first gate oxide area A1, the second total capacitance C2, and the second gate oxide area A2, calculate the electrical thickness of the gate oxide of the first MOS structure and the second MOS structure.

[0046] In this embodiment, by using the electrical thickness monitoring structure of the gate oxide layer, based on the first total capacitance C1, the area A1 of the first gate oxide layer, the second total capacitance C2, the area A2 of the second gate oxide layer, and the gate oxide layer thickness calculation formula, the electrical thicknesses of the gate oxide layers of the first MOS structure and the second MOS structure in the gate oxide layer electrical thickness monitoring structure can be calculated.

[0047] In some embodiments, the known gate oxide layer thickness calculation formula is as follows: , where C (1) Where is the gate oxide layer thickness, is the vacuum permittivity, is the relative permittivity of the gate oxide layer, A is the gate area, C is the total capacitance, is the gate oxide layer capacitance, is the parasitic capacitance.

[0048] In this embodiment, given the gate oxide layer capacitance calculation formula (1), the first gate oxide layer capacitance can be set as C ox1 , and the first parasitic capacitance as C x1 . Substituting the first total capacitance C1 and the area A1 of the first gate oxide layer into the above formula, we can get: (2) Let the second gate oxide layer capacitance be C ox2 , and the second parasitic capacitance be C x2，将第二总电容C2 . Substituting the area A2 of the second gate oxide layer into the above formula, we can get: (3) Since the first gate oxide layer thickness is equal to the second gate oxide layer thickness , and the first parasitic capacitance C x1 is equal to the second parasitic capacitance C x2 , then And C x1 = C x2 （4） According to formulas (2)-(3), the first parasitic capacitance C x1 of the first MOS structure can be calculated. Substituting C x1 into formula (2), the electrical thickness of the gate oxide layer of the first MOS structure is obtained as .

[0049] In some other embodiments, calculating the electrical thicknesses of the gate oxide layers of the first MOS structure and the second MOS structure includes the following steps: In step S1031, a third equivalent capacitance C3 can be determined according to the first total capacitance C1 and the second total capacitance C2, and the third equivalent capacitance C3 does not include parasitic capacitance.

[0050] In step S1032, a third equivalent gate oxide layer area A3 is determined according to the first gate oxide layer area A1 and the second gate oxide layer area A2, and the thickness of the third equivalent gate oxide layer is the same as that of the first gate oxide layer and the second gate oxide layer.

[0051] In step S1033, based on the third equivalent capacitance C3, the third equivalent gate oxide layer area A3, and the capacitance formula, the electrical thickness of the gate oxide layer of the first MOS structure and the second MOS structure is calculated.

[0052] In this embodiment, C3 = C1 - C2 and A3 = A1 - A2 (5) Combining Equation (1), (4) and Equation (5), it can be obtained that C3 = C ox1 -C ox2 (6) Since the first gate oxide layer area A1 and the first gate oxide layer area A2 are respectively: A1 = L1 * W A2 = L2 * W (7) Wherein, W is the width of the first gate and the width of the second gate, then from Equation (5) and (7), it can be obtained: ( - ) * W (8) Substituting Equation (6) and (8) into Equation (1), the electrical thickness of the gate oxide layer is obtained In this embodiment, the gate oxide layer capacitance is proportional to the area A of the gate oxide layer. The third equivalent capacitance C3 is the difference between the first total capacitance C1 and the second total capacitance C2, and the third equivalent gate oxide layer area A3 is the difference between the first gate oxide layer area A1 and the second gate oxide layer area A2. Therefore, the third equivalent capacitance C3 is proportional to the third equivalent gate oxide layer area A3. The thickness of the third equivalent gate oxide layer is the same as that of the first gate oxide layer and the second gate oxide layer, and the third equivalent capacitance C3 does not include parasitic capacitance and is the capacitance of the third equivalent gate oxide layer. Therefore, by applying the third equivalent capacitance C3 and the third equivalent gate oxide layer area A3 to the capacitance formula (4), the accurate thickness of the gate oxide layer can be calculated .

[0053] Through the above steps, the capacitance measurement results of the first MOS structure and the second MOS structure cancel out the parasitic capacitance, thereby calculating the accurate electrical thickness of the gate oxide layer. This monitoring structure does not require additional process steps and has good compatibility with the actual semiconductor manufacturing process. By monitoring the capacitance value, the final thickness of the gate oxide layer can be effectively monitored, improving the accuracy and efficiency of process monitoring. It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown in the direction of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps in other steps.

[0054] Based on the same inventive concept, an embodiment of the present application also provides a gate oxide layer electrical thickness monitoring device for implementing the gate oxide layer electrical thickness method described above. The solution provided by this device to solve the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the gate oxide layer electrical thickness monitoring device provided below can refer to the limitations on the gate oxide layer electrical thickness monitoring method in the above text, and will not be repeated here.

[0055] In one embodiment, a gate oxide layer electrical thickness monitoring device is provided, including: a gate oxide layer area determination unit, a total capacitance determination unit, and a gate oxide layer electrical thickness calculation unit.

[0056] The gate oxide layer area determination unit is configured to determine the area of the first gate oxide layer under the gate region on the second electrode plate and the area of the second gate oxide layer under the gate region on the fourth electrode plate; The total capacitance determination unit is configured to determine the first total capacitance of the first MOS structure and the second total capacitance of the second MOS structure; The gate oxide layer electrical thickness calculation unit is configured to calculate the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance, the area of the first gate oxide layer, the second total capacitance, and the area of the second gate oxide layer.

[0057] In some embodiments, the total capacitance determination unit includes: a first current acquisition unit, a first charge amount determination unit, and a first calculation unit.

[0058] A first current acquisition unit for acquiring a current signal of a first MOS structure, wherein a scanning voltage is applied above the gate in the first MOS structure, and the source-drain region is grounded; A first charge quantity determination unit for integrating the current signal over time to determine the charge quantity; A first calculation unit for calculating a first total capacitance according to the scanning voltage and the charge quantity.

[0059] In some embodiments, the total capacitance determination unit further includes: a second current acquisition unit, a second charge quantity determination unit, and a second calculation unit.

[0060] A second current acquisition unit for acquiring a current signal of a second MOS structure, wherein a scanning voltage is applied above the gate in the second MOS structure, and the source-drain region is grounded; A second charge quantity determination unit for integrating the current signal over time to determine the charge quantity; A second calculation unit for calculating a second total capacitance according to the scanning voltage and the charge quantity.

[0061] In some embodiments, the electrical thickness calculation unit of the gate oxide layer includes: an equivalent capacitance determination unit, an equivalent gate oxide layer area determination unit, and a first thickness calculation unit.

[0062] The equivalent capacitance determination unit is configured to determine a third equivalent capacitance according to the first total capacitance and the second total capacitance, and the third equivalent capacitance does not include parasitic capacitance; The equivalent gate oxide layer area determination unit is configured to determine a third equivalent gate oxide layer area according to the first gate oxide layer area and the second gate oxide layer area; The first thickness calculation unit is configured to calculate the electrical thickness of the gate oxide layer of the first MOS structure and the second MOS structure based on the third equivalent capacitance, the third equivalent gate oxide layer area, and the capacitance formula.

[0063] In some embodiments, the electrical thickness calculation unit of the gate oxide layer includes: a parasitic capacitance calculation unit and a second thickness calculation unit.

[0064] The parasitic capacitance calculation unit is configured to determine a first parasitic capacitance and a second parasitic capacitance based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area; The second thickness calculation unit is configured to determine the electrical thickness of the gate oxide layer of the first MOS structure based on the first total capacitance, the first gate oxide layer area, and the first parasitic capacitance, or determine the electrical thickness of the gate oxide layer of the second MOS structure based on the second total capacitance, the second gate oxide layer area, and the second parasitic capacitance.

[0065] In one embodiment, a computer device is provided, which may be a server or a terminal device. The computer device includes a processor, a memory, and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it implements the above-mentioned method for monitoring the electrical thickness of the gate oxide layer.

[0066] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0067] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A monitoring structure for the electrical thickness of a gate oxide layer, characterized in that, Comprising: A first MOS structure and a second MOS structure arranged at intervals, wherein in the first MOS structure, a first electrode plate is formed above the source-drain region, and a second electrode plate is formed above the channel region, and the gate on the second electrode plate has a first overlapping region with the source-drain region; In the second MOS structure, a third electrode plate is formed above the source-drain region, and a fourth electrode plate is formed above the channel region, and the gate on the fourth electrode plate has a second overlapping region with the source-drain region; In the channel direction, the distance between any point on the first electrode plate and the second electrode plate is the same as the distance between the corresponding point on the third electrode plate and the fourth electrode plate, the areas of the first overlapping region and the second overlapping region are the same, and compared with the gate region on the fourth electrode plate, the gate width of the gate region on the second electrode plate is the same and the gate length is different.

2. The gate oxide layer electrical thickness monitoring structure according to claim 1, characterized in that: The first MOS structure includes: A first source electrode and a first drain electrode, respectively connected to a first metal wire through a first contact hole; and a first gate, connected to a second metal wire through a second contact hole; The second MOS structure includes: A second source electrode and a second drain electrode, respectively connected to a third metal wire through a third contact hole; and a second gate, connected to a fourth metal wire through a fourth contact hole; The distance between the first metal wire and the second metal wire is the same as the distance between the third metal wire and the fourth metal wire; the distance between the first contact hole and the second contact hole is the same as the distance between the third contact hole and the fourth contact hole; the distance between the first contact hole and the first gate is the same as the distance between the third contact hole and the second gate; The width of the first gate is equal to the width of the second gate, the length of the first gate is greater than the length of the second gate, and the number of the second contact holes is greater than the number of the fourth contact holes.

3. The gate oxide layer electrical thickness monitoring structure according to claim 2, characterized in that: The first gate has overlapping regions A1 and A2 with the first source electrode and the first drain electrode respectively, and the second gate has overlapping regions B1 and B2 with the second source electrode and the second drain electrode respectively; the areas of the overlapping region A1 and the overlapping region B1 are the same, and the areas of the overlapping region A2 and the overlapping region B2 are the same; The width of the first gate is the same as the width of the second gate, and the length of the first gate is greater than the length of the second gate.

4. A method for monitoring the electrical thickness of a gate oxide layer, which is applied to the gate oxide layer electrical thickness monitoring structure according to any one of claims 1-3, characterized in that, Comprising: Determining the area of the first gate oxide layer under the gate region on the second electrode plate and the area of the second gate oxide layer under the gate region on the fourth electrode plate; Determining the first total capacitance of the first MOS structure and the second total capacitance of the second MOS structure; Based on the first total capacitance, the area of the first gate oxide layer, the second total capacitance, and the area of the second gate oxide layer, calculating the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure.

5. The method for monitoring the electrical thickness of a gate oxide layer according to claim 4, characterized in that, Determining the first total capacitance of the first MOS structure includes: Obtain the current signal of the first MOS structure, wherein a scanning voltage is applied above the gate in the first MOS structure, and the source-drain region is grounded; Integrate the current signal over time to determine the charge quantity; Calculate the first total capacitance based on the scanning voltage and the charge quantity; 6. The method for monitoring the electrical thickness of the gate oxide layer according to claim 4, wherein Determining the second total capacitance of the second MOS structure includes: Obtain the current signal of the second MOS structure, wherein a scanning voltage is applied above the gate in the second MOS structure, and the source-drain region is grounded; Integrate the current signal over time to determine the charge quantity; Calculate the second total capacitance based on the scanning voltage and the charge quantity; 7. The method for monitoring the electrical thickness of a gate oxide layer according to claim 4, wherein Calculating the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area includes: Determine a third equivalent capacitance according to the first total capacitance and the second total capacitance, and the third equivalent capacitance does not include parasitic capacitance; Determine a third equivalent gate oxide layer area according to the first gate oxide layer area and the second gate oxide layer area, and the thickness of the third equivalent gate oxide layer is the same as that of the first gate oxide layer and the second gate oxide layer; Calculate the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the third equivalent capacitance, the third equivalent gate oxide layer area, and the capacitance formula; 8. The method for monitoring the electrical thickness of the gate oxide layer according to claim 4, wherein Calculating the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area includes: Determine the first parasitic capacitance and the second parasitic capacitance based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area; Determine the electrical thickness of the gate oxide layer of the first MOS structure based on the first total capacitance, the first gate oxide layer area, and the first parasitic capacitance, or determine the electrical thickness of the gate oxide layer of the second MOS structure based on the second total capacitance, the second gate oxide layer area, and the second parasitic capacitance; 9. A gate oxide layer electrical thickness monitoring device is applied to the gate oxide layer electrical thickness monitoring structure described in any one of claims 1-3, and is characterized in that, Includes: A gate oxide layer area determination unit for determining the first gate oxide layer area under the gate region on the second electrode plate and the second gate oxide layer area under the gate region on the fourth electrode plate; A total capacitance determination unit for determining the first total capacitance of the first MOS structure and the second total capacitance of the second MOS structure; A gate oxide layer electrical thickness calculation unit for calculating the electrical thickness of the gate oxide layers of the first MOS structure and the second MOS structure based on the first total capacitance, the first gate oxide layer area, the second total capacitance, and the second gate oxide layer area; 10. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 4 to 8.

Images