A combinational logic circuit that outputs high-voltage signals

Abstract

The present invention provides a combinational logic circuit that outputs high-voltage signals, including a power supply circuit, wherein a high-voltage source thereof is connected to a high-voltage PH and a low-voltage source is grounded, and is used to output a first low-voltage PL1 and a second low-voltage PL2; a low-voltage output signal generating circuit, wherein a high-voltage source thereof is connected to the first low-voltage PL1 and the low-voltage source is grounded, and is used to output multiple low-voltage output signals with the same frequency but different phases according to a first low-voltage input signal SL1 and a second low-voltage input signal SL2; multiple high-voltage signal output circuits, each of which has a first high-voltage source, a second high-voltage source, a first low-voltage source, and a second low-voltage source, the first high-voltage source being connected to the high-voltage PH, the second high-voltage source being connected to the first low-voltage PL1, the first low-voltage source being connected to the second low-voltage PL2, and the second low-voltage source being grounded; each high-voltage signal output circuit being connected to a corresponding low-voltage output signal, and outputting a high-voltage signal according to the corresponding low-voltage output signal, wherein the high-voltage signals output by the multiple high-voltage signal output circuits are signals with the same frequency but different phases.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a combinational logic circuit that outputs a high-voltage signal. Background Art

[0002] Existing power supply chips are commonly used in high-voltage, high-power scenarios such as multi-phase interleaved parallel topologies, high-frequency inverters, and motor drives. These applications often require the generation of multiple high-voltage signals within the chip, synchronized in frequency but with different phases. Existing combinational logic circuits that output multiple high-voltage signals are typically bulky and suffer from poor frequency synchronization and low phase control accuracy. Furthermore, these circuits consume a lot of energy, making it difficult to meet the power management requirements of high integration, low power consumption, and high reliability. Summary of the Invention

[0003] The purpose of the present invention is to solve the problems of large volume, low frequency synchronization and phase control precision, and high energy consumption of existing combinational logic circuits.

[0004] According to a first aspect of the present invention, there is provided a combinational logic circuit for outputting a high-voltage signal, comprising:

[0005] A power supply circuit, wherein the high voltage source is connected to the high voltage PH and the low voltage source is grounded, and is used to output a first low voltage PL1 and a second low voltage PL2;

[0006] a low-voltage output signal generating circuit, wherein a high-voltage source thereof is connected to the first low-voltage PL1 and the low-voltage source is grounded, and the low-voltage output signal generating circuit is connected to a first low-voltage input signal SL1 and a second low-voltage input signal SL2, and is configured to output a plurality of low-voltage output signals having the same frequency but different phases according to the first low-voltage input signal SL1 and the second low-voltage input signal SL2;

[0007] Multiple high-voltage signal output circuits, each of which has a first high-voltage source, a second high-voltage source, a first low-voltage source, and a second low-voltage source, the first high-voltage source is connected to the high voltage PH, the second high-voltage source is connected to the first low voltage PL1, the first low-voltage source is connected to the second low voltage PL2, and the second low-voltage source is grounded; each high-voltage signal output circuit is connected to a corresponding low-voltage output signal, and outputs a high-voltage signal according to the corresponding low-voltage output signal, and the high-voltage signals output by the multiple high-voltage signal output circuits are signals with the same frequency but different phases.

[0008] In an optional embodiment, the voltages of the first low-voltage input signal SL1 and the second low-voltage input signal SL2 are both not higher than the voltage of the first low voltage PL1 , and are both not lower than the ground voltage.

[0009] In an optional embodiment, the multiple high-voltage signal output circuits have the same circuit structure, and the high-voltage signal output circuit includes a first high-voltage signal output switch tube M1, a second high-voltage signal output switch tube M2 and a high-voltage signal control module;

[0010] The high-voltage signal control module includes the first high-voltage source, the second high-voltage source, the first low-voltage source, the second low-voltage source, an input end, a first output end, and a second output end. The input end of the high-voltage signal control module is connected to the low-voltage output signal, the first output end of the high-voltage signal control module is connected to the control end of the first high-voltage signal output switch tube M1, and the second output end of the high-voltage signal control module is connected to the control end of the second high-voltage signal output switch tube M2;

[0011] The current input terminal of the first high-voltage signal output switch tube M1 is connected to the high voltage PH, and the current output terminal is connected to the current input terminal of the second high-voltage signal output switch tube M2; the current output terminal of the second high-voltage signal output switch tube M2 is grounded;

[0012] The high voltage signal control module is used to control the on and off of the first high voltage signal output switch tube M1 and the second high voltage signal output switch tube M2 according to the high voltage PH, the second low voltage PL2, the first low voltage PL1 and the low voltage output signal.

[0013] In an optional embodiment, the high-voltage signal control module includes a first logic unit, a second logic unit, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7 and an eighth switch tube M8;

[0014] In the high-voltage signal control module, the high voltage PH is grounded sequentially through the third switch tube M3, the fourth switch tube M4, and the fifth switch tube M5, and the control end of the fifth switch tube M5 is connected to the first logic unit; the high voltage PH is also grounded sequentially through the sixth switch tube M6, the seventh switch tube M7, and the eighth switch tube M8, and the control end of the eighth switch tube M8 is connected to the second logic unit; the control ends of the fourth switch tube M4 and the seventh switch tube M7 are both connected to the second low voltage PL2;

[0015] The input end of the first logic unit serves as the input end of the high-voltage signal control module, and the output end of the first logic unit is connected to the input end of the second logic unit.

[0016] In an optional embodiment, the high-voltage signal control module further includes an RS trigger B1, a first inverter F1, a second inverter F2 and a third inverter F3;

[0017] The input end of the first inverter F1 is connected to the first node E1 between the third switch tube M3 and the fourth switch tube M4, and the output end is connected to the set end of the RS trigger B1;

[0018] The input end of the second inverter F2 is connected to the second node E2 between the sixth switch tube M6 and the seventh switch tube M7, and the output end is connected to the reset end of the RS trigger B1;

[0019] The input end of the third inverter F3 is connected to the inverting output end of the RS trigger B1, and the output end serves as the first output end of the high-voltage signal control module;

[0020] The high reference terminals of the RS trigger B1 , the first inverter F1 , the second inverter F2 and the third inverter F3 are all connected to the high voltage PH, and the low reference terminals are all connected to the second low voltage PL2 .

[0021] In an optional embodiment, the high-voltage signal control module further includes a ninth switch tube M9, a tenth switch tube M10, a fourth inverter F4 and a fifth inverter F5;

[0022] The input end of the fourth inverter F4 is connected to the output end of the second inverter F2, and the output end of the fourth inverter F4 is connected to the control end of the ninth switch tube M9; the current input end of the ninth switch tube M9 is connected to the first node E1, and the current output end is connected to the control end of the fourth switch tube M4. The control end of the ninth switch tube M9 is also connected to the control end of the third switch tube M3;

[0023] The input end of the fifth inverter F5 is connected to the output end of the first inverter F1, and the output end of the fifth inverter F5 is connected to the control end of the tenth switch tube M10; the current input end of the tenth switch tube M10 is connected to the second node E2, and the current output end is connected to the control end of the seventh switch tube M7. The control end of the tenth switch tube M10 is also connected to the control end of the sixth switch tube M6;

[0024] The high reference terminals of the fourth inverter F4 and the fifth inverter F5 are both connected to the high voltage PH, and the low reference terminals are both connected to the second low voltage PL2.

[0025] In an optional embodiment, the first logic unit includes a sixth inverter F6 and a seventh inverter F7, and the second logic unit includes an eighth inverter F8;

[0026] The input end of the sixth inverter F6 serves as the input end of the high-voltage signal control module, and the output end is connected to the input end of the eighth inverter F8 through the seventh inverter F7; the output end of the eighth inverter F8 serves as the second output end of the high-voltage signal control module; the output end of the seventh inverter F7 is connected to the control end of the fifth switch tube M5, and the output end of the eighth inverter F8 is also connected to the control end of the eighth switch tube M8;

[0027] The high reference terminals of the sixth inverter F6 , the seventh inverter F7 and the eighth inverter F8 are all connected to the first low voltage PL1 , and the low reference terminals are all grounded.

[0028] In an optional embodiment, the low-voltage output signal generating circuit includes a first resistor R1, a second resistor R2, an eleventh switch tube M11, a twelfth switch tube M12, a comparator A1, a first controllable current source G1, a second controllable current source G2 and a third controllable current source G3;

[0029] In the low-voltage output signal generating circuit, the first low voltage PL1 is grounded in sequence through the first resistor R1, the eleventh switch tube M11, the twelfth switch tube M12, and the second resistor R2; the first low voltage PL1 is also grounded in sequence through the second controllable current source G2 and the third controllable current source G3;

[0030] The positive control terminals of the first controllable current source G1 and the second controllable current source G2 are both connected to the first low voltage PL1, and the negative control terminals are both connected to the current input terminal of the eleventh switch tube M11; the current input terminal of the first controllable current source G1 is connected to the first low voltage PL1, and the current output terminal is connected to the positive control terminal of the third controllable current source G3; the positive control terminal of the third controllable current source G3 is also connected to the current output terminal of the twelfth switch tube M12, and the negative control terminal of the third controllable current source G3 is grounded;

[0031] A third node E3 between the eleventh switch transistor M11 and the twelfth switch transistor M12 is connected to the first low-voltage input signal SL1;

[0032] The comparator A1 has a positive input terminal connected to the first comparison voltage V1 , a negative input terminal connected to the first low-voltage input signal SL1 , and an output terminal connected to the control terminals of the eleventh switch tube M11 and the twelfth switch tube M12 .

[0033] In an optional embodiment, the low-voltage output signal generating circuit further includes a third resistor R3, a fourth controllable current source G4, a fifth controllable current source G5, a sixth controllable current source G6 and a seventh controllable current source G7;

[0034] The first end of the third resistor R3 is connected to the first low voltage PL1, and the current input end and the positive control end of the fifth controllable current source G5, the sixth controllable current source G6 and the seventh controllable current source G7 are all connected to the first low voltage PL1; the negative control ends of the fifth controllable current source G5, the sixth controllable current source G6 and the seventh controllable current source G7 are all connected to the second end of the third resistor R3, and are commonly connected to the current input end of the fourth controllable current source G4; the current output end and the negative control end of the fourth controllable current source G4 are both grounded, and the positive control end of the fourth controllable current source G4 is connected to the positive control end of the third controllable current source G3.

[0035] In an optional embodiment, the low-voltage output signal generating circuit further includes a thirteenth switch tube M13, a fourteenth switch tube M14, a first capacitor C1, a ninth inverter F9 and a tenth inverter F10;

[0036] The current input terminal of the thirteenth switch tube M13 is connected to the current output terminal of the fifth controllable current source G5, the current output terminal of the thirteenth switch tube M13 is grounded through the fourteenth switch tube M14, and the control terminal is connected to the second low-voltage input signal SL2; the control terminal of the fourteenth switch tube M14 is connected to the control terminal of the thirteenth switch tube M13;

[0037] A first end of the first capacitor C1 is connected to the current input end of the fourteenth switch tube M14, and a second end thereof is grounded;

[0038] The input end of the ninth inverter F9 is connected to the current input end of the fourteenth switch tube M14, and the output end thereof outputs the first low-voltage output signal SLO1;

[0039] An input terminal of the tenth inverter F10 is connected to an output terminal of the ninth inverter F9 , and an output terminal of the tenth inverter F10 outputs a second low-voltage output signal SLO2 .

[0040] In an optional embodiment, the low-voltage output signal generating circuit further includes an eleventh inverter F11, a twelfth inverter F12, a fifteenth switch tube M15, a sixteenth switch tube M16, a second capacitor C2, a first OR gate O1, a first AND gate N1 and a first NAND gate NF1;

[0041] The current input terminal of the fifteenth switch tube M15 is connected to the current output terminal of the sixth controllable current source G6, the current output terminal of the fifteenth switch tube M15 is grounded through the sixteenth switch tube M16, and the control terminal of the fifteenth switch tube M15 is connected to the control terminal of the sixteenth switch tube M16;

[0042] The input end of the eleventh inverter F11 is connected to the second low-voltage input signal SL2, and the output end is connected to the control end of the fifteenth switch tube M15;

[0043] A first end of the second capacitor C2 is connected to the current input end of the sixteenth switch tube M16, and a second end is grounded;

[0044] The input end of the twelfth inverter F12 is connected to the current input end of the sixteenth switch tube M16, and the output end is connected to the first input end of the first OR gate O1; the second input end of the first OR gate O1 is connected to the first input end of the first NAND gate NF1, and both are connected to the current output end of the second controllable current source G2; the second input end of the first NAND gate NF1 is connected to the first input end of the first OR gate O1;

[0045] A first input of the first AND gate N1 is connected to the output of the first OR gate O1 , a second input of the first AND gate N1 is connected to the output of the first NAND gate NF1 , and the output of the first AND gate N1 outputs a third low-voltage output signal SLO3 .

[0046] In an optional embodiment, the low-voltage output signal generating circuit further includes a thirteenth inverter F13, a fourteenth inverter F14, a seventeenth switch tube M17, an eighteenth switch tube M18, a third capacitor C3, a second OR gate O2, a second AND gate N2, and a second NAND gate NF2;

[0047] A current input terminal of the seventeenth switch tube M17 is connected to a current output terminal of the seventh controllable current source G7, a current output terminal of the seventeenth switch tube M17 is grounded via the eighteenth switch tube M18, a control terminal of the seventeenth switch tube M17 is connected to a control terminal of the eighteenth switch tube M18, and both are connected to an output terminal of the eleventh inverter F11;

[0048] A first end of the third capacitor C3 is connected to the current input end of the eighteenth switch tube M18, and a second end thereof is grounded;

[0049] The input end of the thirteenth inverter F13 is connected to the current input end of the eighteenth switch tube M18, and the output end is connected to the first input end of the second OR gate O2;

[0050] The input end of the fourteenth inverter F14 is connected to the current output end of the second controllable current source G2, and the output end is connected to the first input end of the second NAND gate NF2;

[0051] The first input terminal of the second OR gate O2 is further connected to the second input terminal of the second NAND gate NF2; the first input terminal of the second NAND gate NF2 is further connected to the second input terminal of the second OR gate O2;

[0052] A first input of the second AND gate N2 is connected to the output of the second OR gate O2 , a second input of the second AND gate N2 is connected to the output of the second NAND gate NF2 , and an output of the second AND gate N2 outputs a fourth low-voltage output signal SLO4 .

[0053] In an optional embodiment, the current coefficient of the third controllable current source G3 is less than 1, and the current coefficients of the first controllable current source G1, the second controllable current source G2, the fourth controllable current source G4, the fifth controllable current source G5, the sixth controllable current source G6 and the seventh controllable current source G7 are equal to 1.

[0054] In an optional embodiment, the first low-voltage input signal SL1 includes a first sub-signal SL11 and a second sub-signal SL12 , the voltage of the first sub-signal SL11 is lower than the first comparison voltage V1 , and the voltage of the second sub-signal SL12 is higher than the first comparison voltage V1 .

[0055] In an optional embodiment, in the power supply circuit, the high voltage PH is grounded sequentially through the nineteenth switch tube M19 and the fourth resistor R4; the high voltage PH is also grounded sequentially through the fifth resistor R5 and the first voltage stabilizing diode D1; the high voltage PH is also grounded sequentially through the second voltage stabilizing diode D2 and the sixth resistor R6; the high voltage PH is also grounded sequentially through the seventh resistor R7 and the twentieth switch tube M20;

[0056] The control end of the nineteenth switch tube M19 is connected between the fifth resistor R5 and the first voltage zener diode D1; the control end of the twentieth switch tube M20 is connected between the second voltage zener diode D2 and the sixth resistor R6; the current output end voltage of the nineteenth switch tube M19 is the first low voltage PL1, and the current input end voltage of the twentieth switch tube M20 is the second low voltage PL2.

[0057] According to the solution of the present invention, through the precise coordination of the low-voltage input signal and the circuit structure, multiple groups of high-voltage signals with the same frequency but different phases can be generated. Specifically, the low-voltage output signal generation circuit generates multiple low-voltage output signals with the same frequency but different phases based on the low-voltage input signal, and then multiple high-voltage signal output circuits generate high-voltage signals based on the corresponding low-voltage output signals, thereby achieving phase control and frequency synchronization of the high-voltage signal. The technical solution of the present invention effectively reduces the overall power consumption of the circuit, while achieving frequency synchronization and precise phase control of the high-voltage signal, and helps to reduce the circuit area, thereby improving the integration and reliability of the system.

[0058] Furthermore, by providing Zener diodes with different parameters in the power supply circuit, the output voltages of the first low voltage PL1 and the second low voltage PL2 can be adjusted. At the same time, by clamping the gate-source voltage difference of the switching tube using the Zener diodes in the power supply circuit, all the switching tubes in the power supply circuit can use switching tubes with a low gate-source voltage difference.

[0059] Furthermore, by performing logical processing on the first low-voltage input signal SL1 and the second low-voltage input signal SL2 through the low-voltage output signal generating circuit, multiple low-voltage output signals with the same frequency but different phases can be generated simultaneously, and the phase difference between each low-voltage output signal can be dynamically adjusted by adjusting the magnitude of the external first current I1, thereby ensuring frequency synchronization between each low-voltage output signal while achieving high-precision phase control to meet the precise requirements of signal timing in different application scenarios.

[0060] Furthermore, the first low voltage PL1 is isolated from the high voltage PH by the nineteenth switch tube M19, thereby realizing the design of all low-voltage components of the low-voltage output signal generating circuit, effectively reducing the circuit volume and lowering power consumption.

[0061] Furthermore, through the design of multi-stage switching tubes and logic control circuits in the high-voltage signal output circuit, the high-voltage signal output circuit can receive a low-voltage output signal with a relatively low voltage and output a high-voltage signal with a higher voltage, thereby driving an external high-power switching tube, thereby improving the reliability of the high-voltage signal and the power conversion efficiency.

[0062] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 A structural block diagram of a combinational logic circuit for outputting a high-voltage signal according to an embodiment of the present invention is shown;

[0064] Figure 2shows a topological structure diagram of a power supply circuit 100 according to an embodiment of the present invention;

[0065] Figure 3 shows a topological structure diagram of a low-voltage output signal generating circuit 200 according to an embodiment of the present invention;

[0066] Figure 4 shows a waveform diagram of a second low voltage input signal SL2 according to an embodiment of the present invention;

[0067] Figure 5 1 shows a waveform comparison diagram of the second low voltage input signal SL2 and the first low voltage output signal SLO1 according to one embodiment of the present invention;

[0068] Figure 6 1 shows a waveform comparison diagram of a second low voltage input signal SL2 and a second low voltage output signal SLO2 according to an embodiment of the present invention;

[0069] Figure 7 1 shows a waveform comparison diagram of the second low voltage input signal SL2, the sixth node E6 and the third low voltage output signal SLO3 according to one embodiment of the present invention;

[0070] Figure 8 shows a waveform comparison diagram of the second low voltage input signal SL2 and the fourth low voltage output signal SLO4 according to one embodiment of the present invention;

[0071] Figure 9 shows a topological structure diagram of a high-voltage signal output circuit according to an embodiment of the present invention;

[0072] Figure 10 shows an input and output waveform diagram of a high voltage signal output circuit according to an embodiment of the present invention;

[0073] Figure 11 A comparison diagram of input signal and output signal waveforms of a combinational logic circuit according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0074] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. It will be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0075] The terms "comprise," "comprising," and "having," and any variations thereof, as used herein, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0076] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute a separate or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0077] Figure 1 FIG1 shows a structural block diagram of a combinational logic circuit for outputting a high voltage signal according to an embodiment of the present invention. Figure 1 As shown, the combinational logic circuit that outputs high-voltage signals includes a power supply circuit 100, a low-voltage output signal generating circuit 200, and multiple high-voltage signal output circuits. The high-voltage source of the power supply circuit 100 is connected to a high-voltage voltage PH, and the low-voltage source is grounded, for outputting a first low-voltage PL1 and a second low-voltage PL2. The high-voltage source of the low-voltage output signal generating circuit 200 is connected to the first low-voltage PL1 and the low-voltage source is grounded. The low-voltage output signal generating circuit 200 is connected to a first low-voltage input signal SL1 and a second low-voltage input signal SL2, and is configured to output multiple low-voltage output signals with the same frequency but different phases based on the first low-voltage input signal SL1 and the second low-voltage input signal SL2. Each of the multiple high-voltage signal output circuits includes a first high-voltage source, a second high-voltage source, a first low-voltage source, and a second low-voltage source. The first high-voltage source is connected to the high-voltage PH, the second high-voltage source is connected to the first low-voltage PL1, the first low-voltage source is connected to the second low-voltage PL2, and the second low-voltage source is grounded. Each high-voltage signal output circuit receives a corresponding low-voltage output signal and outputs a high-voltage signal according to the corresponding low-voltage output signal. The high-voltage signal output by each high-voltage signal output circuit is a signal with the same frequency but different phase.

[0078] Among them, multiple high-voltage signal output circuits include a first high-voltage signal output circuit 310, a second high-voltage signal output circuit 320...the Nth high-voltage signal output circuit 3N0. The first high-voltage signal output circuit 310 is connected to the low-voltage output signal SLO1 and outputs the high-voltage signal SHO1; the second high-voltage signal output circuit 320 is connected to the low-voltage output signal SLO2 and outputs the high-voltage signal SHO2; the Nth high-voltage signal output circuit 3N0 is connected to the low-voltage output signal SLON and outputs the high-voltage signal SHON.

[0079] According to the solution of the embodiment of the present invention, through the precise coordination of the low-voltage input signal and the circuit structure, multiple groups of high-voltage signals with the same frequency but different phases can be generated. Specifically, the low-voltage output signal generating circuit 200 generates multiple low-voltage output signals with the same frequency but different phases based on the low-voltage input signal, and then multiple high-voltage signal output circuits generate high-voltage signals based on the corresponding low-voltage output signals, thereby realizing phase control and frequency synchronization of the high-voltage signal. The technical solution of the present invention effectively reduces the overall power consumption of the circuit, while realizing frequency synchronization and precise phase control of the high-voltage signal, and helps to reduce the circuit area, thereby improving the integration and reliability of the system.

[0080] Figure 2 FIG. 1 shows a topological structure diagram of a power supply circuit 100 according to an embodiment of the present invention. Figure 2 As shown, in the power supply circuit 100, the high voltage PH is connected to ground sequentially through the nineteenth switch M19 and the fourth resistor R4. The high voltage PH is also connected to ground sequentially through the fifth resistor R5 and the first voltage zener diode D1. The high voltage PH is also connected to ground sequentially through the second voltage zener diode D2 and the sixth resistor R6. The high voltage PH is also connected to ground sequentially through the seventh resistor R7 and the twentieth switch M20. The control terminal of the nineteenth switch M19 is connected between the fifth resistor R5 and the first voltage zener diode D1, and the control terminal of the twentieth switch M20 is connected between the second voltage zener diode D2 and the sixth resistor R6. The current output terminal voltage of the nineteenth switch M19 is the first low voltage PL1, and the current input terminal voltage of the twentieth switch M20 is the second low voltage PL2.

[0081] In this embodiment, the reverse breakdown voltage of the first Zener diode D1 is VD1, and the reverse breakdown voltage of the second Zener diode D2 is VD2. Both the reverse breakdown voltage VD1 and the reverse breakdown voltage VD2 are less than the high voltage PH. The turn-on threshold voltage VTH19 of the nineteenth switch M19 is less than the reverse breakdown voltage VD1, and the turn-on threshold voltage VTH20 of the twentieth switch M20 is less than the reverse breakdown voltage VD2.

[0082] In the above embodiment, the working principle of the power supply circuit 100 is as follows: when the power supply circuit 100 is powered on, a high voltage PH is input to the power supply circuit 100. Since the high voltage PH is higher than the reverse breakdown voltages VD1 and VD2, the first voltage stabilizing diode D1 and the second voltage stabilizing diode D2 are both broken down. At this time, the voltage at the control terminal of the nineteenth switch tube M19 is the reverse breakdown voltage VD1. When the nineteenth switch tube M19 is not turned on, the voltage at its current output terminal is the ground voltage GND, and the voltage difference between the control terminal and the current output terminal of the nineteenth switch tube M19 is the reverse breakdown voltage VD1. The turn-on threshold voltage VTH19 of the nineteenth switch tube M19 is less than the reverse breakdown voltage VD1. Therefore, the voltage difference between the control terminal and the current output terminal of the nineteenth switch tube M19 is greater than the turn-on threshold voltage VTH19 of the nineteenth switch tube M19, and the nineteenth switch tube M19 is turned on. At this time, the voltage at the current output terminal of the nineteenth switch tube M19 is the first low voltage At the same time, the control terminal voltage of the twentieth switch tube M20 is Since the voltage at the current input terminal of the 20th switch tube M20 is PH when it is not turned on, the voltage difference between the control terminal and the current input terminal of the 20th switch tube M20 is VD2, and the turn-on threshold voltage VTH20 of the 20th switch tube M20 is less than the reverse breakdown voltage VD2, the 20th switch tube M20 is turned on. At this time, the voltage at the current input terminal of the 20th switch tube M20 is the second low voltage. .

[0083] Based on the above analysis, it can be seen that by configuring Zener diodes with different parameters in the power supply circuit 100, the output voltages of the first low voltage PL1 and the second low voltage PL2 can be adjusted. Furthermore, because the conduction threshold voltage of the MOS transistor is constant, the stability and reliability of the first low voltage PL1 and the second low voltage PL2 are ensured. Furthermore, the gate-source voltage difference between the nineteenth switch M19 and the twentieth switch M20 in the power supply circuit 100 is clamped by the corresponding Zener diodes. Therefore, the switches in the power supply circuit 100 can all employ switches with a low gate-source voltage difference.

[0084] Figure 3 FIG. 2 shows a topological structure diagram of a low voltage output signal generating circuit 200 according to an embodiment of the present invention. Figure 3As shown, the low-voltage output signal generating circuit 200 includes a first resistor R1, a second resistor R2, an eleventh switch M11, a twelfth switch M12, a comparator A1, a first controllable current source G1, a second controllable current source G2, and a third controllable current source G3. In the low-voltage output signal generating circuit 200, the first low-voltage PL1 is grounded sequentially through the first resistor R1, the eleventh switch M11, the twelfth switch M12, and the second resistor R2. The first low-voltage PL1 is also grounded sequentially through the second controllable current source G2 and the third controllable current source G3. The positive control terminals of the first controllable current source G1 and the second controllable current source G2 are both connected to the first low-voltage PL1, and the negative control terminals are both connected to the current input terminal of the eleventh switch M11. The current input terminal of the first controllable current source G1 is connected to the first low-voltage PL1, and the current output terminal is connected to the positive control terminal of the third controllable current source G3. The positive control terminal of the third controllable current source G3 is also connected to the current output terminal of the twelfth switch M12, and the negative control terminal of the third controllable current source G3 is grounded. A third node E3 between the eleventh switch M11 and the twelfth switch M12 is connected to the first low-voltage input signal SL1. The comparator A1 has a positive input terminal connected to the first comparison voltage V1, a negative input terminal connected to the first low-voltage input signal SL1, and an output terminal connected to the control terminals of the eleventh switch M11 and the twelfth switch M12.

[0085] In one embodiment, the current coefficient of the third controllable current source G3 is less than 1, and the current coefficients of the first controllable current source G1 and the second controllable current source G2 are equal to 1.

[0086] In one embodiment, the first comparison voltage V1 is a fixed value.

[0087] The first low-voltage input signal SL1 includes a first sub-signal SL11 and a second sub-signal SL12. The voltage of the first sub-signal SL11 is lower than the first comparison voltage V1, and the first low-voltage input signal terminal draws a first current I1 from the third node E3. The voltage of the second sub-signal SL12 is higher than the first comparison voltage V1, and the first low-voltage input signal terminal injects the first current I1 into the third node E3.

[0088] In the above embodiment, after the circuit is powered on, when the first sub-signal SL11 of the first low-voltage input signal SL1 is input into the circuit, comparator A1 outputs a high level. The first low-voltage input signal terminal draws a first current I1 from the third node E3. Consequently, the voltage at the current output terminal of the eleventh switch M11 and the voltage at the current input terminal of the twelfth switch M12 are pulled low, turning the eleventh switch M11 on and the twelfth switch M12 off. At this point, the current flowing through the first resistor R1 is the first current I1. Because the current coefficients of the first controllable current source G1 and the second controllable current source G2 are equal to 1, the current generated by the first controllable current source G1 and the current generated by the second controllable current source G2 are both equal to the current flowing through the first resistor R1, i.e., equal to the first current I1. At this time, the current generated in the first controllable current source G1 flows into the second resistor R2. Since the current coefficient of the third controllable current source G3 is less than 1, the current generated in the third controllable current source G3 is less than the first current I1, that is, the current generated in the second controllable current source G2 is greater than the current generated in the third controllable current source G3, and the voltage of the fourth node E4 between the second controllable current source G2 and the third controllable current source G3 is pulled up.

[0089] When the second sub-signal SL12 of the first low-voltage input signal SL1 is input into the circuit, comparator A1 outputs a low level. The first low-voltage input signal terminal injects the first current I1 into the third node E3. As a result, the voltage at the current output terminal of the eleventh switch M11 and the voltage at the current input terminal of the twelfth switch M12 are pulled high, turning the eleventh switch M11 off and the twelfth switch M12 on. At this point, no current flows through the first resistor R1, the first controllable current source G1, and the second controllable current source G2. The first current I1 flows directly into the second resistor R2, and the current generated in the third controllable current source G3 becomes the first current I1, thereby lowering the voltage at the fourth node E4 between the second controllable current source G2 and the third controllable current source G3.

[0090] From the above analysis, it can be seen that when the first sub-signal SL11 is input into the circuit, the fourth node E4 is at a high level; when the second sub-signal SL12 is input into the circuit, the fourth node E4 is at a low level.

[0091] In one embodiment, the low-voltage output signal generating circuit 200 further includes a third resistor R3, a fourth controllable current source G4, a fifth controllable current source G5, a sixth controllable current source G6, and a seventh controllable current source G7. A first end of the third resistor R3 is connected to the first low voltage PL1. Current input terminals and positive control terminals of the fifth controllable current source G5, the sixth controllable current source G6, and the seventh controllable current source G7 are all connected to the first low voltage PL1. Negative control terminals of the fifth controllable current source G5, the sixth controllable current source G6, and the seventh controllable current source G7 are all connected to the second end of the third resistor R3 and are collectively connected to the current input terminal of the fourth controllable current source G4. The current output terminal and negative control terminal of the fourth controllable current source G4 are both grounded, and the positive control terminal of the fourth controllable current source G4 is connected to the positive control terminal of the third controllable current source G3.

[0092] In one embodiment, the current coefficients of the fourth controllable current source G4, the fifth controllable current source G5, the sixth controllable current source G6, and the seventh controllable current source G7 are equal to 1. Therefore, the current flowing through the fourth controllable current source G4 is equal to the current flowing through the second resistor R2. The current flowing through the fifth controllable current source G5, the sixth controllable current source G6, and the seventh controllable current source G7 is equal to the current flowing through the third resistor R3. Since the third resistor R3 is connected to the fourth controllable current source G4, the current flowing through the fifth controllable current source G5, the sixth controllable current source G6, and the seventh controllable current source G7 is equal to the current flowing through the fourth controllable current source G4, that is, equal to the current flowing through the second resistor R2.

[0093] According to the above analysis, when the first sub-signal SL11 is input into the circuit, the current flowing through the second resistor R2 is the first current I1, and the currents flowing through the fourth controllable current source G4, the third resistor R3, the fifth controllable current source G5, the sixth controllable current source G6, and the seventh controllable current source G7 are all the first current I1. When the second sub-signal SL12 is input into the circuit, the current flowing through the second resistor R2 is the first current I1, and the currents flowing through the fourth controllable current source G4, the third resistor R3, the fifth controllable current source G5, the sixth controllable current source G6, and the seventh controllable current source G7 are all the first current I1.

[0094] In one embodiment, the low-voltage output signal generating circuit 200 further includes a thirteenth switch M13, a fourteenth switch M14, a first capacitor C1, a ninth inverter F9, and a tenth inverter F10. The current input terminal of the thirteenth switch M13 is connected to the current output terminal of the fifth controllable current source G5, the current output terminal of the thirteenth switch M13 is grounded via the fourteenth switch M14, and the control terminal is connected to the second low-voltage input signal SL2. The control terminal of the fourteenth switch M14 is connected to the control terminal of the thirteenth switch M13. The first terminal of the first capacitor C1 is connected to the current input terminal of the fourteenth switch M14, and the second terminal is grounded. The input terminal of the ninth inverter F9 is connected to the current input terminal of the fourteenth switch M14, and the output terminal outputs the first low-voltage output signal SLO1. The input terminal of the tenth inverter F10 is connected to the output terminal of the ninth inverter F9, and the output terminal of the tenth inverter F10 outputs the second low-voltage output signal SLO2.

[0095] Figure 4 FIG. 4 shows a waveform diagram of the second low voltage input signal SL2 according to an embodiment of the present invention. Figure 4 As shown, the second low-voltage input signal SL2 is a periodic signal. The second low-voltage input signal SL2 is input into the control terminals of the thirteenth switch tube M13 and the fourteenth switch tube M14.

[0096] When the second low-voltage input signal SL2 is at a high level, the thirteenth switch tube M13 is turned off and the fourteenth switch tube M14 is turned on, then the terminal voltage of the first capacitor C1 is instantly pulled down to the ground voltage GND through the fourteenth switch tube M14, therefore, the first low-voltage output signal SLO1 output by the ninth inverter F9 is instantly at a high level. When the second low-voltage input signal SL2 switches from a high level to a low level, the thirteenth switch tube M13 is turned on and the fourteenth switch tube M14 is turned off, and the first capacitor C1 is charged through the fifth controllable current source G5 and the thirteenth switch tube M13. From the above analysis, it can be seen that the current generated in the fifth controllable current source G5 is the first current I1, then the charging current of the first capacitor C1 at this time is the first current I1. According to the capacitor charging and discharging formula It can be seen that the time for the terminal voltage of the first capacitor C1 to charge from 0 to the flip voltage VH9 of the ninth inverter F9 is That is, when the second low-voltage input signal SL2 switches from a high level to a low level, after time t1, the terminal voltage of the first capacitor C1 becomes greater than the flip voltage VH9 of the ninth inverter F9. At this time, the first low-voltage output signal SLO1 output by the ninth inverter F9 switches from a high level to a low level. When the second low-voltage input signal SL2 switches back to a high level, the thirteenth switch M13 turns off and the fourteenth switch M14 turns on. The terminal voltage of the first capacitor C1 is then instantaneously pulled down to the ground voltage GND through the fourteenth switch M14, and the first low-voltage output signal SLO1 instantaneously switches to a high level.

[0097] From the above analysis, the waveform comparison diagram of the second low voltage input signal SL2 and the first low voltage output signal SLO1 is as follows: Figure 5 See Figure 5 The first low-voltage output signal SLO1 output by the low-voltage output signal generating circuit 200 has the same frequency as the second low-voltage input signal SL2, but has a falling edge phase lag, and the lag phase time is Therefore, at this time, by adjusting the magnitude of the external first current I1, the lag phase of the first low-voltage output signal SLO1 can be adjusted.

[0098] Since only the tenth inverter F10 is connected between the second low-voltage output signal SLO2 and the first low-voltage output signal SLO1 , the second low-voltage output signal SLO2 and the first low-voltage output signal SLO1 have the same frequency but opposite phases. Figure 6 FIG shows a waveform comparison diagram of the second low voltage input signal SL2 and the second low voltage output signal SLO2 according to an embodiment of the present invention. Figure 6 The second low-voltage output signal SLO2 output by the low-voltage output signal generating circuit 200 has the same frequency as the second low-voltage input signal SL2, but has an opposite phase, and the phase of the rising edge lags behind the phase of the falling edge of the second low-voltage input signal SL2. The delayed phase time is Therefore, at this time, by adjusting the magnitude of the external first current I1, the lag phase of the second low-voltage output signal SLO2 can be adjusted.

[0099] In one embodiment, the low-voltage output signal generating circuit 200 further includes an eleventh inverter F11, a twelfth inverter F12, a fifteenth switch M15, a sixteenth switch M16, a second capacitor C2, a first OR gate O1, a first AND gate N1, and a first NAND gate NF1. The current input terminal of the fifteenth switch M15 is connected to the current output terminal of the sixth controllable current source G6, the current output terminal of the fifteenth switch M15 is connected to ground via the sixteenth switch M16, and the control terminal of the fifteenth switch M15 is connected to the control terminal of the sixteenth switch M16. The input terminal of the eleventh inverter F11 receives the second low-voltage input signal SL2, and the output terminal is connected to the control terminal of the fifteenth switch M15. The first terminal of the second capacitor C2 is connected to the current input terminal of the sixteenth switch M16, and the second terminal is grounded. The input of the twelfth inverter F12 is connected to the current input of the sixteenth switch M16, and the output of the twelfth inverter F12 is connected to the first input of the first OR gate O1. The second input of the first OR gate O1 is connected to the first input of the first NAND gate NF1, and both are connected to the current output of the second controllable current source G2. The second input of the first NAND gate NF1 is connected to the first input of the first OR gate O1, and the first input of the first OR gate O1 is the sixth node E6. The first input of the first AND gate N1 is connected to the output of the first OR gate O1, and the second input of the first AND gate N1 is connected to the output of the first NAND gate NF1. The output of the first AND gate N1 outputs the third low-voltage output signal SLO3.

[0100] In this embodiment, the second low-voltage input signal SL2 is inverted by the eleventh inverter F11 and then input to the control terminals of the fifteenth and sixteenth switching transistors M15 and M16. The signal at the fifth node E5 between the control terminals of the fifteenth and sixteenth switching transistors M15 and M16 is in phase with the second low-voltage input signal SL2. When the second low-voltage input signal SL2 is low, the fifth node E5 is high, the fifteenth switching transistor M15 is off, and the sixteenth switching transistor M16 is on. The terminal voltage of the second capacitor C2 is instantly pulled down to the ground voltage GND via the sixteenth switching transistor M16, and the sixth node E6 is instantly pulled up to a high level. When the second low-voltage input signal SL2 switches from a low level to a high level, the fifth node E5 switches from a high level to a low level, the fifteenth switching transistor M15 is on, and the sixteenth switching transistor M16 is off. The second capacitor C2 is charged via the sixth controllable current source G6 and the fifteenth switching transistor M15. According to the above analysis, the current generated by the sixth controllable current source G6 is the first current I1, and the charging current of the second capacitor C2 is the first current I1. According to the capacitor charging and discharging formula It can be seen that the time for the terminal voltage of the second capacitor C2 to charge from 0 to the flip voltage VH12 of the twelfth inverter F12 is That is, when the second low-voltage input signal SL2 switches from a low level to a high level, after time t2, the terminal voltage of the second capacitor C2 becomes greater than the flip voltage VH12 of the twelfth inverter F12. At this time, the output of the twelfth inverter F12 switches from a high level to a low level, that is, the sixth node E6 switches from a high level to a low level. When the second low-voltage input signal SL2 switches back to a low level, the fifteenth switch M15 turns off and the sixteenth switch M16 turns on. The terminal voltage of the second capacitor C2 is then momentarily pulled down to the ground voltage GND via the sixteenth switch M16, and the sixth node E6 momentarily outputs a high level.

[0101] Based on the above analysis, it can be seen that when the first sub-signal SL11 of the first low-voltage input signal SL1 is input into the low-voltage output signal generating circuit 200, the fourth node E4 is at a high level. At this time, the first input of the first NAND gate NF1 and the second input of the first OR gate O1 are both at a high level. Therefore, the first OR gate O1 necessarily outputs a high level. Furthermore, the second input of the first NAND gate NF1 is in phase with the sixth node E6, so the output signal of the first NAND gate NF1 is in phase with the sixth node E6. Furthermore, the first input of the first AND gate N1 is connected to the output signal of the first OR gate O1, and the second input of the first AND gate N1 is connected to the output signal of the first NAND gate NF1. Since the output signal of the first OR gate O1 is a high level signal, the signal output by the first AND gate N1 is the output signal of the first NAND gate NF1, which is in phase with the sixth node E6. Therefore, the third low-voltage output signal SLO3 is in phase with the sixth node E6.

[0102] From the above analysis, the waveform comparison diagram of the second low voltage input signal SL2, the sixth node E6 and the third low voltage output signal SLO3 is shown in FIG. Figure 7 See Figure 7 The third low-voltage output signal SLO3 output by the low-voltage output signal generating circuit 200 has the same frequency as the second low-voltage input signal SL2, but has a rising edge phase lag, and the lag phase time is Therefore, at this time, by adjusting the magnitude of the external first current I1, the lag phase of the third low-voltage output signal SLO3 can be adjusted.

[0103] In one embodiment, the low-voltage output signal generating circuit 200 further includes a thirteenth inverter F13, a fourteenth inverter F14, a seventeenth switch M17, an eighteenth switch M18, a third capacitor C3, a second OR gate O2, a second AND gate N2, and a second NAND gate NF2. The current input terminal of the seventeenth switch M17 is connected to the current output terminal of the seventh controllable current source G7, the current output terminal of the seventeenth switch M17 is grounded via the eighteenth switch M18, and the control terminal of the seventeenth switch M17 is connected to the control terminal of the eighteenth switch M18, and both are connected to the output terminal of the eleventh inverter F11. A first terminal of the third capacitor C3 is connected to the current input terminal of the eighteenth switch M18, and a second terminal is grounded. The input terminal of the thirteenth inverter F13 is connected to the current input terminal of the eighteenth switch M18, and the output terminal is connected to the first input terminal of the second OR gate O2, the first input terminal of which is the seventh node E7. The input of the fourteenth inverter F14 is connected to the current output of the second controllable current source G2, and the output is connected to the first input of the second NAND gate NF2, the first input of which is the eighth node E8. The first input of the second OR gate O2 is also connected to the second input of the second NAND gate NF2, which is also connected to the second input of the second OR gate O2. The first input of the second AND gate N2 is connected to the output of the second OR gate O2, the second input of the second AND gate N2 is connected to the output of the second NAND gate NF2, and the output of the second AND gate N2 outputs the fourth low-voltage output signal SLO4.

[0104] In this embodiment, the control ends of the seventeenth switch tube M17 and the eighteenth switch tube M18 are both controlled by the fifth node E5, and the fifth node E5 signal is inversely proportional to the second low-voltage input signal SL2. When the second low-voltage input signal SL2 is at a low level, the fifth node E5 is at a high level, the seventeenth switch tube M17 is turned off, and the eighteenth switch tube M18 is turned on, then the terminal voltage of the third capacitor C3 is instantly pulled down to the ground voltage GND through the eighteenth switch tube M18, and then the seventh node E7 is instantly pulled up to a high level. When the second low-voltage input signal SL2 is switched from a low level to a high level, the fifth node E5 is switched from a high level to a low level, the seventeenth switch tube M17 is turned on, and the eighteenth switch tube M18 is turned off, then the third capacitor C3 is charged through the seventh controllable current source G7 and the seventeenth switch tube M17. According to the above analysis, it can be seen that the current generated in the seventh controllable current source G7 is the first current I1, then the charging current of the third capacitor C3 is the first current I1, according to the capacitor charging and discharging formula It can be seen that the time for the terminal voltage of the third capacitor C3 to charge from 0 to the flip voltage VH13 of the thirteenth inverter F13 is That is, when the second low-voltage input signal SL2 switches from a low level to a high level, after time t3, the terminal voltage of the third capacitor C3 becomes greater than the flip voltage VH13 of the thirteenth inverter F13. At this time, the output of the thirteenth inverter F13 switches from a high level to a low level, that is, the seventh node E7 switches from a high level to a low level. When the second low-voltage input signal SL2 switches back to a low level, the seventeenth switch M17 turns off and the eighteenth switch M18 turns on. The terminal voltage of the third capacitor C3 is then momentarily pulled down to the ground voltage GND via the eighteenth switch M18, and the seventh node E7 momentarily outputs a high level.

[0105] Based on the above analysis, it can be seen that when the first sub-signal SL11 of the first low-voltage input signal SL1 is input into the low-voltage output signal generating circuit 200, the fourth node E4 is at a high level. At this time, the eighth node E8 is at a low level. That is, the first input of the second NAND gate NF2 and the second input of the second OR gate O2 are both at a low level. Therefore, the second NAND gate NF2 must output a high level. Furthermore, the first input of the second OR gate O2 is in phase with the seventh node E7, so the output signal of the second OR gate O2 is in phase with the seventh node E7. Furthermore, the first input of the second AND gate N2 is connected to the output signal of the second OR gate O2, and the second input of the second AND gate N2 is connected to the output signal of the second NAND gate NF2. Since the output signal of the second NAND gate NF2 is a high level signal, the signal output by the second AND gate N2 is the output signal of the second OR gate O2, which is in phase with the seventh node E7. Therefore, the fourth low-voltage output signal SLO4 is in phase with the seventh node E7.

[0106] From the above analysis, the waveform comparison diagram of the second low voltage input signal SL2 and the fourth low voltage output signal SLO4 is shown as follows: Figure 8 See Figure 8 The fourth low-voltage output signal SLO4 output by the low-voltage output signal generating circuit 200 has the same frequency as the second low-voltage input signal SL2, but has an opposite phase, and the phase of the falling edge lags behind the phase of the rising edge of the second low-voltage input signal SL2. The delayed phase time is Therefore, at this time, by adjusting the magnitude of the external first current I1, the lag phase of the fourth low-voltage output signal SLO4 can be adjusted.

[0107] In one embodiment, when the second sub-signal SL12 of the first low-voltage input signal SL1 is input into the low-voltage output signal generating circuit 200, the fourth node E4 is at a low level. At this point, the waveforms of the first low-voltage output signal SLO1 and the second low-voltage output signal SLO2 are identical to those when the first sub-signal SL11 is input into the low-voltage output signal generating circuit 200. The waveforms of the sixth node E6 and the seventh node E7 are identical to those when the first sub-signal SL11 is input into the low-voltage output signal generating circuit 200, while the waveform of the eighth node E8 is opposite to that when the first sub-signal SL11 is input into the low-voltage output signal generating circuit 200. At this point, the voltages of the signals at the second input terminal of the first OR gate O1 and the first input terminal of the first NAND gate NF1 are low, causing the first NAND gate NF1 to output a high level. The signal output by the first OR gate O1 is in phase with the sixth node E6, so the third low-voltage output signal SLO3 is in phase with the sixth node E6. At the same time, the voltages of the signals at the first input terminal of the second NAND gate NF2 and the second input terminal of the second OR gate O2 become high, and the second OR gate O2 outputs a high level. The signal output by the second NAND gate NF2 is in phase opposite to the seventh node E7. Therefore, at this time, the fourth low-voltage output signal SLO4 is in phase opposite to the seventh node E7.

[0108] According to the above embodiment, in the low-voltage output signal generating circuit 200 of the present invention, the high-voltage sources of the comparator A1, each inverter, each OR gate, each AND gate and each NAND gate are all the first low voltage PL1, and the low-voltage sources are all the ground voltage GND. Therefore, the high-level voltage of the low-voltage output signals SLO1, SLO2...SLON output by the low-voltage output signal generating circuit 200 is the first low voltage PL1, and the low-level voltage is the ground voltage GND.

[0109] According to the above embodiment, the low-voltage output signal generation circuit 200 performs logical processing on the first low-voltage input signal SL1 and the second low-voltage input signal SL2, thereby simultaneously generating multiple low-voltage output signals having the same frequency but different phases. Furthermore, the phase difference between the low-voltage output signals can be dynamically adjusted by adjusting the magnitude of the external first current I1. This ensures frequency synchronization between the low-voltage output signals while achieving high-precision phase control, meeting the precise signal timing requirements of different application scenarios. Furthermore, since the high level of the signals output by the low-voltage output signal generation circuit 200 is all the first low voltage PL1, analysis of the power supply circuit 100 indicates that the first low voltage PL1 is isolated from the high voltage PH by the nineteenth switch M19, preventing the high voltage PH from affecting the output of the low-voltage output signal generation circuit 200. Therefore, the low-voltage output signal generation circuit 200 can be composed entirely of low-voltage devices, and each switch can be a switch with low drain-source and gate-source voltage differences, thereby reducing the size and energy consumption of the low-voltage output signal generation circuit 200.

[0110] Furthermore, the number of signals output by the low-voltage output signal generation circuit 200 can be flexibly configured based on actual circuit requirements. When receiving any sub-signal of the first low-voltage input signal SL1, it can simultaneously generate multiple control signals with the same frequency but different phases. Therefore, the first low-voltage input signal SL1 can be multiplexed with other low-voltage signals, expanding the application range of the control signal output circuit. Furthermore, the high-voltage PH generates a supply current through the nineteenth switch M19 in the power supply circuit 100, which flows directly into the low-voltage output signal generation circuit 200, effectively reducing the operating energy consumption of the entire combinational logic circuit.

[0111] Figure 9 The topology diagram of the high voltage signal output circuit according to one embodiment of the present invention is shown. The multiple high voltage signal output circuits in the high voltage signal combination logic circuit of the present invention all adopt the following structure: Figure 9 The following describes the working principle of the first high-voltage signal output circuit 310 as an example:

[0112] The first high-voltage signal output circuit 310 includes a first high-voltage signal output switch transistor M1, a second high-voltage signal output switch transistor M2, and a first high-voltage signal control module 311. The first high-voltage signal control module 311 includes a first high-voltage source, a second high-voltage source, a first low-voltage source, a second low-voltage source, an input terminal, a first output terminal, and a second output terminal. The input terminal of the first high-voltage signal control module 311 is connected to the first low-voltage output signal SLO1. The first output terminal of the first high-voltage signal control module 311 is connected to the control terminal of the first high-voltage signal output switch transistor M1. The second output terminal of the first high-voltage signal control module 311 is connected to the control terminal of the second high-voltage signal output switch transistor M2. The current input terminal of the first high-voltage signal output switch transistor M1 is connected to the high voltage PH, and the current output terminal is connected to the current input terminal of the second high-voltage signal output switch transistor M2. The current output terminal of the second high-voltage signal output switch transistor M2 is grounded. The first high voltage signal control module 311 is used to control the on and off of the first high voltage signal output switch tube M1 and the second high voltage signal output switch tube M2 according to the high voltage PH, the second low voltage PL2, the first low voltage PL1 and the first low voltage output signal SLO1.

[0113] In one embodiment, the first high-voltage signal control module 311 includes a first logic unit, a second logic unit, a third switch M3, a fourth switch M4, a fifth switch M5, a sixth switch M6, a seventh switch M7, and an eighth switch M8. In the first high-voltage signal control module 311, the high voltage PH is connected to ground sequentially through the third switch M3, the fourth switch M4, and the fifth switch M5. The control terminal of the fifth switch M5 is connected to the first logic unit. The high voltage PH is also connected to ground sequentially through the sixth switch M6, the seventh switch M7, and the eighth switch M8. The control terminal of the eighth switch M8 is connected to the second logic unit. The control terminals of the fourth switch M4 and the seventh switch M7 are both connected to the second low voltage PL2. The input terminal of the first logic unit serves as the input terminal of the high-voltage signal control module, and the output terminal of the first logic unit is connected to the input terminal of the second logic unit.

[0114] In one embodiment, the first logic unit includes a sixth inverter F6 and a seventh inverter F7, and the second logic unit includes an eighth inverter F8. The input of the sixth inverter F6 serves as the input of the first high-voltage signal control module 311, and its output is connected to the input of the eighth inverter F8 via the seventh inverter F7. The output of the eighth inverter F8 serves as the second output of the first high-voltage signal control module 311. The output of the seventh inverter F7 is also connected to the control terminal of the fifth switch M5, and the output of the eighth inverter F8 is also connected to the control terminal of the eighth switch M8. The high reference terminals of the sixth, seventh, and eighth inverters F6, F7, and F8 are all connected to the first low voltage PL1, and their low reference terminals are all grounded.

[0115] In the above embodiment, the input terminal of the sixth inverter F6 is connected to the first low-voltage output signal SLO1 as the input terminal of the first high-voltage signal control module 311. When the first low-voltage output signal SLO1 is low, the sixth inverter F6 outputs a high level, the seventh inverter F7 outputs a low level, and the eighth inverter F8 outputs a high level to the second high-voltage signal output switch M2, turning on the second high-voltage signal output switch M2. When the first low-voltage output signal SLO1 is high, the sixth inverter F6 outputs a low level, the seventh inverter F7 outputs a high level, and the eighth inverter F8 outputs a low level to the second high-voltage signal output switch M2, turning off the second high-voltage signal output switch M2.

[0116] When the first low-voltage output signal SLO1 is at a low level, preferably at ground level, the seventh inverter F7 outputs a low level and the eighth inverter F8 outputs a high level, turning off the fifth switch M5 and turning on the eighth switch M8. At this point, the fourth switch M4 is off and the seventh switch M7 is turned on, pulling down the voltage at the current output terminal of the seventh switch M7. Furthermore, the control terminal of the seventh switch M7 is connected to the second low voltage PL2. At this point, the seventh switch M7 operates in the saturation region, generating a current flowing from the current input terminal to the current output terminal. Consequently, the voltage at the current input terminal of the seventh switch M7 is clamped to VGS7 + PL2, where VGS7 is the voltage difference between the control terminal and the current input terminal of the seventh switch M7. Consequently, the voltage at the second node E2 is VGS7 + PL2.

[0117] When the first low-voltage output signal SLO1 is at a high level, preferably the first low voltage PL1, the seventh inverter F7 outputs a high level and the eighth inverter F8 outputs a low level, turning on the fifth switch M5 and turning off the eighth switch M8. At this point, the seventh switch M7 is turned off, turning on the fourth switch M4, and the voltage at the current output terminal of the fourth switch M4 is pulled down. Furthermore, the control terminal of the fourth switch M4 is connected to the second low voltage PL2. At this point, the fourth switch M4 operates in the saturation region, generating a current flowing from the current input terminal to the current output terminal. Consequently, the voltage at the current input terminal of the fourth switch M4 is clamped to VGS4 + PL2, where VGS4 is the voltage difference between the control terminal and the current input terminal of the fourth switch M4. Therefore, the voltage at the first node E1 is VGS4 + PL2.

[0118] In one embodiment, the first high-voltage signal control module 311 further includes an RS flip-flop B1, a first inverter F1, a second inverter F2, and a third inverter F3. The input of the first inverter F1 is connected to a first node E1 between the third switch M3 and the fourth switch M4, and the output is connected to the set terminal of the RS flip-flop B1. The input of the second inverter F2 is connected to a second node E2 between the sixth switch M6 and the seventh switch M7, and the output is connected to the reset terminal of the RS flip-flop B1. The input of the third inverter F3 is connected to the inverting output terminal of the RS flip-flop B1, and the output serves as the first output terminal of the first high-voltage signal control module 311. The high reference terminals of the RS flip-flop B1, the first inverter F1, the second inverter F2, and the third inverter F3 are all connected to the high voltage PH, and the low reference terminals are all connected to the second low voltage PL2.

[0119] In one embodiment, the first high-voltage signal control module 311 further includes a ninth switch M9, a tenth switch M10, a fourth inverter F4, and a fifth inverter F5. The input of the fourth inverter F4 is connected to the output of the second inverter F2, and the output of the fourth inverter F4 is connected to the control terminal of the ninth switch M9. The current input of the ninth switch M9 is connected to the first node E1, and the current output is connected to the control terminal of the fourth switch M4. The control terminal of the ninth switch M9 is also connected to the control terminal of the third switch M3. The input of the fifth inverter F5 is connected to the output of the first inverter F1, and the output of the fifth inverter F5 is connected to the control terminal of the tenth switch M10. The current input of the tenth switch M10 is connected to the second node E2, and the current output is connected to the control terminal of the seventh switch M7. The control terminal of the tenth switch M10 is also connected to the control terminal of the sixth switch M6. The high reference terminals of the fourth inverter F4 and the fifth inverter F5 are both connected to the high voltage PH, and the low reference terminals are both connected to the second low voltage PL2.

[0120] In the above embodiment, when the first low-voltage output signal SLO1 is low, according to the above analysis, the voltage at the second node E2 is VGS7 + PL2. At this point, the flip threshold voltage of the second inverter F2 is designed to be greater than the voltage difference VGS7 between the control terminal and the current input terminal of the seventh switch M7. Furthermore, since the low reference voltage of the second inverter F2 is the second low voltage PL2, the voltage at the second node E2 is low for the second inverter F2, and the second inverter F2 outputs a high voltage. At this point, the fourth inverter F4 outputs a low voltage, turning on the third switch M3 and turning off the ninth switch M9. The voltage at the first node E1 is pulled up by the third switch M3, causing the first inverter F1 to output a low voltage and the fifth inverter F5 to output a high voltage. At this point, the tenth switch M10 turns on, while the sixth switch M6 turns off, further pulling the voltage at the second node E2 down to the second low voltage PL2.

[0121] As can be seen, when the first low-voltage output signal SLO1 is low, the set terminal of the RS flip-flop B1 is low and the reset terminal is high. Consequently, the inverting output terminal of the RS flip-flop B1 outputs a low level, and the third inverter F3 outputs a high level, thereby turning off the first high-voltage signal output switch M1. Furthermore, according to the above analysis, when the first low-voltage output signal SLO1 is low, the second high-voltage signal output switch M2 is turned on. Therefore, the first high-voltage signal SHO1 output by the high-voltage signal output circuit is pulled down to ground by the second high-voltage signal output switch M2.

[0122] When the first low-voltage output signal SLO1 is high, according to the above analysis, the voltage at the first node E1 is VGS4 + PL2. At this point, the flip threshold voltage of the first inverter F1 is designed to be greater than the voltage difference VGS4 between the control terminal and the current input terminal of the fourth switch M4. Furthermore, since the low reference voltage of the first inverter F1 is the second low voltage PL2, the voltage at the first node E1 is low for the first inverter F1, and the first inverter F1 outputs a high voltage. At this point, the fifth inverter F5 outputs a low voltage, turning on the sixth switch M6 and turning off the tenth switch M10. The voltage at the second node E2 is pulled up by the sixth switch M6, causing the second inverter F2 to output a low voltage and the fourth inverter F4 to output a high voltage. At this point, the ninth switch M9 turns on, while the third switch M3 turns off, further pulling the voltage at the first node E1 down to the second low voltage PL2.

[0123] As can be seen, when the first low-voltage output signal SLO1 is high, the set terminal of the RS flip-flop B1 is high and the reset terminal is low. Consequently, the inverting output terminal of the RS flip-flop B1 outputs a high level, and the third inverter F3 outputs a low level, thereby turning on the first high-voltage signal output switch M1. Furthermore, according to the above analysis, when the first low-voltage output signal SLO1 is high, the second high-voltage signal output switch M2 is turned off. Therefore, the first high-voltage signal SHO1 output by the high-voltage signal output circuit is pulled high to the high voltage PH by the first high-voltage signal output switch M1.

[0124] According to the above analysis, when the first low voltage output signal SLO1 is at a high level, the first high voltage signal output switch tube M1 is turned on, and the gate-source voltage difference is The second high-voltage signal output switch tube M2 is turned off, and its gate-source voltage difference is 0. When the first low-voltage output signal SLO1 is at a low level, the second high-voltage signal output switch tube M2 is turned on, and its gate-source voltage difference is The first high-voltage signal output switch tube M1 is turned off, and its gate-source voltage difference is 0. Therefore, regardless of whether the first low-voltage output signal SLO1 is at a high level or a low level, the gate-source voltage difference between the first high-voltage signal output switch tube M1 and the second high-voltage signal output switch tube M2 is much lower than the high voltage PH. Therefore, the first high-voltage signal output switch tube M1 and the second high-voltage signal output switch tube M2 can use switch tubes with a low gate-source voltage difference. Similarly, other switch tubes in the high-voltage signal output circuit can also use switch tubes with a low gate-source voltage difference.

[0125] It should be noted that, in the combinational logic circuit for outputting high-voltage signals of the present invention, other high-voltage signal output circuits all adopt the same circuit structure as the first high-voltage signal output circuit 310 and have the same working principle, which will not be elaborated here.

[0126] Figure 10 FIG1 shows an input and output waveform diagram of a high voltage signal output circuit according to an embodiment of the present invention. Figure 10 As shown, the high-voltage signal output circuit can receive a relatively low-voltage low-voltage output signal SLON and output a higher-voltage high-voltage signal SHON, thereby driving an external high-power switch tube, improving the reliability and power conversion efficiency of the high-voltage signal SHON. In addition, the supply current of the high-voltage signal output circuit flows directly from the high-voltage PH through the nineteenth switch tube M19 into the high-voltage signal output circuit, and the supply current of the high-voltage signal output circuit flows directly into the ground terminal through the twentieth switch tube M20, thereby reducing the energy consumption of the combinational logic circuit during operation.

[0127] Figure 11 FIG1 shows a comparison diagram of input signal and output signal waveforms of a combinational logic circuit according to an embodiment of the present invention. Figure 11 As shown, when the first low-voltage input signal SL1 is the first sub-signal, the combinational logic circuit of the present invention generates multiple high-voltage signals SHON with the same frequency but different phases based on the input first low-voltage input signal SL1 and the second low-voltage input signal SL2 through synchronous logic processing. The high voltage of the second low-voltage input signal SL2 is PL1, while the high voltage of the high-voltage signal SHON is PH.

[0128] According to the above-described embodiments, the combinational logic circuit for outputting high-voltage signals provided by the present invention generates multiple sets of high-voltage signals with the same frequency but different phases through the precise coordination of two low-voltage input signals and low-voltage switching tubes, thereby achieving frequency synchronization and precise phase control of the high-voltage signals. Furthermore, the use of switching tube designs with low gate-source voltage differences or low drain-source and gate-source voltage differences in each circuit effectively reduces the energy consumption of the overall circuit and helps to reduce the circuit area. Based on the above-described structure, the present invention can improve the system's integration and operational reliability while ensuring output accuracy, meeting the requirements of high-performance power management applications.

[0129] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A combinational logic circuit that outputs a high-voltage signal, characterized in that: include: A power supply circuit, wherein the high voltage source is connected to the high voltage PH and the low voltage source is grounded, and is used to output a first low voltage PL1 and a second low voltage PL2; a low-voltage output signal generating circuit, wherein a high-voltage source thereof is connected to the first low-voltage PL1 and the low-voltage source is grounded, and the low-voltage output signal generating circuit is connected to a first low-voltage input signal SL1 and a second low-voltage input signal SL2, and is configured to output a plurality of low-voltage output signals having the same frequency but different phases according to the first low-voltage input signal SL1 and the second low-voltage input signal SL2; Multiple high-voltage signal output circuits, each having a first high-voltage source, a second high-voltage source, a first low-voltage source, and a second low-voltage source, wherein the first high-voltage source is connected to the high-voltage PH, the second high-voltage source is connected to the first low-voltage PL1, the first low-voltage source is connected to the second low-voltage PL2, and the second low-voltage source is grounded; each high-voltage signal output circuit is connected to a corresponding low-voltage output signal and outputs a high-voltage signal based on the corresponding low-voltage output signal, and the high-voltage signals output by the multiple high-voltage signal output circuits are signals with the same frequency but different phases; The multiple high-voltage signal output circuits have the same circuit structure, and the high-voltage signal output circuits include a first high-voltage signal output switch tube M1, a second high-voltage signal output switch tube M2 and a high-voltage signal control module; The high-voltage signal control module includes the first high-voltage source, the second high-voltage source, the first low-voltage source, the second low-voltage source, an input end, a first output end, and a second output end. The input end of the high-voltage signal control module is connected to the low-voltage output signal, the first output end of the high-voltage signal control module is connected to the control end of the first high-voltage signal output switch tube M1, and the second output end of the high-voltage signal control module is connected to the control end of the second high-voltage signal output switch tube M2; The current input terminal of the first high-voltage signal output switch tube M1 is connected to the high voltage PH, and the current output terminal is connected to the current input terminal of the second high-voltage signal output switch tube M2; the current output terminal of the second high-voltage signal output switch tube M2 is grounded; The high voltage signal control module is used to control the on and off of the first high voltage signal output switch tube M1 and the second high voltage signal output switch tube M2 according to the high voltage PH, the second low voltage PL2, the first low voltage PL1 and the low voltage output signal.

2. The combinational logic circuit according to claim 1, wherein: The voltages of the first low voltage input signal SL1 and the second low voltage input signal SL2 are both not higher than the voltage of the first low voltage PL1 , and are both not lower than the ground voltage.

3. The combinational logic circuit according to claim 1, wherein: The high-voltage signal control module includes a first logic unit, a second logic unit, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7 and an eighth switch tube M8; In the high-voltage signal control module, the high voltage PH is grounded sequentially through the third switch tube M3, the fourth switch tube M4, and the fifth switch tube M5, and the control end of the fifth switch tube M5 is connected to the first logic unit; the high voltage PH is also grounded sequentially through the sixth switch tube M6, the seventh switch tube M7, and the eighth switch tube M8, and the control end of the eighth switch tube M8 is connected to the second logic unit; the control ends of the fourth switch tube M4 and the seventh switch tube M7 are both connected to the second low voltage PL2; The input end of the first logic unit serves as the input end of the high-voltage signal control module, and the output end of the first logic unit is connected to the input end of the second logic unit.

4. The combinational logic circuit according to claim 3, wherein: The high voltage signal control module further includes an RS trigger B1, a first inverter F1, a second inverter F2 and a third inverter F3; The input end of the first inverter F1 is connected to the first node E1 between the third switch tube M3 and the fourth switch tube M4, and the output end is connected to the set end of the RS trigger B1; The input end of the second inverter F2 is connected to the second node E2 between the sixth switch tube M6 and the seventh switch tube M7, and the output end is connected to the reset end of the RS trigger B1; The input end of the third inverter F3 is connected to the inverting output end of the RS trigger B1, and the output end serves as the first output end of the high-voltage signal control module; The high reference terminals of the RS trigger B1 , the first inverter F1 , the second inverter F2 and the third inverter F3 are all connected to the high voltage PH, and the low reference terminals are all connected to the second low voltage PL2 .

5. The combinational logic circuit according to claim 4, wherein: The high-voltage signal control module further includes a ninth switch tube M9, a tenth switch tube M10, a fourth inverter F4 and a fifth inverter F5; The input end of the fourth inverter F4 is connected to the output end of the second inverter F2, and the output end of the fourth inverter F4 is connected to the control end of the ninth switch tube M9; the current input end of the ninth switch tube M9 is connected to the first node E1, and the current output end is connected to the control end of the fourth switch tube M4. The control end of the ninth switch tube M9 is also connected to the control end of the third switch tube M3; The input end of the fifth inverter F5 is connected to the output end of the first inverter F1, and the output end of the fifth inverter F5 is connected to the control end of the tenth switch tube M10; the current input end of the tenth switch tube M10 is connected to the second node E2, and the current output end is connected to the control end of the seventh switch tube M7. The control end of the tenth switch tube M10 is also connected to the control end of the sixth switch tube M6; The high reference terminals of the fourth inverter F4 and the fifth inverter F5 are both connected to the high voltage PH, and the low reference terminals are both connected to the second low voltage PL2.

6. The combinational logic circuit according to claim 5, wherein: The first logic unit includes a sixth inverter F6 and a seventh inverter F7, and the second logic unit includes an eighth inverter F8; The input end of the sixth inverter F6 serves as the input end of the high-voltage signal control module, and the output end is connected to the input end of the eighth inverter F8 through the seventh inverter F7; the output end of the eighth inverter F8 serves as the second output end of the high-voltage signal control module; the output end of the seventh inverter F7 is connected to the control end of the fifth switch tube M5, and the output end of the eighth inverter F8 is also connected to the control end of the eighth switch tube M8; The high reference terminals of the sixth inverter F6 , the seventh inverter F7 and the eighth inverter F8 are all connected to the first low voltage PL1 , and the low reference terminals are all grounded.

7. The combinational logic circuit according to any one of claims 1 to 6, characterized in that: The low-voltage output signal generating circuit includes a first resistor R1, a second resistor R2, an eleventh switch tube M11, a twelfth switch tube M12, a comparator A1, a first controllable current source G1, a second controllable current source G2 and a third controllable current source G3; In the low-voltage output signal generating circuit, the first low voltage PL1 is grounded in sequence through the first resistor R1, the eleventh switch tube M11, the twelfth switch tube M12, and the second resistor R2; the first low voltage PL1 is also grounded in sequence through the second controllable current source G2 and the third controllable current source G3; The positive control terminals of the first controllable current source G1 and the second controllable current source G2 are both connected to the first low voltage PL1, and the negative control terminals are both connected to the current input terminal of the eleventh switch tube M11; the current input terminal of the first controllable current source G1 is connected to the first low voltage PL1, and the current output terminal is connected to the positive control terminal of the third controllable current source G3; the positive control terminal of the third controllable current source G3 is also connected to the current output terminal of the twelfth switch tube M12, and the negative control terminal of the third controllable current source G3 is grounded; A third node E3 between the eleventh switch transistor M11 and the twelfth switch transistor M12 is connected to the first low-voltage input signal SL1; The comparator A1 has a positive input terminal connected to the first comparison voltage V1 , a negative input terminal connected to the first low-voltage input signal SL1 , and an output terminal connected to the control terminals of the eleventh switch tube M11 and the twelfth switch tube M12 .

8. The combinational logic circuit according to claim 7, wherein: The low-voltage output signal generating circuit further includes a third resistor R3, a fourth controllable current source G4, a fifth controllable current source G5, a sixth controllable current source G6 and a seventh controllable current source G7; The first end of the third resistor R3 is connected to the first low voltage PL1, and the current input end and the positive control end of the fifth controllable current source G5, the sixth controllable current source G6 and the seventh controllable current source G7 are all connected to the first low voltage PL1; the negative control ends of the fifth controllable current source G5, the sixth controllable current source G6 and the seventh controllable current source G7 are all connected to the second end of the third resistor R3, and are commonly connected to the current input end of the fourth controllable current source G4; the current output end and the negative control end of the fourth controllable current source G4 are both grounded, and the positive control end of the fourth controllable current source G4 is connected to the positive control end of the third controllable current source G3.

9. The combinational logic circuit according to claim 8, wherein: The low-voltage output signal generating circuit further includes a thirteenth switch tube M13, a fourteenth switch tube M14, a first capacitor C1, a ninth inverter F9 and a tenth inverter F10; The current input terminal of the thirteenth switch tube M13 is connected to the current output terminal of the fifth controllable current source G5, the current output terminal of the thirteenth switch tube M13 is grounded through the fourteenth switch tube M14, and the control terminal is connected to the second low-voltage input signal SL2; the control terminal of the fourteenth switch tube M14 is connected to the control terminal of the thirteenth switch tube M13; A first end of the first capacitor C1 is connected to the current input end of the fourteenth switch tube M14, and a second end thereof is grounded; The input end of the ninth inverter F9 is connected to the current input end of the fourteenth switch tube M14, and the output end thereof outputs the first low-voltage output signal SLO1; An input terminal of the tenth inverter F10 is connected to an output terminal of the ninth inverter F9 , and an output terminal of the tenth inverter F10 outputs a second low-voltage output signal SLO2 .

10. The combinational logic circuit according to claim 9, wherein: The low-voltage output signal generating circuit further includes an eleventh inverter F11, a twelfth inverter F12, a fifteenth switch tube M15, a sixteenth switch tube M16, a second capacitor C2, a first OR gate O1, a first AND gate N1 and a first NAND gate NF1; The current input terminal of the fifteenth switch tube M15 is connected to the current output terminal of the sixth controllable current source G6, the current output terminal of the fifteenth switch tube M15 is grounded through the sixteenth switch tube M16, and the control terminal of the fifteenth switch tube M15 is connected to the control terminal of the sixteenth switch tube M16; The input end of the eleventh inverter F11 is connected to the second low-voltage input signal SL2, and the output end is connected to the control end of the fifteenth switch tube M15; A first end of the second capacitor C2 is connected to the current input end of the sixteenth switch tube M16, and a second end is grounded; The input end of the twelfth inverter F12 is connected to the current input end of the sixteenth switch tube M16, and the output end is connected to the first input end of the first OR gate O1; the second input end of the first OR gate O1 is connected to the first input end of the first NAND gate NF1, and both are connected to the current output end of the second controllable current source G2; the second input end of the first NAND gate NF1 is connected to the first input end of the first OR gate O1; A first input of the first AND gate N1 is connected to the output of the first OR gate O1 , a second input of the first AND gate N1 is connected to the output of the first NAND gate NF1 , and the output of the first AND gate N1 outputs a third low-voltage output signal SLO3 .

11. The combinational logic circuit according to claim 10, wherein: The low-voltage output signal generating circuit further includes a thirteenth inverter F13, a fourteenth inverter F14, a seventeenth switch tube M17, an eighteenth switch tube M18, a third capacitor C3, a second OR gate O2, a second AND gate N2 and a second NAND gate NF2; A current input terminal of the seventeenth switch tube M17 is connected to a current output terminal of the seventh controllable current source G7, a current output terminal of the seventeenth switch tube M17 is grounded via the eighteenth switch tube M18, a control terminal of the seventeenth switch tube M17 is connected to a control terminal of the eighteenth switch tube M18, and both are connected to an output terminal of the eleventh inverter F11; A first end of the third capacitor C3 is connected to the current input end of the eighteenth switch tube M18, and a second end thereof is grounded; The input end of the thirteenth inverter F13 is connected to the current input end of the eighteenth switch tube M18, and the output end is connected to the first input end of the second OR gate O2; The input end of the fourteenth inverter F14 is connected to the current output end of the second controllable current source G2, and the output end is connected to the first input end of the second NAND gate NF2; The first input terminal of the second OR gate O2 is further connected to the second input terminal of the second NAND gate NF2; the first input terminal of the second NAND gate NF2 is further connected to the second input terminal of the second OR gate O2; A first input of the second AND gate N2 is connected to the output of the second OR gate O2 , a second input of the second AND gate N2 is connected to the output of the second NAND gate NF2 , and an output of the second AND gate N2 outputs a fourth low-voltage output signal SLO4 .

12. The combinational logic circuit according to claim 11, wherein: The current coefficient of the third controllable current source G3 is less than 1, and the current coefficients of the first controllable current source G1, the second controllable current source G2, the fourth controllable current source G4, the fifth controllable current source G5, the sixth controllable current source G6 and the seventh controllable current source G7 are equal to 1.

13. The combinational logic circuit according to claim 12, wherein: The first low-voltage input signal SL1 includes a first sub-signal SL11 and a second sub-signal SL12 . The voltage of the first sub-signal SL11 is lower than the first comparison voltage V1 , and the voltage of the second sub-signal SL12 is higher than the first comparison voltage V1 .

14. The combinational logic circuit according to claim 1, wherein: In the power supply circuit, the high voltage PH is grounded sequentially through the nineteenth switch tube M19 and the fourth resistor R4; the high voltage PH is also grounded sequentially through the fifth resistor R5 and the first voltage stabilizing diode D1; the high voltage PH is also grounded sequentially through the second voltage stabilizing diode D2 and the sixth resistor R6; the high voltage PH is also grounded sequentially through the seventh resistor R7 and the twentieth switch tube M20; The control end of the nineteenth switch tube M19 is connected between the fifth resistor R5 and the first voltage zener diode D1; the control end of the twentieth switch tube M20 is connected between the second voltage zener diode D2 and the sixth resistor R6; the current output end voltage of the nineteenth switch tube M19 is the first low voltage PL1, and the current input end voltage of the twentieth switch tube M20 is the second low voltage PL2.

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