High-gain folding cascode structure fully differential operational amplifier
By adopting a high-gain folding casubar structure fully differential operational amplifier in the multi-stage amplifier circuit, the gain bootstrap structure of the self-casubar cogate transistor is used to solve the trade-off between gain and bandwidth of the traditional multi-stage amplifier circuit, and achieving higher gain and stability.
Patent Information
- Application Number
- CN202510312210.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2025-07-01
AI Technical Summary
While improving the gain, traditional multi-stage amplifier circuits are difficult to maintain sufficient bandwidth and stability, especially when the load capacitance is large.
A high-gain folding cascorder structure fully differential operational amplifier is adopted. Through the gain bootstrap structure of the self-cascorder cogate transistor, the output impedance is improved to achieve higher gain.
Without introducing additional power consumption, the gain and bandwidth of the amplifier are improved, meeting the requirements of stability and high frequency response.
Smart Images
Figure CN120238065A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and particularly to a high-gain folded cascode structure fully differential operational amplifier. Background Art
[0002] An amplifier circuit is one of the most commonly used circuits in electronic technology. To improve the amplification effect, multistage amplification is usually used. A two-stage amplifier circuit is a commonly used multistage amplifier circuit. A commonly used two-stage amplifier circuit is a two-stage Miller compensation amplifier circuit, which includes a first-stage amplifier circuit and a second-stage amplifier circuit. By reasonably designing the compensation capacitor, the oscillation problem caused by the superposition of high-frequency poles in the multistage amplifier circuit can be avoided. However, the reduction of the main pole frequency will sacrifice part of the bandwidth, and a compromise needs to be made between high gain and wide bandwidth. If the secondary pole frequency is too low (such as a large load capacitance), it may still not meet the stability requirements even after compensation.
[0003] Through the gain bootstrap technique, the auxiliary amplifier dynamically adjusts the gate voltage of the transistors in the main amplifier, so that the output impedance is increased to A times that of the conventional structure (A is the gain of the auxiliary amplifier), thereby greatly improving the DC gain. The gain bootstrap technique only adjusts the low-frequency impedance through the auxiliary amplifier, has little influence on the frequency response of the main amplifier, the main pole is still determined by the load capacitance and the output impedance, and the position of the secondary pole is far away, resulting in less bandwidth loss. The traditional gain bootstrap stage structure selection is usually folded-cascode, as Figure 4 shown, Figure 1 is the auxiliary amplifier A, Figure 2 is the auxiliary amplifier circuit B. The amplifier circuit adopting this circuit structure can ensure that each device works in the saturation region.
[0004] The self-cascode composite transistor structure, as Figure 5 shown, can be regarded as a composite transistor, which has a larger effective channel length (therefore lower output conductance).
[0005] Therefore, applying the self-cascode composite transistor to the gain bootstrap structure can effectively improve the DC gain of the operational amplifier. Summary of the Invention
[0006] The object of the present invention is to provide a high-gain folded cascode structure fully differential operational amplifier, which can improve the output impedance to achieve higher gain without introducing additional power consumption.
[0007] The technical solution of the present invention is: an auxiliary operational amplifier A, an auxiliary operational amplifier B, a plurality of P-type MOS transistors and a plurality of N-type MOS transistors 2; the plurality of P-type MOS transistors are respectively denoted as PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, PMOS transistor P7, PMOS transistor P8, PMOS transistor P9; the plurality of N-type MOS transistors are respectively denoted as NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6.
[0008] The voltage source VDD is connected to the source of PMOS transistor P1; the gate of the PMOS transistor P1 is connected to the bias voltage Vb1, and the sources of the PMOS transistor P2 and the PMOS transistor P3 are connected to the drain of the PMOS transistor; the drain of the PMOS transistor P2 is connected to the source of the NMOS transistor N2 and the drain of the NMOS transistor N4; the drain of the PMOS transistor P3 is connected to the source of the NMOS transistor N1 and the drain of the NMOS transistor N3; the drain of the NMOS transistor N5 is connected to the source of the NMOS transistor N3, and the source of the NMOS transistor N5 is grounded; the drain of the NMOS transistor N6 is connected to the source of the NMOS transistor N2, and the source of the NMOS transistor N6 is grounded; the gates of the NMOS transistors N3, N4, N5, and N6 are connected and connected to the bias voltage Vb3. The voltage source VDD is connected to the sources of the PMOS transistors P4 and P5; the gates of the PMOS transistors P4, P5, P6, and P7 are connected and connected to the bias voltage Vb2; the drain of the PMOS transistor P4 is connected to the source of the PMOS transistor P6; the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P7; the source of the PMOS transistor P8 is connected to the drain of the PMOS transistor P6; the source of the PMOS transistor P9 is connected to the drain of the PMOS transistor 7.
[0009] The drain of the PMOS transistor P8 is connected to the drain of the NMOS transistor N1 as the non-inverting output terminal Voutp of the operational amplifier, and the drain of the PMOS transistor P9 is connected to the drain of the NMOS transistor N2 as the inverting output terminal Voutn of the operational amplifier; the positive input terminal of the auxiliary amplifier A is connected to the drain of the PMOS transistor P6 and the source of the PMOS transistor P8, and the negative input terminal of the auxiliary amplifier A is connected to the drain of the PMOS transistor P7 and the source of the PMOS transistor P9; the positive input terminal of the auxiliary amplifier B is connected to the drain of the NMOS transistor N3 and the source of the NMOS transistor N1, and the negative input terminal of the auxiliary amplifier B is connected to the drain of the NMOS transistor N6 and the source of the NMOS transistor N4; the positive output terminal of the auxiliary amplifier A is connected to the gate of the PMOS transistor P9, the negative output terminal of the auxiliary amplifier A is connected to the gate of the PMOS transistor P8, the positive output terminal of the auxiliary amplifier B is connected to the gate of the NMOS transistor N2, and the negative output terminal of the auxiliary amplifier B is connected to the gate of the NMOS transistor N1.
[0010] The sources of the PMOS transistors P10 and P11 are connected to the power supply VDD, and the gates of the PMOS transistors P10 and P11 are connected together and connected to the bias voltage BP1; the drains of the PMOS transistor P10 and the NMOS transistor N8 are connected together and connected to the source of the PMOS transistor P12; the drains of the PMOS transistor P11 and the NMOS transistor N7 are connected together and connected to the source of the PMOS transistor P13; the gates of the PMOS transistors P12 and P13 are connected together and connected to the bias voltage BP2; the drain of the NMOS transistor N12 is connected to the drain of the PMOS transistor P12 as the positive output terminal of the auxiliary amplifier A; the drain of the NMOS transistor N13 is connected to the drain of the PMOS transistor P13 as the negative output terminal of the auxiliary amplifier A; the gates of the NMOS transistors N12 and N13 are connected together and connected to the bias voltage BN1; the drain of the NMOS transistor N14 is connected to the source of the NMOS transistor N12; the drain of the NMOS transistor N15 is connected to the source of the NMOS transistor N13; the gates of the NMOS transistors N14 and N15 are connected together and connected to the bias voltages BN2, and the sources are connected to the ground; the drain of the NMOS transistor N16 is connected to the power supply VDD, and the gate is connected to the bias voltage VCMN; the sources of the NMOS transistors N16, N7, and N8 are connected together and connected to the drain of the NMOS transistor N10; the source of the NMOS transistor N10 is connected to the drain of the NMOS transistor N11, and the gate of the NMOS transistor N10 is connected to the bias voltage BN1; the source of the NMOS transistor N11 is connected to the ground, and the gate of the NMOS transistor N11 is connected to the bias voltage BN2; the gate of the NMOS transistor N7 serves as the positive input terminal of the auxiliary amplifier A, and the gate of the NMOS transistor N8 serves as the negative input terminal of the auxiliary amplifier A.
[0011] The sources of the PMOS transistors P19 and P20 are connected to the power supply VDD, and the gates of the PMOS transistors P19 and P20 are connected together and connected to the bias voltage BP1; the gates of the PMOS transistors P21 and P22 are connected together and connected to the bias voltage BP2; the drain of the NMOS transistor N17 is connected to the drain of the PMOS transistor P21 as the positive output terminal of the auxiliary amplifier A; the drain of the NMOS transistor N18 is connected to the drain of the PMOS transistor P22 as the negative output terminal of the auxiliary amplifier A; the gates of the NMOS transistors N17 and N18 are connected together and connected to the bias voltage BN1; the drains of the NMOS transistor N19 and the PMOS transistor P18 are connected to the source of the NMOS transistor N17; the drains of the NMOS transistor N20 and the PMOS transistor P17 are connected to the source of the NMOS transistor N18; the gates of the NMOS transistors N19 and N20 are connected together and connected to the bias voltage BN2, and the sources are connected to the ground; the source of the PMOS transistor P14 is connected to the power supply VDD, the gate of the PMOS transistor P14 is connected to the bias voltage BP1, and the drain of the PMOS transistor P14 is connected to the source of the PMOS transistor P15; the PMOS transistor P15 is connected to the sources of the PMOS transistors P16, P17, and P18; the gate of the PMOS transistor P16 is connected to the bias voltage VCMP, and the drain of the PMOS transistor P16 is connected to the ground.
[0012] The auxiliary amplifier A adopts a folded cascode structure, as Figure 2 shown, which can provide a large DC gain, and its value is;
[0013] A VA = g mn8 (g mp12 r op12 (r op10 / / r on8 ) / / g mn12 r on12 r on14 )
[0014] The auxiliary amplifier B adopts a folded cascode structure, as Figure 3 shown, which can provide a large DC gain, and its value is;
[0015] A VB = g mp18 (g mp21 r op21 r op19 / / g mn17 r on17 (r on19 / / r on18 ))
[0016] The PMOS transistors P4, P6 and the PMOS transistors P5, P7 form a self-cascode structure, and the NMOS transistors N3, N5 and the NMOS transistors N4, N6 form a self-cascode structure. This transistor structure can be regarded as a composite transistor, which has a larger effective channel length and thus a lower output conductance.
[0017] The gain-boosting structure of the self-cascode transistor is as Figure 6 shown. Compared with the traditional gain improvement technology, it can provide a larger output impedance, and its output impedance is: A V g mn3 r on3 (r on1 g m2 r on2 ).
[0018] Since the PMOS transistors P4, P5 and the NMOS transistors N5, N6 are always operating in the linear region, while the PMOS transistors P6, P7 and the NMOS transistors N3, N4 are operating in the saturation or linear region. The voltage between the source and drain of the PMOS transistors P4, P5 and the NMOS transistors N5, N6 is very small, so that there is no obvious VDSAT difference between the composite transistor and the simple transistor. Therefore, the self-cascode structure can be used for low-voltage applications.
[0019] The described high-gain folded cascode structure fully differential operational amplifier has a large DC gain, and its value is:
[0020] Gain=g mp2 [A VA g mp8 r op8 (r op6 g mp6 r op4 ) / / A VB g mn1 r on1 ((r on3 g mn3 r on5 ) / / r ap3 )]
[0021] The present invention provides a high-gain folded cascode structure fully differential operational amplifier, which uses the gain-boosting structure of the self-cascode transistor and can increase the output impedance without introducing additional power consumption to achieve higher gain. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The present invention will be further described below in conjunction with the drawings and embodiments:
[0023] Figure 1 is the circuit diagram of the high-gain folded cascode structure fully differential operational amplifier of the present invention.
[0024] Figure 2 This is the circuit diagram of the auxiliary amplifier A in the first embodiment of the present invention.
[0025] Figure 3 This is the circuit diagram of the auxiliary amplifier B in the first embodiment of the present invention.
[0026] Figure 4 This is the circuit diagram of a traditional gain-boosted folded cascode fully differential operational amplifier.
[0027] Figure 5 This is the circuit diagram of a self-cascode transistor structure.
[0028] Figure 6 This is the circuit diagram of a gain-boosted structure using self-cascode transistors. Figure 7 This is a schematic diagram comparing the gains of the high-gain folded cascode structure and the traditional structure operational amplifier of the present invention. Detailed implementation manners
[0029]
Embodiment 1
[0030] The circuit of the embodiment is as Figure 2 , the voltage source VDD is connected to the source of the PMOS transistor P1; the gate of the PMOS transistor P1 is connected to the bias voltage Vb1, and the sources of the PMOS transistors P2 and P3 are connected to the drain of the PMOS transistor; the drain of the PMOS transistor P2 is connected to the source of the NMOS transistor N2 and the drain of the NMOS transistor N4; the drain of the PMOS transistor P3 is connected to the source of the NMOS transistor N1 and the drain of the NMOS transistor N3; the drain of the NMOS transistor N5 is connected to the source of the NMOS transistor N3, and the source of the NMOS transistor N5 is grounded; the drain of the NMOS transistor N6 is connected to the source of the NMOS transistor N2, and the source of the NMOS transistor N6 is grounded; the gates of the NMOS transistors N3, N4, N5, and N6 are connected and connected to the bias voltage Vb3.
[0031] The voltage source VDD is connected to the sources of the PMOS transistors P4 and P5; the gates of the PMOS transistors P4, P5, P6, and P7 are connected and connected to the bias voltage Vb2; the drain of the PMOS transistor P4 is connected to the source of the PMOS transistor P6; the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P7; the source of the PMOS transistor P8 is connected to the drain of the PMOS transistor P6; the source of the PMOS transistor P9 is connected to the drain of the PMOS transistor 7.
[0032] The drain of the PMOS transistor P8 is connected to the drain of the NMOS transistor N1 as the non-inverting output terminal Voutp of the operational amplifier. The drain of the PMOS transistor P9 is connected to the drain of the NMOS transistor N2 as the inverting output terminal Voutn of the operational amplifier. The positive input terminal of the auxiliary amplifier A is connected to the drain of the PMOS transistor P6 and the source of the PMOS transistor P8. The negative input terminal of the auxiliary amplifier A is connected to the drain of the PMOS transistor P7 and the source of the PMOS transistor P9. The positive input terminal of the auxiliary amplifier B is connected to the drain of the NMOS transistor N3 and the source of the NMOS transistor N1. The negative input terminal of the auxiliary amplifier B is connected to the drain of the NMOS transistor N6 and the source of the NMOS transistor N4. The positive output terminal of the auxiliary amplifier A is connected to the gate of the PMOS transistor P9. The negative output terminal of the auxiliary amplifier A is connected to the gate of the PMOS transistor P8. The positive output terminal of the auxiliary amplifier B is connected to the gate of the NMOS transistor N2. The negative output terminal of the auxiliary amplifier B is connected to the gate of the NMOS transistor N1.
[0033] The sources of the PMOS transistors P10 and P11 are connected to the power supply VDD. The gates of the PMOS transistors P10 and P11 are connected together and connected to the bias voltage BP1. The drains of the PMOS transistor P10 and the NMOS transistor N8 are connected together and connected to the source of the PMOS transistor P12. The drains of the PMOS transistor P11 and the NMOS transistor N7 are connected together and connected to the source of the PMOS transistor P13. The gates of the PMOS transistors P12 and P13 are connected together and connected to the bias voltage BP2. The drain of the NMOS transistor N12 is connected to the drain of the PMOS transistor P12 as the positive output terminal of the auxiliary amplifier A. The drain of the NMOS transistor N13 is connected to the drain of the PMOS transistor P13 as the negative output terminal of the auxiliary amplifier A. The gates of the NMOS transistors N12 and N13 are connected together and connected to the bias voltage BN1. The drain of the NMOS transistor N14 is connected to the source of the NMOS transistor N12. The drain of the NMOS transistor N15 is connected to the source of the NMOS transistor N13. The gates of the NMOS transistors N14 and N15 are connected together and connected to the bias voltages BN2, and their sources are connected to the ground. The drain of the NMOS transistor N16 is connected to the power supply VDD, and its gate is connected to the bias voltage VCMN. The sources of the NMOS transistors N16, N7, and N8 are connected together and connected to the drain of the NMOS transistor N10. The source of the NMOS transistor N10 is connected to the drain of the NMOS transistor N11. The gate of the NMOS transistor N10 is connected to the bias voltage BN1. The source of the NMOS transistor N11 is connected to the ground, and its gate is connected to the bias voltage BN2. The gate of the NMOS transistor N7 serves as the positive input terminal of the auxiliary amplifier A, and the gate of the NMOS transistor N8 serves as the negative input terminal of the auxiliary amplifier A.
[0034] The sources of the PMOS transistors P19 and P20 are connected to the power supply VDD, and the gates of the PMOS transistors P19 and P20 are connected together and connected to the bias voltage BP1; the gates of the PMOS transistors P21 and P22 are connected together and connected to the bias voltage BP2; the drain of the NMOS transistor N17 is connected to the drain of the PMOS transistor P21 as the positive output terminal of the auxiliary amplifier A; the drain of the NMOS transistor N18 is connected to the drain of the PMOS transistor P22 as the negative output terminal of the auxiliary amplifier A; the gates of the NMOS transistors N17 and N18 are connected together and connected to the bias voltage BN1; the drains of the NMOS transistor N19 and the PMOS transistor P18 are connected to the source of the NMOS transistor N17; the drains of the NMOS transistor N20 and the PMOS transistor P17 are connected to the source of the NMOS transistor N18; the gates of the NMOS transistors N19 and N20 are connected together and connected to the bias voltage BN2, and the sources are connected to the ground; the source of the PMOS transistor P14 is connected to the power supply VDD, the gate of the PMOS transistor P14 is connected to the bias voltage BP1, and the drain of the PMOS transistor P14 is connected to the source of the PMOS transistor P15; the PMOS transistor P15 is connected to the sources of the PMOS transistors P16, P17, and P18; the gate of the PMOS transistor P16 is connected to the bias voltage VCMP, and the drain of the PMOS transistor P16 is connected to the ground.
[0035] The auxiliary amplifier respectively adopts NMOS and PMOS transistor differential input pairs. Figure 2 and Figure 3 are their circuit structures respectively. When designing the auxiliary amplifier, the pole-zero pair coupling phenomenon must be noted. If the pole-zero pair appears within the -3dB bandwidth of the closed-loop system, the settling time of the system will become longer. In the gain bootstrap structure, the pole-zero pair appears near the unity-gain frequency of the auxiliary op-amp. Increasing the occurrence frequency of the pole-zero pair can avoid its influence on the settling time, but if it is increased to near the secondary point of the main op-amp, the op-amp will become unstable. Therefore, the design of the auxiliary op-amp must satisfy
[0036] βω u ≤ω a ≤ω p.2
[0037] β is the closed-loop feedback coefficient; ω u is the unity-gain bandwidth of the main amplifier; ω a is the unity-gain bandwidth of the auxiliary amplifier; ω p.2 is the l-th non-dominant pole of the main amplifier. When designing, first assume β = 1, so that the condition can also be satisfied for lower β values. The position of the first non-dominant pole of the main op-amp is not easy to determine. It can be selected that the unity-gain frequency of the auxiliary op-amp is greater than the unity-gain frequency of the main op-amp, and then see whether adjustment or compensation capacitors are needed according to the simulation results.
[0038] The PMOS transistors P4, P6 and the PMOS transistors P5, P7 form a self-cascode structure, and the NMOS transistors N3, N5 and the NMOS transistors N4, N6 form a self-cascode structure. This transistor structure can be regarded as a composite transistor, which has a larger effective channel length and thus a lower output conductance. Taking the self-cascode structure formed by the PMOS transistors P4, P6 as an example, if the lengths of P4 and P6 are equal and P6 is m times wider than P4, the equivalent W / L ratio is:
[0039] The gain of this operational amplifier is Gain = g mp2 [A VA g mp8 r op8 (r op6 g mp6 r op4 ) / / A VB g mn1 r on1 ((r on3 g mn3 r on5 ) / / r op3 )].
Claims
1. A high-gain folded cascode fully differential operational amplifier, characterized in that: PMOS tube P1, PMOS tube P2, PMOS tube P3, PMOS tube P4, PMOS tube P5, PMOS tube P6, PMOS tube P7, PMOS tube P8, PMOS tube P9; multiple N-type MOS tubes are respectively recorded as NMOS tube N1, NMOS tube N2, NMOS tube N3, NMOS tube N4, NMOS tube N5, NMOS tube N6. A voltage source VDD is connected to the source of the PMOS tube P1; the gate of the PMOS tube P1 is connected to the bias voltage Vb1, and the sources of the PMOS tubes P2 and P3 are connected to the drain of the PMOS tube; the drain of the PMOS tube P2 is connected to the source of the NMOS tube N2 and the drain of the NMOS tube N4; the drain of the PMOS tube P3 is connected to the source of the NMOS tube N1 and the drain of the NMOS tube N3; the drain of the NMOS tube N5 is connected to the source of the NMOS tube N3, and the source of the NMOS tube N5 is grounded; the drain of the NMOS tube N6 is connected to the source of the NMOS tube N2, and the source of the NMOS tube N6 is grounded; the gates of the NMOS tubes N3, NMOS tubes N4, NMOS tubes N5, and NMOS tubes N6 are connected and connected to the bias voltage Vb3. The voltage source VDD is connected to the sources of the PMOS tubes P4 and P5; the gates of the PMOS tubes P4, P5, P6 and P7 are connected and connected to the bias voltage Vb2; the drain of the PMOS tube P4 is connected to the source of the PMOS tube P6; the drain of the PMOS tube P5 is connected to the source of the PMOS tube P7; the source of the PMOS tube P8 is connected to the drain of the PMOS tube P6; the source of the PMOS tube P9 is connected to the drain of the PMOS tube 7. The drain of the PMOS tube P8 is connected to the drain of the NMOS tube N1 as the positive phase output terminal Voutp of the operational amplifier, and the drain of the PMOS tube P9 is connected to the drain of the NMOS tube N2 as the negative phase output terminal Voutn of the operational amplifier; the positive input terminal of the auxiliary amplifier A is connected to the drain of the PMOS tube P6 and the source of the PMOS tube P8, and the negative input terminal of the auxiliary amplifier A is connected to the drain of the PMOS tube P7 and the source of the PMOS tube P9; the positive input terminal of the auxiliary amplifier B is connected to the drain of the NMOS tube N3 and the source of the NMOS tube N1, and the negative input terminal of the auxiliary amplifier B is connected to the drain of the NMOS tube N6 and the source of the NMOS tube N4; the positive output terminal of the auxiliary amplifier A is connected to the gate of the PMOS tube P9, the negative output terminal of the auxiliary amplifier A is connected to the gate of the PMOS tube P8, the positive output terminal of the auxiliary amplifier B is connected to the gate of the NMOS tube N2, and the negative output terminal of the auxiliary amplifier B is connected to the gate of the NMOS tube N1.
2. The high-gain folded cascode fully differential operational amplifier according to claim 1, characterized in that: The gain of the gain bootstrap op amp satisfies: Gain=g mp2 [A VA g mp8 r op8 (r op6 g mp6 r op4 ) / / A VB g mn1 r on1 (r on3 g mn3 r ron5 )] Wherein, Gain represents the gain of the high-gain folded cascode fully differential operational amplifier, A VA represents the gain of the auxiliary amplifier A, A VB represents the gain of the auxiliary amplifier B, g mp2 Indicates the transconductance of PMOS tube P2, g mp8 represents the transconductance of PMOS tube P8, r op8 represents the output impedance of PMOS tube P8, r op6 Indicates the output impedance of PMOS tube P6, g mp6 represents the transconductance of PMOS tube P6, r op4 Indicates the output impedance of PMOS tube P4, g mn1 represents the transconductance of NMOS tube N1, r on1 Represents the output impedance of NMOS tube N1, r on3 Indicates the output impedance of NMOS tube N3, g mn3 The transconductance of NMOS tube N3 is shown in Figure 2. on5 Represents the output impedance of NMOS tube N5.
3. The high-gain folded cascode fully differential operational amplifier according to claim 1, characterized in that: The auxiliary operational amplifier A includes PMOS tube P10, PMOS tube P11, PMOS tube P12, and PMOS tube P13; multiple N-type MOS tubes are respectively recorded as NMOS tube N7, NMOS tube N8, NMOS tube N9, NMOS tube N10, NMOS tube N11, NMOS tube N12, NMOS tube N13, NMOS tube N14, NMOS tube N15, and NMOS tube N16. The sources of the PMOS tubes P10 and P11 are connected to the power supply VDD, and the gates of the PMOS tubes P10 and P11 are connected and connected to the bias voltage BP1; the drains of the PMOS tubes P10 and NMOS tubes N8 are connected and connected to the source of the PMOS tube P12; the drains of the PMOS tubes P11 and NMOS tubes N7 are connected and connected to the source of the PMOS tube P13; the gates of the PMOS tubes P12 and PMOS tubes P13 are connected and connected to the bias voltage BP2; the drain of the NMOS tube N12 is connected to the drain of the PMOS tube P12 as the positive output terminal of the auxiliary amplifier A; the drain of the NMOS tube N13 is connected to the drain of the PMOS tube P13 as the negative output terminal of the auxiliary amplifier A; the gates of the NMOS tubes N12 and NMOS tubes N13 are connected and connected to the bias voltage BN1; The drain of N14 is connected to the source of NMOS tube N12; the drain of NMOS tube N15 is connected to the source of NMOS tube N13; the gates of NMOS tubes N14 and N15 are connected and connected to bias voltage BN2, and the sources are connected to ground; the drain of NMOS tube N16 is connected to power supply VDD, and the gate is connected to bias voltage VCMN; the sources of NMOS tubes N16, N7, and N8 are connected and connected to the drain of NMOS tube N10; the source of NMOS tube N10 is connected to the drain of NMOS tube N11, and the gate of NMOS tube N10 is connected to bias voltage BN1; the source of NMOS tube N11 is connected to ground, and the gate of NMOS tube N11 is connected to bias voltage BN2; the gate of NMOS tube N7 serves as the positive input terminal of the auxiliary amplifier A, and the gate of NMOS tube N8 serves as the negative input terminal of the auxiliary amplifier A.
4. The high-gain folded cascode fully differential operational amplifier according to claim 1, characterized in that: The auxiliary operational amplifier B includes PMOS tube P14, PMOS tube P15, PMOS tube P16, PMOS tube P17, PMOS tube P18, PMOS tube P19, PMOS tube P20, PMOS tube P21, and PMOS tube P22; multiple N-type MOS tubes are respectively recorded as NMOS tube N17, NMOS tube N18, NMOS tube N19, and NMOS tube N20. The sources of the PMOS tubes P19 and P20 are connected to the power supply VDD, the gates of the PMOS tubes P19 and P20 are connected and connected to the bias voltage BP1; the gates of the PMOS tubes P21 and P22 are connected and connected to the bias voltage BP2; the drain of the NMOS tube N17 is connected to the drain of the PMOS tube P21 as the positive output end of the auxiliary amplifier A; the drain of the NMOS tube N18 is connected to the drain of the PMOS tube P22 as the negative output end of the auxiliary amplifier A; the gates of the NMOS tubes N17 and NMOS tubes N18 are connected and connected to the bias voltage BN1; the NMOS tubes N19 and PMOS tubes P18 are connected. The drain of the NMOS tube N17 is connected to the source of the NMOS tube N17; the drains of the NMOS tube N20 and the PMOS tube P17 are connected to the source of the NMOS tube N18; the gates of the NMOS tubes N19 and N20 are connected and connected to the bias voltage BN2, and the sources are connected to the ground; the source of the PMOS tube P14 is connected to the power supply VDD, the gate of the PMOS tube P14 is connected to the bias voltage BP1, and the drain of the PMOS tube P14 is connected to the source of the PMOS tube P15; the PMOS tube P15 is connected to the sources of the PMOS tubes P16, P17, and P18; the gate of the PMOS tube P16 is connected to the bias voltage VCMP, and the drain of the PMOS tube P16 is connected to the ground.