False wakeup fault processing method and device and medium

Abstract

The invention discloses a false wake-up fault processing method, a false wake-up fault processing device and a medium, relates to the technical field of electronic circuits, and is used for solving the false wake-up problem existing in a multi-path wake-up circuit. Aiming at the problem of false wake-up existing in a multi-path wake-up circuit based on monostable trigger design, the invention provides a false wake-up fault processing method which comprises the following steps: judging whether the problem of false wake-up exists or not by capturing a voltage waveform at a chip wake-up end. If so; if yes, voltage waveforms of all circuit nodes in the multiple wake-up circuits are captured, so that abnormal electrical elements causing the false wake-up problem are positioned; moreover, based on the difference between the abnormal voltage waveform and the corresponding normal voltage waveform, the parameter range which the abnormal electrical element should reach can be determined. Therefore, abnormal electrical elements are adjusted, the problem of false wake-up existing in a multi-path wake-up circuit realized based on monostable triggering at present is solved, and the stability and the safety of the circuit are improved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a method, device and medium for handling false wakeup faults. Background Art

[0002] A monostable trigger circuit is a circuit that uses resistors and capacitors to make the trigger signal valid for a certain period of time. Based on the monostable trigger circuit, a circuit with adjustable action time can be realized, so that different signals can be processed in time-sharing mode, thereby obtaining a multi-way wake-up circuit that allows multiple wake-up sources to share one wake-up channel. Compared with the original multi-way wake-up circuit that requires the use of multiple different wake-up channels, it has more advantages, so it has been used as a combination switch in many scenarios such as vehicles.

[0003] However, in the actual project implementation, the technicians found that due to improper operation or mechanical structure deviation, the combination switch slider would slide to the middle of the two gears. At this time, the combination switch would be turned on in both directions at the same time (the slider went from grounded to suspended), which would lead to the problem of false wake-up.

[0004] Therefore, technicians in this field are in urgent need of a false awakening fault processing method to solve the false awakening problem existing in the current multi-channel awakening circuit implemented based on monostable triggering. Summary of the invention

[0005] The purpose of the present application is to provide a false wake-up fault processing method, device and medium to solve the false wake-up problem existing in the multi-way wake-up circuit currently implemented based on monostable trigger.

[0006] In order to solve the above technical problems, the present application provides a method for handling false wakeup faults, including:

[0007] Obtaining a first voltage waveform at the chip wake-up end through an oscilloscope, and determining whether there is a false wake-up problem according to the first voltage waveform;

[0008] If it exists, the second voltage waveform at each circuit node in the multi-way wake-up circuit is obtained through an oscilloscope, and the abnormal electrical component is located according to the second voltage waveform;

[0009] Determine a target parameter range of the abnormal electrical component according to the first voltage waveform and / or the second voltage waveform; wherein the target parameter range is a parameter value range of the abnormal electrical component when the false wake-up problem does not occur;

[0010] Abnormal electrical components are adjusted according to the target parameter range.

[0011] In a possible embodiment, obtaining a second voltage waveform at each circuit node in the multi-way wake-up circuit through an oscilloscope, and locating an abnormal electrical component according to the second voltage waveform includes:

[0012] Obtain the voltage waveforms at the bases of the NPN transistor and the PNP transistor in the multi-channel wake-up circuit;

[0013] If the voltage waveform at the base of the NPN transistor is abnormal and the voltage waveform at the base of the PNP transistor is normal, obtain the voltage waveform at the midpoint of the resistor-capacitor combination connected to the base of the NPN transistor;

[0014] If it is determined according to the voltage waveform at the midpoint that the time constant of the resistor-capacitor combination is too large, determine that one or a group of electrical components that affect the time constant in the resistor-capacitor combination are abnormal electrical components.

[0015] In a possible embodiment, the resistor-capacitor combination includes: a first combined resistor, a second combined resistor, a third combined resistor, a first combined capacitor, a second combined capacitor, and a third combined capacitor;

[0016] Wherein, the first end of the first combined resistor is connected to the base of the NPN transistor, and the second end of the first combined resistor is connected to the collector of the PNP transistor;

[0017] The first end of the second combined resistor is connected to the base of the NPN transistor, and the second end of the second combined resistor is grounded; the first end of the first combined capacitor is connected to the base of the NPN transistor, and the second end of the first combined capacitor is grounded; the second combined capacitor and the third combined capacitor are in parallel;

[0018] The first end of the third combined resistor is connected to the base of the NPN transistor, and the second end of the third combined resistor is connected to one parallel end of the second combined capacitor and the third combined capacitor;

[0019] The abnormal electrical components are: the second combined capacitor and the third combined capacitor, or, the first combined resistor.

[0020] In a possible embodiment, determining the target parameter range of the abnormal electrical component according to the first voltage waveform and / or the second voltage waveform includes:

[0021] Obtain the ideal charging parameter of the base voltage of the NPN transistor when the multi-channel wake-up circuit does not have a false wake-up phenomenon;

[0022] According to the ideal charging parameter, determine the target parameter range of the abnormal electrical component through the charging formula of the resistor-capacitor combination.

[0023] In a possible embodiment, determining the target parameter range of the abnormal electrical component according to the first voltage waveform and / or the second voltage waveform includes:

[0024] Perform parameter scanning on abnormal electrical components, and monitor the first voltage waveform and / or the second voltage waveform to determine whether the false wake-up problem disappears;

[0025] Determine the parameter value range of the abnormal electrical component when the false wake-up problem disappears, and use it as the target parameter range.

[0026] In a possible embodiment, determining the target parameter range of the abnormal electrical component according to the first voltage waveform and / or the second voltage waveform includes:

[0027] Use the current parameter value of the abnormal electrical component as the starting value, and perform the first parameter scanning according to the preset first step size;

[0028] Use the parameter upper limit value determined during the first parameter scanning as the target upper limit value, and use the parameter lower limit value determined during the first parameter scanning as the intermediate result value;

[0029] Use the intermediate result value as the starting value, and perform the second parameter scanning according to the preset second step size; where the second step size is smaller than the first step size;

[0030] Use the parameter lower limit value determined during the second parameter scanning as the target lower limit value;

[0031] Determine the target parameter range according to the target upper limit value and the target lower limit value.

[0032] In a possible embodiment, obtaining the first voltage waveform at the chip wake-up terminal through an oscilloscope, and determining whether there is a false wake-up problem according to the first voltage waveform includes:

[0033] Obtain multiple first voltage waveforms at the chip wake-up terminal at different times;

[0034] If, among all the first voltage waveforms, the proportion of the first voltage waveforms determined to be abnormal reaches a preset ratio, it is determined that there is a false wake-up problem.

[0035] To solve the above technical problems, the present application also provides a false wake-up fault processing device, including:

[0036] A problem analysis module, configured to obtain the first voltage waveform at the chip wake-up terminal through an oscilloscope, and determine whether there is a false wake-up problem according to the first voltage waveform. If so, trigger the abnormal location module;

[0037] An abnormal location module, configured to obtain the second voltage waveforms at each circuit node in the multi-channel wake-up circuit through an oscilloscope, and locate the abnormal electrical component according to the second voltage waveforms;

[0038] A parameter determination module, configured to determine a target parameter range of an abnormal electrical component according to a first voltage waveform and / or a second voltage waveform; wherein, the target parameter range is the parameter value range of the abnormal electrical component when no false wake-up problem occurs.

[0039] A circuit adjustment module, configured to adjust the abnormal electrical component according to the target parameter range.

[0040] To solve the above technical problems, the present application further provides a false wake-up fault processing device, including:

[0041] A memory, configured to store a computer program;

[0042] A processor, configured to implement the steps of the false wake-up fault processing method as described above when executing the computer program.

[0043] To solve the above technical problems, the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the false wake-up fault processing method as described above are implemented.

[0044] The false wake-up fault processing method provided by the present application captures the voltage waveform at the wake-up terminal of the chip to determine whether the voltage waveform for waking up the chip is abnormal, thereby determining whether there is a false wake-up problem currently. If so, the method further captures the voltage waveforms of each circuit node in the multi-path wake-up circuit to locate the abnormal electrical component that causes the false wake-up problem. And based on the difference between the abnormal voltage waveform and the corresponding normal voltage waveform, the parameter range that the abnormal electrical component should reach can be determined, that is, the target parameter range. Finally, the abnormal electrical component is adjusted according to the corresponding target parameter range, and the multi-path wake-up circuit that will not have a false wake-up problem is obtained by re-designing or adjusting the existing circuit, so as to solve the false wake-up problem existing in the multi-path wake-up circuit based on monostable triggering, and improve stability and security.

[0045] The false wake-up fault processing device and the computer-readable storage medium provided by the present application correspond to the above method, and the effects are the same. Description of the Drawings

[0046] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0047] Figure 1 It is a structural diagram of a multi-path wake-up circuit under normal working conditions;

[0048] Figure 2 Flow chart of a method for handling false wake-up faults provided by an embodiment of the present invention;

[0049] Figure 3 Schematic diagram of the output voltage waveform when the multi-channel wake-up circuit is switched on under normal operating conditions;

[0050] Figure 4 Schematic diagram of the output voltage waveform when the multi-channel wake-up circuit is switched off under normal operating conditions;

[0051] Figure 5 Schematic diagram of the output voltage waveform when the multi-channel wake-up circuit has a false wake-up problem;

[0052] Figure 6 Schematic diagram of the equivalent circuit when two channels of the multi-channel wake-up circuit are conducting simultaneously;

[0053] Figure 7 Schematic diagram of the output voltage waveform during the first capacitance parameter scan when the switch is conducting, provided by an embodiment of the present invention;

[0054] Figure 8 Schematic diagram of the output voltage waveform during the first capacitance parameter scan when the switch is off, provided by an embodiment of the present invention;

[0055] Figure 9 Schematic diagram of the output voltage waveform of the first resistance parameter scan provided by an embodiment of the present invention;

[0056] Figure 10 Schematic diagram of the output voltage waveform during the second capacitance parameter scan when the switch is conducting, provided by an embodiment of the present invention;

[0057] Figure 11 Schematic diagram of the output voltage waveform during the second capacitance parameter scan when the switch is off, provided by an embodiment of the present invention;

[0058] Figure 12 Schematic diagram of the output voltage waveform of the second resistance parameter scan provided by an embodiment of the present invention;

[0059] Figure 13 Structural diagram of a false wake-up fault handling device provided by the present invention;

[0060] Figure 14 Structural diagram of another false wake-up fault handling device provided by the present invention. Detailed implementation manners

[0061] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0062] The core of the present application is to provide a method, device and medium for handling false wake-up faults.

[0063] To enable those skilled in the art to better understand the solutions of the present application, the following further detailed description of the present application will be made in conjunction with the accompanying drawings and specific embodiments.

[0064] For devices that need to be used for a long time, the sleep mode is an important solution to ensure their power consumption and effective working duration. However, for a device in the sleep mode, it needs to be woken up when necessary, generally through a specific wake-up circuit. Among them, when there are multiple wake-up sources, that is, a multi-channel wake-up circuit is required to wake up the device.

[0065] Traditional multi-channel wake-up circuits generally require a separate wake-up channel to be set for each wake-up source, and the circuit structure is complex and difficult to implement. At present, those skilled in the art have proposed a multi-channel wake-up circuit based on monostable triggering. A typical circuit structure thereof is as Figure 1 shown, which can achieve the effect that multiple wake-up sources can share the same channel to wake up the device to be woken up.

[0066] However, in the actual application process of the above new multi-channel wake-up circuit, it is found that there is a problem of false wake-up in this multi-channel wake-up circuit. Specifically, when at least two of the multi-way switches are simultaneously turned on due to improper operation or mechanical structure deviation in the actual project, a false wake-up problem will occur. And based on methods such as repeated testing and expanding the sample size, it is determined that this false wake-up is not an accidental problem, but a common problem of this multi-channel wake-up circuit, which affects the wake-up effect of the device in the actual project.

[0067] To solve the above problems, the present application provides a method for handling false wake-up faults, as Figure 2 shown, including:

[0068] S11: Obtain the first voltage waveform at the wake-up terminal of the chip through an oscilloscope, and determine whether there is a false wake-up problem according to the first voltage waveform; if so, go to step S12.

[0069] S12: Obtain the second voltage waveforms at each circuit node in the multi-channel wake-up circuit through an oscilloscope, and locate the abnormal electrical components according to the second voltage waveforms.

[0070] S13: Determine the target parameter range of the abnormal electrical component according to the first voltage waveform and / or the second voltage waveform.

[0071] Wherein, the target parameter range is the parameter value range of the abnormal electrical component when no false wake-up problem occurs.

[0072] S14: Adjust the abnormal electrical component according to the target parameter range.

[0073] Before discussing how to determine whether there is a false wake-up problem through the voltage waveform, this embodiment first briefly describes the basic working principle of the multi-channel wake-up circuit:

[0074] As Figure 1 shown, when the switch S2 is turned on and off, rising and falling edges are generated at the output point e through the monostable trigger circuit, thereby generating a waveform for triggering wake-up. Among them, the monostable trigger circuit has two working states: steady state and transient state:

[0075] Steady state: When the switch does not switch, the output always remains at the 12V pulled-high state.

[0076] Transient state: When the switch switches, the output will be pulled low to 0V, but only for a short period of time.

[0077] Under the action of an external trigger pulse, through the resistor-capacitor (RC) combination in the circuit, charge and discharge can transfer from the steady state to the transient state. After maintaining the transient state for a period of time, it will automatically return to the steady state as the charge and discharge process is completed.

[0078] Furthermore, in combination with the voltage waveform (i.e., the first voltage waveform) diagram output by the multi-channel wake-up circuit in different states, analyze the reasons for the false wake-up problem of the multi-channel wake-up circuit.

[0079] 1. Voltage waveform output in an ideal scenario (i.e., when there is no false wake-up problem);

[0080] Among them, the switch SW1 is used to simulate two different states of point a grounded and floating, and point d is the circuit output for outputting the wake-up signal.

[0081] When the switch SW1 is turned on (point a changes from floating to grounded), point a is instantaneously pulled low; at this time, the capacitor C2 discharges, the voltage at point c drops, and the PNP transistor Q2 conducts; at the same time, the capacitor C3 discharges, the voltage at point b instantaneously drops, and because the PNP transistor Q2 conducts, the voltage at point b rises rapidly, causing the NPN transistor Q1 to conduct, and point d is pulled low from the original 12V to 0; afterwards, as the discharges of the capacitors C2 and C3 end, the voltage at point c gradually rises to 12V and returns to the steady state, and both the PNP transistor Q2 and the NPN transistor Q1 are turned off, and the voltage at point d rises back to 12V.

[0082] At this time, the voltage waveform output by the multi-channel wake-up circuit is as Figure 3 shown. Figure 3 In Figure 3 , the duration of the EF segment is approximately 849 μs. Considering the voltage fluctuations, an anti-shake time is added and set to 100 μs. If it is greater than this time, the wake-up will be triggered.

[0083] When the switch SW1 is turned off (from grounded to floating), point a is instantly pulled high, charging the capacitor C2, and the voltage at point c rises. At this time, the PNP transistor Q2 is turned off; at the same time, point a being pulled high also charges the capacitor C3, and the voltage at point b rises instantaneously; restricted by the turn-off of the PNP transistor Q2, the voltage at point b drops rapidly, and the drop amplitude will be greater than that of point c; therefore, the NPN transistor Q1 will turn on first and then turn off as the voltage at point b drops; the voltage at point d drops from 12 V to 0, and as the system enters the steady state, the voltage at point d returns to 12 V.

[0084] At this time, the voltage waveform output by the multi-channel wake-up circuit is as Figure 4 shown. Figure 4 In Figure 4 , the time of the EF segment is approximately 721 μs, which is greater than 100 μs, meeting the condition for triggering wake-up.

[0085] 2. Voltage waveform output in case of false wake-up;

[0086] As can be seen from the above description, in an actual project (such as when the multi-channel wake-up circuit is applied to the combination switch of a certain vehicle), due to improper operation or mechanical structure deviation, the slider may slide to the middle of two gears. At this time, when the two paths of the multi-way switch are simultaneously turned on (the slider changes from grounded to floating), the original circuit will be falsely awakened. Capture the voltage waveform at the wake-up terminal (pin) of the chip with an oscilloscope. As Figure 5 shown, it is found that there is indeed an extra spike compared to normal wake-up, and the duration and voltage of each spike are greater than the trigger wake-up threshold of this chip (voltage threshold: 3 V, duration threshold: 100 μs), so false wake-up is triggered.

[0087] Moreover, based on multiple repeated tests with multiple sample parts replaced, it is found that the above problem is not an accidental phenomenon, but a common problem existing in the multi-channel wake-up circuit implemented based on the monostable trigger circuit. Therefore, it is inferred that this problem may be caused by a defect in the circuit topology.

[0088] The above analysis is equivalent to analyzing whether there is a false wake-up problem in the multi-channel wake-up circuit by capturing the voltage waveform at the wake-up terminal of the chip (which is also equivalent to the voltage waveform output by the multi-channel wake-up circuit, Figure 1 the voltage waveform at point d in Figure 1 ) in step S11.

[0089] Based on this, this embodiment also provides a possible implementation. Specifically, step S11 is as follows:

[0090] S111: Obtain multiple first voltage waveforms at the chip wake-up terminal at different times respectively.

[0091] S112: If the proportion of the first voltage waveforms determined to be abnormal among all the first voltage waveforms reaches a preset ratio, it is determined that there is a problem of false wake-up.

[0092] That is, when determining whether there is a problem of false wake-up in the circuit in step S11 of this embodiment, it is not to determine whether the circuit has or has not had a problem of false wake-up through one-time waveform capture and analysis, but to repeatedly capture the first voltage waveforms output by the circuit at different times to exclude the errors caused by accidental reasons, so that when determining whether there is a problem of false wake-up in the circuit in step S11, a more accurate result can be obtained.

[0093] Furthermore, this method locates the cause of the abnormality based on step S12. By using an oscilloscope to capture the voltage waveforms at each circuit node (including but not limited to the above-mentioned points a to d) in the multi-channel wake-up circuit and comparing them with the voltage waveforms at each circuit node under normal operation, it can be determined which section of the circuit specifically causes the problem of false wake-up, realizing the location of abnormal electrical components. It should be particularly noted that capturing all the circuit nodes in the multi-channel wake-up circuit can effectively ensure the implementation of step S12. However, if it can be determined in advance based on experience or circuit principle analysis which key nodes in the multi-channel wake-up circuit may cause the problem of false wake-up, then in step S12, only the voltage waveforms of these key nodes in the multi-channel wake-up circuit can be captured and analyzed to bring higher efficiency, and this embodiment does not limit this.

[0094] Moreover, the voltage waveform reflects various parameters of the voltage signal at each circuit node. Combining with the analysis of the circuit principle of the multi-channel wake-up circuit, it can be analyzed which parameters of the abnormal electrical component cause the problem of false wake-up. And then in step S13, the target parameter range that can avoid the problem of false wake-up is determined through various methods such as calculation analysis or test experiments.

[0095] It is not difficult to understand that the method of obtaining the target parameter range based on calculation analysis can start from the working principle of the multi-channel wake-up circuit, judge the relationship between the voltage waveform output by the circuit and the parameters of the abnormal electrical component, and thus inversely deduce the target parameter range of the abnormal electrical component based on the ideal voltage waveform output under normal operation. In addition, for the method of determining the target parameter range through test experiments, it is to repeatedly change the parameters of the abnormal electrical component multiple times and monitor the situation of the first voltage waveform to judge whether the problem of false wake-up disappears. If it disappears, the parameter values of the abnormal electrical component at this time can be included in the target parameter range. Through repeated tests multiple times, a set of parameter values or even a parameter range that can solve the problem of false wake-up can be obtained, so as to determine the target parameter range of the abnormal electrical component.

[0096] Finally, based on the target parameter range obtained in step S13, step S14 adjusts the abnormal electrical components in the original multi-channel wake-up circuit to achieve the redesign of the circuit. After the redesign, the multi-channel wake-up circuit can solve the problem of false wake-up caused by the simultaneous conduction of two paths.

[0097] In summary, a method for processing false wake-up faults provided by the present application, during the use of a multi-channel wake-up circuit implemented based on a monostable trigger, determines whether a false wake-up problem occurs by capturing the voltage waveform at the wake-up terminal of the chip. After a false wake-up problem occurs, by capturing the voltage waveforms of each circuit node in the multi-channel wake-up circuit and based on the comparison with the normal voltage waveforms, the possible circuit positions where abnormalities may occur can be located, and then the abnormal electrical components can be located. Subsequently, based on the analysis of the abnormal voltage waveforms, the parameter range of the abnormal electrical components when the false wake-up problem is solved can be obtained as the target parameter range for the final circuit adjustment. Based on the multi-channel wake-up circuit analyzed and optimized by this method, the solution to the false wake-up problem can be effectively ensured, thereby improving the stability and reliability of the circuit.

[0098] On the other hand, the above embodiments give several possible solutions for step S12 to locate abnormal electrical components, and this embodiment also gives a specific implementation solution for the specific implementation of step S12. Step S12 specifically includes:

[0099] S121: Obtain the voltage waveforms at the bases of the NPN transistors and the bases of the PNP transistors in the multi-channel wake-up circuit.

[0100] S122: If the voltage waveform at the base of the NPN transistor is abnormal and the voltage waveform at the base of the PNP transistor is normal, obtain the voltage waveform at the midpoint of the resistor-capacitor combination connected to the base of the NPN transistor.

[0101] S123: If it is determined according to the voltage waveform at the midpoint that the time constant of the resistor-capacitor combination is too large, determine that one or a group of electrical components in the resistor-capacitor combination that affect the time constant are abnormal electrical components.

[0102] Before elaborating on the solution provided by this embodiment in detail, first analyze why the multi-channel wake-up circuit has a voltage waveform that causes false wake-up (such as Figure 5 the shown voltage waveform):

[0103] First, clarify the differences between the simultaneous conduction of two paths and normal operation: The simultaneous conduction of two paths is equivalent to adding an additional parallel capacitance, that is, Figure 1 the shown multi-channel wake-up circuit becomes as Figure 6 shown, Figure 1 where one path C2 in Figure 6 becomes C3 in parallel with C5 inFigure 1 One of the C3s in Figure 6 becomes one of the C4s and C6s in

[0104] At this time, the capacitor-resistor combination (RC circuit) connected to the circuit changes from the original one path to two paths in parallel connection. The time constant of the RC circuit becomes larger, and the system response time becomes longer, resulting in the appearance of a second peak.

[0105] At the same time, by using an oscilloscope to simultaneously capture the voltage waveform at the base (point c) of the NPN transistor Q1 (i.e., the above-mentioned second voltage waveform) and the voltage waveform received at the chip wake-up pin (i.e., the above-mentioned first voltage waveform). It is found that when a false wake-up occurs, the voltage at point c is pulled down, lower than the base-emitter (b-e) threshold voltage of 0.7V of the NPN transistor Q1, which is consistent with the speculation. At the same time, the voltage waveform at the base (point d) of the PNP transistor Q2 (which also belongs to the second voltage waveform) is captured. It is found that when the slider is suspended, the voltage at point d decreases and the PNP transistor Q2 conducts, which meets the expectation. Therefore, the analysis of the false wake-up fault points to the voltage condition at the base (point c) of the NPN transistor Q1.

[0106] At the same time, since it is determined through the capture of the voltage waveform that the voltage at point c is abnormal and the voltage at point d is normal, based on this, it can be preliminarily determined that there is a problem in the circuit section from the resistor-capacitor combination (C4, C6, R6) in the lower path to the NPN transistor Q1. Therefore, the voltage waveform at point f is measured through an oscilloscope, and compared with the voltage waveform at point f under normal operation, it is found that the voltage first suddenly changes from 0 to more than -4V, and then discharges exponentially in the reverse direction to 0V. It can be seen that at this time, the voltage change rate of the circuit is slower than that under normal operation and the voltage drop amplitude is larger, which is in line with the analysis of the fault phenomenon. It is indeed the resistor-capacitor combination in the lower path (i.e., the resistor-capacitor combination C4, C6, R6, C2, R5, R3 connected to the base of the NPN transistor Q1) that causes the false wake-up due to the longer system response time when the two paths are conducting simultaneously.

[0106] In summary, it can be concluded that the simultaneous conduction of the two paths makes the equivalent capacitance of the resistor-capacitor combination in the connected circuit become larger. The increase in the equivalent capacitance leads to an increase in its time constant, and further slows down the overall system response time. As Figure 5 shown, when the first voltage waveform output by the circuit is in the FG section, C3 and C5 discharge, the voltage at point d decreases, the PNP transistor Q2 conducts, and the voltage at point c is pulled up; at the same time, correspondingly, C4 and C6 discharge, the voltage at point c decreases, which restricts the above-mentioned increase in voltage caused by the conduction of the PNP transistor Q2; due to the larger RC time constant of C4 and C6, more charges accumulate at point c and discharge slowly; so in the HI section, the voltage at point c decreases due to the capacitor discharge, the NPN transistor Q1 turns off, and the voltage at point e is pulled up, resulting in a false wake-up.

[0107] Therefore, the direction for improvement is to reduce the RC time constant. However, if the RC time constant is too small and the charge is too little, C4 and C6 cannot be fully discharged, and the voltage at point c cannot be pulled down, resulting in the inability of the subsequent NPN transistor Q1 to conduct and the failure to wake up.

[0108] That is, in this embodiment, based on the principle analysis of the multi-channel wake-up circuit, several key circuit nodes in the circuit can be determined (point c at the base of the NPN transistor Q1, point d at the base of the PNP transistor Q2, and point f at the middle of the resistor-capacitor combination connected to the base of the NPN transistor Q1). By capturing and analyzing the voltage waveforms at these key circuit nodes, the position of the abnormal electrical component can be quickly and accurately located, and the reason for the mis-wake-up problem can be analyzed as follows: the simultaneous conduction of two paths causes the capacitance to increase, and then the RC time constant increases. Based on this, the adjustment direction for improving the mis-wake-up problem can also be obtained: reducing the RC time constant. This also provides a theoretical basis and reference for determining the target parameter range of the abnormal electrical component, and can greatly improve the efficiency and accuracy of this method in dealing with mis-wake-up faults.

[0109] Furthermore, only one abnormal circuit segment that may cause the mis-wake-up problem in the multi-channel wake-up circuit is given in the above embodiment, but no specific restrictions are imposed on the specific abnormal electrical components, which can be one or some of the electrical components in the abnormal circuit segment. In response to this, this embodiment provides a specific implementation scheme:

[0110] As Figure 6 shown, the resistor-capacitor combination corresponding to the base of the NPN transistor Q1 (i.e., belonging to the abnormal circuit segment determined in the previous embodiment) includes: the first combined resistor R3, the second combined resistor R5, the third combined resistor R6, the first combined capacitor C2, the second combined capacitor C4, and the third combined capacitor C6.

[0111] Among them, the first end of the first combined resistor R3 is connected to the base of the NPN transistor Q1, and the second end of the first combined resistor R3 is connected to the collector of the PNP transistor Q2.

[0112] The first end of the second combined resistor R5 is connected to the base of the NPN transistor Q1, and the second end of the second combined resistor R5 is grounded; the first end of the first combined capacitor C2 is connected to the base of the NPN transistor Q1, and the second end of the first combined capacitor C2 is grounded; the second combined capacitor C4 and the third combined capacitor C5 are connected in parallel.

[0113] The first end of the third combined resistor R6 is connected to the base of the NPN transistor Q1, and the second end of the third combined resistor R6 is connected to one of the parallel ends of the second combined capacitor C4 and the third combined capacitor C6.

[0114] Then, in the above resistor-capacitor combination, the abnormal electrical components are: the second combined capacitor C4 and the third combined capacitor C6, or the first combined resistor R3.

[0115] As can be seen from the above description, this embodiment provides a positioning scheme for abnormal electrical components. Based on the capture of the voltage waveforms at key circuit nodes (the base c point of the NPN transistor, the base of the PNP transistor, and the midpoint of the resistor-capacitor combination connected to the base of the NPN transistor), the possible positions of the abnormal electrical components that cause the false wake-up problem in the circuit can be located in the resistor-capacitor combination in the lower path of the circuit, that is, the resistor-capacitor combination corresponding to the base of the NPN transistor. Furthermore, there are mainly two groups of electrical components in this resistor-capacitor combination that can affect the overall time constant: 1. The second combined capacitor and the third combined capacitor; 2. The first combined resistor; that is, two groups of possible abnormal electrical components are determined. By adjusting the parameters of the above two groups of possible abnormal electrical components, the false wake-up problem can be solved, thereby improving the safety and reliability of the circuit.

[0116] On the other hand, after determining the abnormal electrical components, how to determine the target parameter range of the abnormal electrical components is not limited in the above embodiment, but two possible implementation directions are provided: 1. Perform parameter calculation based on circuit principles; 2. Observe whether the false wake-up phenomenon disappears based on parameter scanning.

[0117] Based on these two possible implementation directions, this application provides corresponding specific implementation schemes respectively. First, for the above direction 1, this embodiment provides a specific implementation scheme for step S13. Step S13 specifically includes:

[0118] S131-A: Obtain the ideal charging parameters of the voltage at the base of the NPN transistor when the multi-channel wake-up circuit does not exhibit false wake-up phenomena.

[0119] S132-A: Determine the target parameter range of the abnormal electrical components according to the ideal charging parameters through the charging formula of the resistor-capacitor combination.

[0120] Based on the two groups of possible abnormal electrical component combinations determined in the above embodiment, combined with Figure 6 the circuit and a possible example (that is, the specific electrical parameters involved in the following description are only one possible example), this embodiment will be described respectively:

[0121] 1. The abnormal electrical components are the second combined capacitor C4 and the third combined capacitor C6;

[0122] In one possible example, the capacitance values of C4 and C6 are 10 nF. Based on the theoretical analysis of the above embodiment, one of the keys to improving the false wake-up problem is to reduce the time constant of the resistor-capacitor combination. For C4 and C6, it is necessary to reduce their capacitance values.

[0123] Specifically, based on the charging formula of the resistor-capacitor combination: Vc = V * (1 - e^(-t / R * C)); where Vc is the voltage at point c; V is the power supply voltage; t is the time; R is the equivalent resistance value after the parallel connection of R3 and R5; C is the capacitance value of C4 and C6.

[0124] Among them, under ideal wake-up conditions, the voltage at point c should be charged from 470 mV to 700 mV, and the charging time is about 158 us. Substituting these three parameters into the formula for calculation, it is obtained that the maximum capacitance value C is 8.7 nF. Less than the theoretically calculated value obtained by this calculation, theoretically, it can meet the need to avoid false wake-up problems.

[0125] However, in the actual application process, there are other requirements for the capacitance values of C4 and C6 (for example, if the capacitance values of C4 and C6 are too small, C4 and C6 cannot be fully discharged, and the voltage at point c cannot be pulled down, resulting in the non-conduction of the subsequent NPN transistor and the inability to achieve the wake-up function). Therefore, considering the needs of these parts comprehensively, the target parameter range of the abnormal electrical components C4 and C6 can be finally determined. It should be noted that this embodiment focuses on introducing the target parameter range required to solve the false wake-up problem, and it can be achieved as long as it is less than the theoretically calculated value of 8.7 nF obtained above. For other requirements for the capacitance values of C4 and C6, they can be calculated with reference to the requirements for the parameters of electrical components in the current circuit design, and this embodiment does not limit this.

[0126] 2. The abnormal electrical component is the first combined resistor R3;

[0127] In a possible example, the resistance value of R3 is 100 KΩ. Based on the theoretical analysis of the above embodiment, one of the keys to improving the false wake-up problem is to reduce the time constant of the resistor-capacitor combination. For R3, it is necessary to reduce its resistance value.

[0128] The idea is still to use the resistor-capacitor combination to filter out the spikes, then according to the charging formula of the resistor-capacitor combination: Vc = V * (1 - e^(-t / R * C)). Among them, under ideal wake-up conditions, the voltage at the left end of R3 should be charged from 11.693 V to 11.706 V, and the charging time is about 158 us. Substituting these three parameters into the formula for calculation, it is obtained that the maximum equivalent resistance value R is 48.7 KΩ. Since this equivalent resistance value R is the equivalent resistance value after the parallel connection of resistor R3 and resistor R5, and according to the resistance value of R5 being 100 KΩ, it is calculated that the maximum resistance value of R3 is 92 KΩ. It can be seen that the adjustment direction of resistor R3 is consistent with the expectation. By reducing the resistance value to below the theoretically calculated value of 92 KΩ, the false wake-up fault can be eliminated.

[0129] Similarly, for the minimum value of the resistance R3, it should be determined according to other design requirements of the actual circuit. This embodiment only focuses on introducing the parameter adjustment part for eliminating the false wake-up fault, and does not impose any restrictions on other parameter requirements. For example, R3 also has the function of absorbing the leakage current of the PNP triode. Since the PNP triode will inevitably generate leakage current when it is turned off, if the resistance value of R3 is too small, a large voltage drop will be generated after R3 absorbs the leakage current, causing the base c point voltage of the NPN triode to be higher than the threshold voltage, and the NPN triode will be mis-conducted. Therefore, the resistance of R3 cannot be too small. Under the condition of ensuring no false wake-up, R3 should be selected as large as possible. For example, when the theoretically calculated value is 92 KΩ, for the convenience of implementation, a 90 KΩ resistor can be selected as R3.

[0130] As can be seen from the above, an implementation scheme provided by this embodiment can obtain the target parameter range of the abnormal electrical component by means of theoretical calculation based on the circuit principle, and can more efficiently realize the adjustment of the abnormal electrical component. And during the determination process of the target parameter range, strict theoretical derivation is carried out to obtain theoretical support, which can exclude the wrong results caused by occasional factors.

[0131] On the other hand, for the implementation direction of obtaining the target parameter range based on parameter scanning described above, this embodiment also provides a specific implementation scheme. The above step S13 is specifically:

[0132] S131-B: Perform parameter scanning on the abnormal electrical component, and monitor the first voltage waveform and / or the second voltage waveform to determine whether the false wake-up problem disappears.

[0133] S132-B: Determine the parameter value range of the abnormal electrical component when the false wake-up problem disappears as the target parameter range.

[0134] Still taking the two groups of possible abnormal electrical component combinations determined in the above embodiment, combined with Figure 6 the circuit and a possible example (that is, the specific electrical parameters involved in the following description are only a possible example), this embodiment will be described separately:

[0135] 1. The abnormal electrical components are the second combined capacitor C4 and the third combined capacitor C6;

[0136] Based on the adjustment direction of improving the false wake-up problem in the above embodiment, which is to reduce the resistance-capacitance combination time constant, when the abnormal electrical components are C4 and C6, the adjustment direction should be to reduce the capacitance values of C4 and C6, that is, the parameter scanning direction is to reduce the parameter values.

[0137] Assume that the current capacitance values of C4 and C6 are 10 nF and the scanning step is 1 nF. Scanning in the direction of reducing the parameter values, we can obtain as Figure 7 andFigure 8 The first voltage waveform shown (i.e., the voltage waveform output by the multi-channel wake-up circuit).

[0138] Among them, as Figure 7 shown, when the switch is turned on (changing from floating to grounded), there are false wake-up problems with 9nF and 10nF, while 1nF - 8nF has no sharp corners and will not cause false wake-up. And the wake-up time in these cases is about 4ms, meeting the wake-up condition that the duration is greater than 100us. Therefore, the target parameter range of C4 and C6 can be initially determined as 1nF - 8nF, and it can also meet the requirement of being less than the theoretical calculated value of 8.7nF obtained above.

[0139] As Figure 8 shown, when the switch is turned off (changing from grounded to floating), as C4 and C6 increase, the voltage waveform has no sharp corners, and the wake-up time gradually increases from 900us to more than 6ms, meeting the wake-up condition.

[0140] 2. The abnormal electrical component is the first combined resistor R3;

[0141] Based on the adjustment direction for improving the false wake-up problem in the above embodiments, which is to reduce the resistance-capacitance combination time constant, when the abnormal electrical component is R3, the adjustment direction should be to reduce the resistance value of R3, that is, the direction of parameter scanning is to reduce the parameter value.

[0142] Assume that the current resistance value of R3 is 100KΩ and the scanning step size is 10KΩ. Scanning in the direction of reducing the parameter value, the Figure 9 first voltage waveform shown (i.e., the voltage waveform output by the multi-channel wake-up circuit) can be obtained.

[0143] Among them, as Figure 9 shown, when the resistance value of R3 is 10K - 90K, the false wake-up fault is eliminated. That is, the target parameter range of the resistor R3 can be determined as 10K - 90K, and this target parameter range also meets the condition of being less than the theoretical calculated value of 92KΩ.

[0144] As can be seen from the above, the solution for determining the target parameter range based on parameter scanning provided in this embodiment can be supported by the actual (simulation) situation, ensuring that the obtained target parameter range can accurately solve the false wake-up problem in the current scenario. At the same time, compared with the theoretical calculation solution, the parameter scanning solution can determine a finite parameter range including the upper limit and the lower limit, reducing the implementation difficulty of adjusting the abnormal electrical component.

[0145] It should be particularly noted that the above two schemes of theoretical calculation and parameter scanning can be implemented separately, but can also be combined. For example, before performing parameter scanning, first obtain the scanning direction and the preliminary target parameter range based on theoretical calculation, and then further determine through parameter scanning, so that the finally determined target parameter range can be supported by both theory and the actual environment, maximizing the reliability of the method to solve the problem of false wake-up.

[0146] Furthermore, for the above parameter scanning scheme, this embodiment also provides a further implementation scheme. Specifically, step S13 further includes:

[0147] S131-C: Use the current parameter value of the abnormal electrical component as the starting value, and perform the first parameter scanning according to the preset first step size.

[0148] S132-C: Take the parameter upper limit value determined during the first parameter scanning as the target upper limit value, and take the parameter lower limit value determined during the first parameter scanning as the intermediate result value.

[0149] S133-C: Use the intermediate result value as the starting value, and perform the second parameter scanning according to the preset second step size.

[0150] Among them, the second step size is smaller than the first step size.

[0151] S134-C: Take the parameter lower limit value determined during the second parameter scanning as the target lower limit value.

[0152] S135-C: Determine the target parameter range according to the target upper limit value and the target lower limit value.

[0153] The above embodiment of the parameter scanning of the capacitors C4 and C6 and the resistor R3 is also used to illustrate the solution of this embodiment:

[0154] 1. The abnormal electrical components are C4 and C6;

[0155] Assume that the current capacitance values of C4 and C6 are 10 nF and the scanning step size is 1 nF, and scan in the direction of decreasing parameter values. The first voltage waveform (i.e., the voltage waveform output by the multi-channel wake-up circuit) as shown in Figure 7 and Figure 8 can be obtained. And the preliminary target parameter range of 1 nF - 8 nF is determined.

[0156] The above process corresponds to the first parameter scanning in this embodiment, and the intermediate result value in step S132-C is 1 nF.

[0157] Further, taking the intermediate result value of 1 nF as the initial value of the second parameter scan, with a scan step of 0.1 nF which is less than 1 nF, and scanning in the direction of decreasing the parameter value, the first voltage waveform as shown in Figure 10 and Figure 11 can be obtained. As can be seen from Figure 10 , when the switch is turned on (from floating to grounded), the wake-up time for 0.1 nF - 1 nF is 4 ms, all meeting the wake-up condition. As can be seen from Figure 11 , when the switch is turned off (from grounded to floating), the capacitors of 0.8 nF - 1 nF all meet the wake-up requirements.

[0158] The above process corresponds to the second parameter scan in this embodiment, where the target lower limit value in step S134-C is 0.8 nF, and the finally obtained target parameter range in step S135-C is 0.8 nF - 8 nF.

[0159] 2. The abnormal electrical component is R3;

[0160] Assuming that the current resistance value of R3 is 100 KΩ and the scan step is 10 KΩ, and scanning in the direction of decreasing the parameter value, the first voltage waveform (i.e., the voltage waveform output by the multi-channel wake-up circuit) as shown in Figure 9 can be obtained, and the preliminary target parameter range of 10 KΩ - 90 KΩ is determined.

[0161] The above process corresponds to the first parameter scan in this embodiment, and the intermediate result value in step S132-C is 10 KΩ.

[0162] Then, taking the intermediate result value of 10 KΩ as the initial value of the second parameter scan, with a scan step of 1 KΩ which is less than 10 KΩ, and scanning in the direction of decreasing the parameter value, the first voltage waveform as shown in Figure 12 can be obtained. As can be seen from Figure 12 , when the switch is turned on, the response duration becomes longer, and the slowest is more than 10 ms, all meeting the wake-up requirements.

[0163] The above process corresponds to the second parameter scan in this embodiment, and the finally obtained new target parameter range is 1 KΩ - 90 KΩ. However, due to the need for R3 to absorb leakage current, R3 cannot be too small, and generally the maximum value in the target parameter range can be taken, which is 90 KΩ corresponding to this example.

[0164] As can be seen from the above, based on two parameter scans with different step sizes in this embodiment, a more accurate and larger target parameter range can be obtained, thus providing more and more accurate parameter selections for the optimized design of the circuit when optimizing the problem of false wake-up.

[0165] In the above embodiments, a method for handling false wake-up faults is described in detail. The present application also provides an embodiment corresponding to a false wake-up fault handling device. It should be noted that the embodiments of the device part of the present application are described from two perspectives, one is from the perspective of functional modules, and the other is from the perspective of hardware.

[0166] From the perspective of functional modules, as Figure 13 shown, this embodiment provides a false wake-up fault handling device, including:

[0167] A problem analysis module 11, configured to obtain a first voltage waveform at the chip wake-up terminal through an oscilloscope, and determine whether there is a false wake-up problem according to the first voltage waveform. If so, trigger the abnormal location module;

[0168] An abnormal location module 12, configured to obtain second voltage waveforms at each circuit node in the multi-channel wake-up circuit through an oscilloscope, and locate abnormal electrical components according to the second voltage waveforms;

[0169] A parameter determination module 13, configured to determine a target parameter range of the abnormal electrical component according to the first voltage waveform and / or the second voltage waveform; wherein, the target parameter range is the parameter value range of the abnormal electrical component when there is no false wake-up problem;

[0170] A circuit adjustment module 14, configured to adjust the abnormal electrical component according to the target parameter range.

[0171] Since the embodiments of the device part correspond to the embodiments of the method part, for the embodiments of the device part, please refer to the description of the embodiments of the method part, which will not be elaborated here.

[0172] Figure 14 The structure diagram of a false wake-up fault handling device provided in another embodiment of the present application is as Figure 14 shown. A false wake-up fault handling device includes: a memory 20, configured to store a computer program;

[0173] A processor 21, configured to implement the steps of a false wake-up fault handling method as described in the above embodiment when executing the computer program.

[0174] The false wake-up fault handling device provided in this embodiment may include, but is not limited to, a mobile terminal, a personal computer, a workstation, etc.

[0175] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 may be implemented in at least one hardware form of a digital signal processor (DSP), a field-programmable gate array (FPGA), or a programmable logic array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the central processing unit (CPU); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an artificial intelligence (AI) processor, and the AI processor is used to process computational operations related to machine learning.

[0176] The memory 20 may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory 20 is at least used to store the following computer program 201. After the computer program is loaded and executed by the processor 21, it can implement the relevant steps of a misawakening fault handling method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, a misawakening fault handling method, etc.

[0177] In some embodiments, a misawakening fault handling device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0178] Those skilled in the art can understand that Figure 14 the structure shown in

[0179] An accidental wake-up fault handling device provided by an embodiment of the present application includes a memory and a processor. When the processor executes the program stored in the memory, the following method can be implemented: An accidental wake-up fault handling method.

[0180] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by the processor, the steps recorded in the above method embodiments are implemented.

[0181] It can be understood that if the method in the above embodiments is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0182] The above has introduced in detail an accidental wake-up fault handling method, device, and medium provided by the present application. The various embodiments in the specification are described in a progressive manner, and the key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part. It should be noted that for those of ordinary skill in the art in the technical field of the present application, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the present application.

[0183] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

Claims

1. A method for handling a false wakeup fault, characterized in that: include: Obtaining a first voltage waveform at the chip wake-up end through an oscilloscope, and determining whether there is a false wake-up problem according to the first voltage waveform; If so, obtaining a second voltage waveform at each circuit node in the multi-way wake-up circuit through the oscilloscope, and locating the abnormal electrical component according to the second voltage waveform; Determine a target parameter range of the abnormal electrical component according to the first voltage waveform and / or the second voltage waveform; wherein the target parameter range is a parameter value range of the abnormal electrical component when the false wake-up problem does not occur; The abnormal electrical component is adjusted according to the target parameter range.

2. The method for handling false awakening faults according to claim 1, characterized in that: Acquiring a second voltage waveform at each circuit node in the multi-way wake-up circuit by means of the oscilloscope, and locating an abnormal electrical component according to the second voltage waveform includes: Obtaining voltage waveforms at the base of the NPN transistor and the base of the PNP transistor in the multi-way wake-up circuit; If the voltage waveform at the base of the NPN transistor is abnormal and the voltage waveform at the base of the PNP transistor is normal, then obtaining the voltage waveform at the middle point of the resistor-capacitor combination connected to the base of the NPN transistor; If it is determined based on the voltage waveform at the midpoint that the time constant of the resistor-capacitor combination is too large, then one or a group of electrical components in the resistor-capacitor combination that may affect the time constant are determined to be abnormal electrical components.

3. The method for handling false awakening faults according to claim 2, characterized in that: The resistor and capacitor combination includes: a first combined resistor, a second combined resistor, a third combined resistor, a first combined capacitor, a second combined capacitor and a third combined capacitor; Wherein, the first end of the first combined resistor is connected to the base of the NPN transistor, and the second end of the first combined resistor is connected to the collector of the PNP transistor; The first end of the second combined resistor is connected to the base of the NPN transistor, and the second end of the second combined resistor is grounded; the first end of the first combined capacitor is connected to the base of the NPN transistor, and the second end of the first combined capacitor is grounded; the second combined capacitor and the third combined capacitor are connected in parallel; A first end of the third combined resistor is connected to the base of the NPN transistor, and a second end of the third combined resistor is connected to a parallel end of the second combined capacitor and the third combined capacitor; It is characterized in that the abnormal electrical element is: the second combined capacitor and the third combined capacitor, or the first combined resistor.

4. The method for handling false awakening faults according to claim 3, characterized in that: Determining a target parameter range of the abnormal electrical component according to the first voltage waveform and / or the second voltage waveform includes: Obtaining an ideal charging parameter of the base voltage of the NPN transistor when the multi-way wake-up circuit does not have a false wake-up phenomenon; According to the ideal charging parameters, the target parameter range of the abnormal electrical component is determined by the charging formula of the resistor and capacitor combination.

5. The method for handling false awakening faults according to claim 3, characterized in that: Determining a target parameter range of the abnormal electrical component according to the first voltage waveform and / or the second voltage waveform includes: Performing parameter scanning on the abnormal electrical component, and monitoring the first voltage waveform and / or the second voltage waveform to determine whether the false awakening problem disappears; A parameter value range of the abnormal electrical component when the false awakening problem disappears is determined as a target parameter range.

6. The method for handling false awakening faults according to claim 5, characterized in that: Determining a target parameter range of the abnormal electrical component according to the first voltage waveform and / or the second voltage waveform includes: Taking the current parameter value of the abnormal electrical component as the starting value, performing a first parameter scan according to a preset first step length; The upper limit value of the parameter determined during the first parameter scan is used as the target upper limit value, and the lower limit value of the parameter determined during the first parameter scan is used as the intermediate result value; Taking the intermediate result value as the starting value, performing a second parameter scan according to a preset second step length; wherein the second step length is smaller than the first step length; Using the parameter lower limit value determined during the second parameter scan as the target lower limit value; The target parameter range is determined according to the target upper limit value and the target lower limit value.

7. The method for handling false awakening faults according to any one of claims 1 to 6, characterized in that: Acquiring a first voltage waveform at a chip wake-up terminal through an oscilloscope, and judging whether there is a false wake-up problem according to the first voltage waveform includes: Respectively acquiring a plurality of first voltage waveforms at the chip wake-up end at different times; If, among all the first voltage waveforms, the proportion of the first voltage waveforms judged to be abnormal reaches a preset ratio, it is determined that there is a false wake-up problem.

8. A false awakening fault processing device, characterized in that: include: A problem analysis module, used for obtaining a first voltage waveform at the chip wake-up end through an oscilloscope, and judging whether there is a false wake-up problem according to the first voltage waveform, and if so, triggering an abnormality positioning module; The abnormality locating module is used to obtain the second voltage waveform at each circuit node in the multi-way wake-up circuit through the oscilloscope, and locate the abnormal electrical component according to the second voltage waveform; A parameter determination module, configured to determine a target parameter range of the abnormal electrical component according to the first voltage waveform and / or the second voltage waveform; wherein the target parameter range is a parameter value range of the abnormal electrical component when the false wake-up problem does not occur; A circuit adjustment module is used to adjust the abnormal electrical component according to the target parameter range.

9. A false awakening fault processing device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the false wakeup fault handling method as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the false wakeup fault processing method according to any one of claims 1 to 7 are implemented.

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