JBS diode device with multi-stage grooves communicated with buried layer and preparation method of JBS diode device

Abstract

The invention discloses a JBS diode device with multistage grooves communicated with a buried layer and a preparation method of the JBS diode device. The JBS diode device comprises an N-type SiC substrate, an N-type buffer layer and an N-type epitaxial layer, wherein the N-type buffer layer and the N-type epitaxial layer are sequentially located on the upper surface of the N-type SiC substrate from bottom to top; the P-type buried layer is positioned in the N-type epitaxial layer in the middle region; the P + masking region is positioned on the P-type buried layer in the middle region; the P + masking region is of a multi-stage groove structure, and the multi-stage groove structure is of a stepped structure with the left side and the right side in axial symmetry. A certain distance exists between the lowest step surface in the step structure and the P-type buried layer; the N-type current transmission layer is positioned on the P-type buried layer and the N-type epitaxial layer on the two sides of the P + masking region; the P + source region is positioned in the N-type current transmission layer at the two ends of the device; the anode is located on the P + source region, the N-type current transmission layer and the P + masking region; and the cathode is positioned on the lower surface of the N-type SiC substrate. The method can be applied to single particle radiation resistance required by aerospace.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, and particularly relates to a JBS diode device with multi-stage trench-connected buried layers and a preparation method therefor. Background Art

[0002] In the overall favorable environment of the power electronics industry, power semiconductor devices, which play a decisive role in power electronics, have become a direct factor affecting the cost and efficiency of power electronic devices. Although silicon-based power devices are already very mature at the present stage, with the gradual development of power semiconductors towards high power, high frequency, and low power consumption, silicon (Si)-based devices are beginning to be difficult to apply to some high-voltage, high-temperature, high-efficiency, and high-power-density application scenarios due to the limitations of their own physical characteristics. With the rise of third-generation semiconductor technologies, third-generation wide-bandgap semiconductor materials such as silicon carbide and gallium nitride have received extensive attention and research. Taking silicon carbide (4H SiC) as an example, its bandgap width is 3.26 eV, which is more than three times that of traditional silicon materials. Therefore, in extreme working environments where silicon materials are not suitable for application due to their own limitations, the application of wide-bandgap semiconductor materials such as silicon carbide in these fields has gradually become more extensive. In the field of power semiconductor devices, the devices need to operate under extreme conditions such as high temperature, high voltage, and even high radiation.

[0003] With the rapid development of aerospace technology, the demand for the functions and performance of electronic equipment in the aerospace field has increased significantly. For example, power system control and distribution, high-voltage electric propulsion power supply, high-voltage solid-state semiconductor switches in satellites, space probes and space stations all put forward higher application requirements for power devices. In addition, various harsh high-temperature and strong radiation environments in space also bring severe tests to power electronic systems. Cosmic radiation mainly comes from the influence of cosmic rays and space particles. The main sources of cosmic radiation that pose a greater threat to aerospace systems and detectors are galactic cosmic rays, solar cosmic rays and the near-earth Van Allen radiation belt. The effects of cosmic radiation on silicon carbide power devices mainly include displacement effect, total dose effect and single particle effect. When the aircraft shuttles through the Van Allen radiation belt surrounding the earth to outer space activities, the radiation environment will seriously threaten the safety of electronic equipment. When working in outer space for a long time, electronic equipment will also face the test of cosmic rays and solar flares. Therefore, the aerospace field not only needs high-performance power devices to improve overall performance, but also needs radiation-resistant power devices to improve the safety and reliability of working in complex space environments. The threshold voltage for single-particle burnout of a junction barrier Schottky diode (JBS) is about 30% to 50% of the rated voltage, while single-event leakage current (SELC) is triggered at a lower voltage, about 10% to 30% of the rated voltage. Single-particle effects can lead to performance degradation of power electronics systems at the least, or threaten the reliability and on-orbit life of satellites and spacecraft at the worst. Therefore, in order to ensure the reliability and stability of power electronics systems in aerospace applications, research on single-particle effect radiation hardening design of SiC power devices is extremely important. The structure of existing SiC JBS diode devices is as follows: Figure 1 As shown, the SiC JBS diode has weak single-particle radiation resistance and cannot meet the needs of aerospace. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a JBS diode device with multi-level trenches connected to the buried layer and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] In a first aspect, an embodiment of the present invention provides a JBS diode device with a multi-level trench connected to a buried layer, the JBS diode device comprising:

[0006] An N-type SiC substrate, and an N-type buffer layer and an N-type epitaxial layer sequentially located on the upper surface of the N-type SiC substrate from bottom to top;

[0007] A P-type buried layer located in the N-type epitaxial layer in the middle region;

[0008] A P+ masking region is located on the P-type buried layer in the middle region and is in contact with the P-type buried layer; wherein, the P+ masking region is a multi-level trench structure, and the multi-level trench structure is a stepped structure that is axially symmetric on the left and right sides; there is a certain distance between the surface of the lowest step in the stepped structure and the P-type buried layer;

[0009] An N-type current transmission layer is located on the P-type buried layer and the N-type epitaxial layer on both sides of the P+ masking region and is in contact with the P+ masking region; the doping concentration of the N-type current transmission layer is greater than that of the N-type epitaxial layer;

[0010] P+ source regions are located in the N-type current transmission layer at both ends of the device and are not in contact with the P+ masking region;

[0011] An anode is located on the P+ source regions, the N-type current transmission layer, and the P+ masking region;

[0012] A cathode metal is located on the lower surface of the N-type SiC substrate.

[0013] In an embodiment of the present invention, the thickness of the P-type buried layer is 0.7 μm to 2 μm, the width is 7 μm to 13 μm, and the doping concentration is 1E19 cm -3 ~1E20 cm -3 .

[0014] In an embodiment of the present invention, the stepped structure includes a three-order stepped structure.

[0015] In an embodiment of the present invention, the distance from the surface of the highest step in the stepped structure to the upper surface of the P-type buried layer is 2.6 μm to 4.0 μm; the distance from the surface of the lowest step in the stepped structure to the upper surface of the P-type buried layer is 0.2 μm to 0.4 μm.

[0016] In an embodiment of the present invention, the thickness of each step in the stepped structure is 0.8 μm to 1.2 μm;

[0017] The width of the surface of the highest step in the stepped structure is 0.1 μm to 0.2 μm; the width of the surface of the lowest step in the stepped structure is 2.5 μm to 3 μm; the width of the other step surfaces in the stepped structure except for the surface of the highest step and the surface of the lowest step is 0.2 μm to 0.4 μm.

[0018] In an embodiment of the present invention, the thickness of the N-type current transmission layer is 2.6 μm to 4.0 μm.

[0019] In an embodiment of the present invention, in a cross-section along the top-down direction including a P+ masking region, an N-type current transport layer, and a P+ source region: the N-type current transport layer is the bottom surface, the P+ masking region is the center, and the P+ source region is arranged around the P+ masking region; the P+ masking region and the P+ source region are one of a strip structure, a square structure, a hexagonal structure, an octagonal structure, and a dodecagonal structure;

[0020] In a cross-section along the top-down direction including a P+ masking region, a P-type buried layer, and an N-type epitaxial layer: the P-type buried layer is the bottom surface, the P+ masking region is the center, and the N-type epitaxial layer is arranged around the P+ masking region; the P+ masking region and the N-type epitaxial layer are one of a strip structure, a square structure, a hexagonal structure, an octagonal structure, and a dodecagonal structure.

[0021] Second, an embodiment of the present invention provides a method for manufacturing a JBS diode device with multi-level trenches connected to a buried layer, and the manufacturing method includes:

[0022] Select an N-type SiC substrate;

[0023] Epitaxially grow an N-type buffer layer and an N-type epitaxial layer on the upper surface of the N-type SiC substrate in sequence;

[0024] Perform ion implantation on the N-type epitaxial layer in the middle region to form a P-type buried layer;

[0025] Grow an N-type current transport layer on the N-type epitaxial layer and the P-type buried layer; the doping concentration of the N-type current transport layer is greater than that of the N-type epitaxial layer;

[0026] Perform multiple plasma etching on the N-type current transport layer in the middle region to form a multi-level trench structure, and perform ion implantation on the N-type current transport layer at the multi-level trench structure to form a P+ masking region, so that the P-type buried layer in the N-type epitaxial layer is connected to the P+ masking region; wherein, the formed P+ masking region is a multi-level trench structure, and the multi-level trench structure is a stepped structure with axial symmetry on the left and right sides; there is a certain distance between the lowest upper surface of all upper surfaces of the P+ masking region and the P-type buried layer;

[0027] Perform ion implantation on the N-type current transport layer at both ends of the device to form a P+ source region that does not contact the P+ masking region;

[0028] Deposit an anode metal on the P+ source region, the N-type current transport layer, and the P+ masking region to form an anode;

[0029] Deposit a cathode metal on the lower surface of the N-type SiC substrate to form a cathode.

[0030] In one embodiment of the present invention, the stepped structure includes a three - step stepped structure.

[0031] In one embodiment of the present invention, when looking from the top - down direction along the cross - section including the P+ masking region, the N - type current - carrying layer, and the P+ source region: the N - type current - carrying layer is the bottom surface, the P+ masking region is the center, and the P+ source region is arranged around the P+ masking region; the P+ masking region and the P+ source region are one of a strip structure, a square structure, a hexagonal structure, an octagonal structure, and a dodecagonal structure.

[0032] When looking from the top - down direction along the cross - section including the P+ masking region, the P - type buried layer, and the N - type epitaxial layer: the P - type buried layer is the bottom surface, the P+ masking region is the center, and the N - type epitaxial layer is arranged around the P+ masking region; the P+ masking region and the N - type epitaxial layer are one of a strip structure, a square structure, a hexagonal structure, an octagonal structure, and a dodecagonal structure.

[0033] Advantages of the present invention:

[0034] The JBS diode device with multi - level trenches connecting the buried layer proposed by the present invention innovatively proposes a JBS diode device resistant to single - event radiation that can be applied to aerospace requirements. Specifically: By using the method of multi - level trenches connecting the buried layer, when the ordinary SiC JBS device is in reverse bias, the surface peak electric field caused by single - event radiation is weakened and transferred to the buried layer. At the same time, the reverse leakage current is discharged through the multi - level trench anode, reducing the thermoelectric concentration caused by single - event radiation when the device is in reverse bias; and while opening the N - type doped conduction path by ion implantation with a relatively high doping concentration in the current - carrying layer on the epitaxial layer, the specific on - resistance of the device is reduced, preventing the problem of poor forward conduction characteristics of the device due to the relatively high doping concentration of the buried layer structure; Since the present invention does not require an additional deep P - type doped region and can achieve a deep P - type doped region by using a multi - level trench structure, the characteristic on - resistance of the device is effectively reduced.

[0035] The following will further elaborate on the present invention in detail with reference to the drawings and embodiments. Description of the Drawings

[0036] Figure 1 is a schematic structural diagram of an existing SiC JBS diode device;

[0037] Figure 2 is a schematic structural diagram of a JBS diode device with multi - level trenches connecting the buried layer provided by an embodiment of the present invention;

[0038] Figures 3(a) to 3(c) is a schematic cross - section diagram when looking from the top - down direction along the cross - section including the P+ masking region, the N - type current - carrying layer, and the P+ source region provided by an embodiment of the present invention;

[0039] Figures 4(a) to 4(c) is a schematic cross-sectional view along the section including the P+ masking region, P-type buried layer, and N-type epitaxial layer as viewed from the top-down direction provided by an embodiment of the present invention;

[0040] Figure 5 is a schematic flow chart of a preparation method of a JBS diode device with multi-level trenches connecting buried layers provided by an embodiment of the present invention;

[0041] Figures 6(a) to 6(k) is a corresponding structural schematic diagram of the preparation process of a JBS diode device with multi-level trenches connecting buried layers provided by an embodiment of the present invention.

[0042] Description of reference numerals:

[0043] 1 - N-type SiC substrate; 2 - N-type buffer layer; 3 - N-type epitaxial layer; 4 - P-type buried layer; 5 - N-type current transmission layer; 6 - P+ source region; 7 - P+ masking region; 8 - anode; 9 - cathode. Detailed implementation manners

[0044] The present invention will be further described in detail below with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0045] Please refer to Figure 2 , an embodiment of the present invention provides a JBS diode device with multi-level trenches connecting buried layers, and the JBS diode device includes:

[0046] an N-type SiC substrate 1, and an N-type buffer layer 2 and an N-type epitaxial layer 3 that are sequentially located on the upper surface of the N-type SiC substrate 1 from bottom to top;

[0047] a P-type buried layer 4, located in the N-type epitaxial layer 3 in the middle region;

[0048] a P+ masking region 7, located on the P-type buried layer 4 in the middle region and in contact with the P-type buried layer 4; wherein, the P+ masking region 7 is a multi-level trench structure, and the multi-level trench structure is a stepped structure that is axisymmetric on both left and right sides; there is a certain distance between the lowest step surface in the stepped structure and the P-type buried layer 4;

[0049] an N-type current transmission layer 5, located on the P-type buried layer 4 and the N-type epitaxial layer 3 on both sides of the P+ masking region 7 and in contact with the P+ masking region 7; the doping concentration of the N-type current transmission layer 5 is greater than the doping concentration of the N-type epitaxial layer 3;

[0050] a P+ source region 6, located in the N-type current transmission layer 5 at both ends of the device and not in contact with the P+ masking region 7;

[0051] an anode 8, located on the P+ source region 6, the N-type current transmission layer 5, and the P+ masking region 7;

[0052] The cathode 9 metal is located on the lower surface of the N-type SiC substrate 1.

[0053] In the embodiment of the present invention, the doping concentration of the N-type SiC substrate 1 is 1E18 cm -3 ~1E20 cm -3 , and the doping ions can be impurity ions such as N (nitrogen), P (phosphorus), etc. that can form an N-type semiconductor; the thickness of the N-type SiC substrate 1 is 350 μm, and the width is 10 μm to 18 μm. More preferably, the doping concentration of the N-type SiC substrate 1 is 5E18 cm -3 , the thickness is 350 μm, and the width is 15 μm.

[0054] In the embodiment of the present invention, the N-type buffer layer 2 can be an N-type SiC buffer layer, and the doping concentration is 0.5E18 cm -3 ~1.5E18 cm -3 , and the doping ions can be impurity ions such as N (nitrogen), P (phosphorus), etc. that can form an N-type semiconductor; the thickness of the N-type buffer layer 2 is 0.8 μm to 1.2 μm. More preferably, the doping concentration of the N-type buffer layer 2 is 1E18 cm -3 , the thickness is 1 μm, and the width is 15 μm.

[0055] In the embodiment of the present invention, the N-type epitaxial layer 3 can be an N-type SiC epitaxial layer, and the doping concentration is 5E15 cm -3 ~1E16 cm -3 , and the doping ions can be impurity ions such as N (nitrogen), P (phosphorus), etc. that can form an N-type semiconductor; the thickness of the N-type epitaxial layer 3 is 10 μm to 12 μm. Among them, the thickness of the N-type epitaxial layer 3 is determined by the breakdown voltage level of the device. In the embodiment of the present invention, when applied to a 1200V-class device, the doping concentration of the N-type epitaxial layer 3 is 5E15 cm -3 ~1E16 cm -3 , and the thickness is 10 μm to 12 μm. More preferably, the doping concentration of the N-type epitaxial layer 3 is 7E15 cm -3 , the thickness is 11 μm, and the width is 15 μm.

[0056] In the embodiment of the present invention, the doping concentration of the P-type buried layer 4 is 1E19 cm -3 ~1E20 cm -3 , and the doping ions can be impurity ions such as B (boron), Al (aluminum), etc. that can form a P-type semiconductor; the thickness of the P-type buried layer 4 is 0.7 μm to 2 μm, and the width is 7 μm to 13 μm. More preferably, the doping concentration of the P-type buried layer 4 is 6E19 cm -3 , the thickness is 1.6 μm, and the width is 10 μm.

[0057] In the embodiment of the present invention, the N-type current transport layer 5 can be an N-type SiC current transport layer with a doping concentration of 5E16 cm -3 ~1E17 cm -3 , and the doping ions can be impurity ions such as N (nitrogen), P (phosphorus), etc. that can form an N-type semiconductor; the thickness of the N-type current transport layer 5 is 2.6 μm to 4.0 μm. More preferably, the doping concentration of the N-type current transport layer 5 is 8E16 cm -3 , and the thickness is 3.3 μm.

[0058] In the embodiment of the present invention, the doping concentration of the P+ source region 6 is 1E19 cm -3 ~1E20 cm -3 , and the doping ions can be impurity ions such as B (boron), Al (aluminum), etc. that can form a P-type semiconductor; the thickness of the P+ source region 6 is 1 μm to 1.5 μm, and the width is 1.9 μm to 2.1 μm. More preferably, the doping concentration of the P+ source region 6 is 5E19 cm -3 , the thickness is 1.2 μm, and the width is 2 μm.

[0059] In the embodiment of the present invention, the doping concentration of the P+ masking region 7 is 1E19 cm -3 ~1E20 cm -3 , and the doping ions can be impurity ions such as B (boron), Al (aluminum), etc. that can form a P-type semiconductor. More preferably, the doping concentration of the P+ masking region 7 is 5E19 cm -3 .

[0060] The stepped structure in the embodiment of the present invention includes a three-order stepped structure, as Figure 1 shown. In the stepped structure, the distance from the highest stepped surface to the upper surface of the P-type buried layer 4 is 2.6 μm to 4.0 μm. More preferably, this distance is 3.3 μm; the distance from the lowest stepped surface to the upper surface of the P-type buried layer 4 is 0.2 μm to 0.4 μm. More preferably, this distance is 0.3 μm. The thickness of each step in the stepped structure is 0.8 μm to 1.2 μm. More preferably, this thickness is 1 μm; the width of the highest stepped surface in the stepped structure is 0.1 μm to 0.2 μm. More preferably, this width is 0.1 μm; the width of the lowest stepped surface in the stepped structure is 2.5 μm to 3 μm. More preferably, this width is 2.6 μm; the width of the other stepped surfaces except the highest and lowest stepped surfaces in the stepped structure is 0.2 μm to 0.4 μm. More preferably, this width is 0.3 μm.

[0061] It should be noted here that in the embodiment of the present invention, it can be a three-order stepped structure, but it is not limited to a three-order stepped structure and can be applied to the design of various forms of multi-level trench-connected buried layer methods according to actual needs, such as a five-order stepped structure.

[0062] In the embodiment of the present invention, looking from the top view along the cross-section including the P+ masking region 7, the N-type current transmission layer 5, and the P+ source region 6, that is Figure 1 The top view of the structural cross-section at the AA' cut line in the middle: The N-type current transmission layer 5 is the bottom surface, the P+ masking region 7 is the center, and the P+ source region 6 is arranged around the P+ masking region 7; the P+ masking region 7 and the P+ source region 6 are one of a strip structure, a square structure, a hexagonal structure, an octagonal structure, and a dodecagonal structure; among them, Figures 3(a) to 3(c) The cases of the strip structure, the square structure, and the hexagonal structure are respectively illustrated. The octagonal structure and the dodecagonal structure are similar, and the schematic diagrams are not drawn here;

[0063] Looking from the top view along the cross-section including the P+ masking region 7, the P-type buried layer 4, and the N-type epitaxial layer 3, that is Figure 1 The top view of the structural cross-section at the BB' cut line in the middle: The P-type buried layer 4 is the bottom surface, the P+ masking region 7 is the center, and the N-type epitaxial layer 3 is arranged around the P+ masking region 7; the P+ masking region 7 and the N-type epitaxial layer 3 are one of a strip structure, a square structure, a hexagonal structure, an octagonal structure, and a dodecagonal structure; among them, Figures 4(a) to 4(c) The cases of the strip structure, the square structure, and the hexagonal structure are respectively illustrated. The octagonal structure and the dodecagonal structure are similar, and the schematic diagrams are not drawn here.

[0064] It can be seen that the embodiment of the present invention can be applied to various cell shapes, and the required SiC JBS diode device structure is formed by using the multi-level trench structure to connect the buried layer.

[0065] In the embodiment of the present invention, the anode 8 forms a Schottky contact with the current transmission layer, the P+ masking region 7, and the contact region of the P+ source region 6. The metal material of the anode 8 can be Ti. Figure 1 It can be seen that the anode 8 of the present invention is a multi-level trench anode.

[0066] In the embodiment of the present invention, the cathode 9 forms an ohmic contact with the lower surface of the N-type SiC substrate 1. The metal material of the cathode 9 can be metal Ni.

[0067] The JBS diode with a multi-level trench structure connecting the buried layer proposed in the embodiments of the present invention can increase the junction depth of the P+ masking region 7 under the same implantation energy, thereby avoiding the deep trench leakage problem caused by the limited thickness of P-type ion implantation and the problem that the lattice damage caused by excessive implantation energy cannot be repaired. The P-type buried layer 4 is embedded inside the N-type epitaxial layer 3, which can improve the distribution of the electric field in the epitaxial layer of the device under reverse bias. For the SiC floating junction JBS diode formed by simply embedding the P-type buried layer 4 in the ordinary SiC JBS diode, the device performance is poor. For example, when used as a switching element, when the device operates forward, charges are filled into the P-type buried layer 4 region, and the device can operate in reverse only after the charges are restored, and the charge restoration time is relatively long, generally 30 days. Therefore, the SiC floating junction JBS diode device cannot be used as a switch. However, in the embodiments of the present invention, after introducing the P-type buried layer 4, a multi-level trench structure is innovatively designed. The multi-level trench structure brings a deeper P+ masking region 7, which can connect the P-type buried layer 4 inside the N-type epitaxial layer 3, so that the P+ masking region 7 is connected to the P-type buried layer 4, and the defects of the SiC floating junction JBS diode device when used as a switch can be eliminated.

[0068] Compared with the conventional SiC JBS diode, the structure of the SiC JBS diode with a multi-level trench connecting the buried layer increases the contact areas between the P+ masking region 7 and the N-type epitaxial layer 3, and between the P+ masking region 7 and the anode 8 in the longitudinal direction, thereby increasing the area of the current path. The transient large current generated under single-particle radiation can extract the leakage current through the connected P-type buried layer 4 and P+ masking region 7, that is, the extraction of the leakage current can be accelerated under single-particle radiation, and the transient temperature can be reduced. At the same time, the presence of the P-type buried layer 4 changes the internal electric field distribution of the device, effectively reduces the strong electric fields at the cathode / SiC substrate interface and the epitaxial layer / SiC substrate interface, restricts the rapid increase of the temperature at the cathode / SiC substrate interface, and thus improves the threshold of the single-particle leakage degradation of the device.

[0069] In summary, the JBS diode device with multi-level trenches connected to the buried layer proposed in the embodiment of the present invention innovatively proposes a JBS diode device resistant to single-event radiation that can be applied to aerospace requirements. Specifically: by using the method of connecting the multi-level trenches to the buried layer, when the ordinary SiC JBS device is in reverse bias, the surface peak electric field caused by single-event radiation is weakened and transferred to the buried layer. At the same time, the reverse leakage current is discharged through the multi-level trench anode, reducing the thermoelectric concentration caused by single-event radiation when the device is in reverse bias; and by using ion implantation with a relatively high doping concentration in the current transmission layer on the epitaxial layer to open the conductive path of N-type doping, the specific on-resistance of the device is reduced, preventing the problem of poor forward conduction characteristics of the device caused by the relatively high doping concentration of the buried layer structure; since the present invention does not require an additional deep P-type doping region and can achieve a deep P-type doping region by using a multi-level trench structure, the characteristic on-resistance of the device is effectively reduced.

[0070] In a second aspect, please refer to Figure 5 , the embodiment of the present invention provides a preparation method for a JBS diode device with multi-level trenches connected to the buried layer. The preparation method includes:

[0071] S10. Select an N-type SiC substrate 1.

[0072] In the embodiment of the present invention, an N-type SiC substrate 1 with a doping concentration of 1E18 cm -3 ~1E20 cm -3 , a thickness of 350 μm, and a width of 10 μm to 18 μm is selected.

[0073] S20. Epitaxially grow an N-type buffer layer 2 and an N-type epitaxial layer 3 on the upper surface of the N-type SiC substrate 1 in sequence.

[0074] In the embodiment of the present invention, an N-type buffer layer 2 with a doping concentration of 0.5E18 cm -3 ~1.5E18 cm -3 , a thickness of 0.8 μm to 1.2 μm is epitaxially grown on the upper surface of the N-type SiC substrate 1 by using the MOCVD (Metal-Organic Chemical Vapor Deposition) process, as shown in FIG. 6(a); continue to epitaxially grow an N-type epitaxial layer 3 with a doping concentration of 5E15 cm -3 ~1E16 cm -3 , a thickness of 10 μm to 12 μm on the N-type buffer layer 2 by using the MOCVD process, as shown in FIG. 6(b).

[0075] S30. Perform ion implantation on the N-type epitaxial layer 3 in the middle region to form a P-type buried layer 4.

[0076] In the embodiment of the present invention, a P-type ion implantation is performed on the N-type epitaxial layer 3 in the middle region by an ion implantation process to form a P-type buried layer 4 with a doping concentration of 1E19 cm -3 ~1E20 cm -3 , a thickness of 0.7 μm to 2 μm, and a width of 7 μm to 13 μm, as shown in FIG. 6(c).

[0077] S40. Grow an N-type current transmission layer 5 on the N-type epitaxial layer 3 and the P-type buried layer 4; the doping concentration of the N-type current transmission layer 5 is greater than the doping concentration of the N-type epitaxial layer 3.

[0078] In the embodiment of the present invention, an N-type current transmission layer 5 with a doping concentration of 5E16 cm -3 ~1E17 cm -3 and a thickness of 2.6 μm to 4.0 μm is grown on the P-type buried layer 4 by an MOCVD process.

[0079] S50. Perform multiple plasma etching on the N-type current transmission layer 5 in the middle region to form a multi-level trench structure, and perform ion implantation on the N-type current transmission layer 5 at the multi-level trench structure to form a P+ masking region 7, so that the P-type buried layer 4 in the N-type epitaxial layer 3 is connected to the P+ masking region 7; wherein, the P+ masking region 7 is a multi-level trench structure, and the multi-level trench structure is a stepped structure that is axisymmetric on the left and right sides; there is a certain distance between the lowest upper surface of all the upper surfaces of the P+ masking region 7 and the P-type buried layer 4.

[0080] In the embodiment of the present invention, first grow a SiO2 etching mask layer on the N-type current transmission layer 5 in the middle region, and perform multiple plasma etching to form a multi-level trench structure, as Figures 6(e) to 6(g) shown Figures 6(e) to 6(g)It schematically shows a three - level trench structure formed by three - time etching. The three - level trench structure is a three - order stepped structure that is axisymmetric on the left and right sides: Figure 6(e) shows the structure after the first etching using the SiO2 etching mask layer. The width of the trench after the first etching is 2.5μm - 3μm, which is the width of the lowest stepped surface in the three - order stepped structure. At this time, the etching depth is 2.4μm - 3.6μm, ensuring that the distance from the lowest stepped surface in the stepped structure to the upper surface of the P - type buried layer 4 is 0.2μm - 0.4μm; Figure 6(f) shows the structure after the second etching continued using the SiO2 etching mask layer. During the etching process, the width of the etching step is 0.2μm - 0.4μm and the thickness of the step is 0.8μm - 1.2μm to form the first step; Figure 6(g) shows the structure after the third etching continued using the SiO2 etching mask layer. During the etching process, the width of the etching step is 0.2μm - 0.4μm and the thickness of the step is 0.8μm - 1.2μm to form the second step, and finally a three - order stepped structure is formed; Then, an ion implantation process is used to perform P - type ion implantation on the N - type current - carrying layer 5 at the location where the multi - level trench structure is formed to form a P+ masking region 7. At this time, after implantation, it is ensured that the width of the highest stepped surface in the stepped structure is 0.1μm - 0.2μm, so that the P+ masking region 7 is connected to the P - type buried layer 4 in the N - type epitaxial layer 3. After that, a high - temperature annealing process is carried out to activate the ions.

[0081] S60. Ion implantation is performed on the N - type current - carrying layers 5 at both ends of the device to form a P+ source region 6 that does not contact the P+ masking region 7.

[0082] In the embodiment of the present invention, an ion implantation process is used to perform ion implantation on the N - type current - carrying layers 5 at both ends of the device to form a P+ source region 6 with a doping concentration of 1E19 cm -3 ~1E20 cm -3 , a thickness of 1μm - 1.5μm, and a width of 1.9μm - 2.1μm, as shown in Figure 6(h). After that, a high - temperature annealing process is carried out to activate the ions.

[0083] S70. Anode metal is deposited on the P+ source region 6, the N - type current - carrying layer 5, and the P+ masking region 7 to form an anode 8.

[0084] In the embodiment of the present invention, an electron beam evaporation process is used to deposit anode metal with a thickness of 300nm on the P+ source region 6, the N - type current - carrying layer 5, and the P+ masking region 7 to form an anode 8, as shown in Figure 6(j); The anode metal can be Ti and form a Schottky contact with the upper surfaces of the P+ source region 6, the N - type current - carrying layer 5, and the P+ masking region 7.

[0085] S80. Cathode metal is deposited on the lower surface of the N - type SiC substrate 1 to form a cathode 9.

[0086] In the embodiment of the present invention, an electron beam evaporation process is adopted to deposit a cathode metal with a thickness of 100 nm on the lower surface of the N-type SiC substrate 1 to form a cathode 9, as shown in FIG. 6(k); the cathode metal can be Ni and form an ohmic contact with the lower surface of the N-type SiC substrate 1.

[0087] After the above S10 - S80, the embodiment of the present invention forms a JBS diode device with a three-level trench-connected buried layer. Looking at the cross-section of the JBS diode device including the P+ masking region 7, the N-type current transmission layer 5, and the P+ source region 6 from the top view direction: the N-type current transmission layer 5 is the bottom surface, the P+ masking region 7 is the center, and the P+ source region 6 is arranged around the P+ masking region 7; the P+ masking region 7 and the P+ source region 6 are one of a strip structure, a square structure, and a hexagonal structure; looking at the cross-section of the JBS diode device including the P+ masking region 7, the P-type buried layer 4, and the N-type epitaxial layer 3 from the top view direction: the P-type buried layer 4 is the bottom surface, the P+ masking region 7 is the center, and the N-type epitaxial layer 3 is arranged around the P+ masking region 7; the P+ masking region 7 and the N-type epitaxial layer 3 are one of a strip structure, a square structure, a hexagonal structure, an octagonal structure, and a dodecagonal structure.

[0088] For the embodiment of the preparation method in the second aspect, since it is basically similar to the embodiment of the device structure in the first aspect, the description is relatively simple. For the relevant parts, refer to the partial description of the embodiment of the device structure in the first aspect.

[0089] In the description of the present invention, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, the meaning of "a plurality" is two or more unless otherwise specifically defined.

[0090] Although the present invention is described herein in connection with various embodiments, however, in the process of implementing the claimed invention, those skilled in the art can understand and achieve other variations of the disclosed embodiments by referring to the specification and its drawings. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality. Certain measures are recited in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0091] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A JBS diode device with multi-level trenches connected to the buried layer, characterized in that: The JBS diode device comprises: An N-type SiC substrate, and an N-type buffer layer and an N-type epitaxial layer sequentially located on the upper surface of the N-type SiC substrate from bottom to top; A P-type buried layer located in the N-type epitaxial layer in the middle region; A P+ shielding region is located on the P-type buried layer in the middle region and contacts the P-type buried layer; wherein the P+ shielding region is a multi-level groove structure, and the multi-level groove structure is a stepped structure with axisymmetric left and right sides; a lowest step surface in the stepped structure is at a certain distance from the P-type buried layer; An N-type current transmission layer, located on the P-type buried layer and the N-type epitaxial layer on both sides of the P+ shielding region, and in contact with the P+ shielding region; the doping concentration of the N-type current transmission layer is greater than the doping concentration of the N-type epitaxial layer; A P+ source region, located in the N-type current transmission layer at both ends of the device and not in contact with the P+ shielding region; an anode, located on the P+ source region, the N-type current transmission layer, and the P+ shielding region; The cathode metal is located on the lower surface of the N-type SiC substrate.

2. The JBS diode device with multi-level trenches connected to the buried layer according to claim 1, characterized in that: The thickness of the P-type buried layer is 0.7 μm to 2 μm, the width is 7 μm to 13 μm, and the doping concentration is 1E19 cm -3 ~1E20cm -3 .

3. The JBS diode device with multi-level trenches connected to the buried layer according to claim 1, characterized in that: The step structure includes a three-step step structure.

4. The JBS diode device with multi-level trenches connected to the buried layer according to claim 1, characterized in that: The distance from the highest step surface in the stepped structure to the upper surface of the P-type buried layer is 2.6 μm to 4.0 μm; the distance from the lowest step surface in the stepped structure to the upper surface of the P-type buried layer is 0.2 μm to 0.4 μm.

5. The JBS diode device with multi-level trenches connected to the buried layer according to claim 1, characterized in that: The thickness of each step in the step structure is 0.8 μm to 1.2 μm; The width of the highest step surface in the stepped structure is 0.1 μm to 0.2 μm; the width of the lowest step surface in the stepped structure is 2.5 μm to 3 μm; the width of other step surfaces in the stepped structure except the highest step surface and the lowest step surface is 0.2 μm to 0.4 μm.

6. The JBS diode device with multi-level trenches connected to the buried layer according to claim 1, characterized in that: The thickness of the N-type current transport layer is 2.6 μm to 4.0 μm.

7. The JBS diode device with multi-level trenches connected to the buried layer according to claim 1, characterized in that: Looking from the top direction along the cross section including the P+ shielding area, the N-type current transmission layer, and the P+ source area: the N-type current transmission layer is the bottom surface, the P+ shielding area is the center, and the P+ source area is arranged around the P+ shielding area; the P+ shielding area and the P+ source area are one of a strip structure, a square structure, a hexagonal structure, an octagonal structure, and a dodecagonal structure; Looking from the top direction along the cross section including the P+ shielding area, the P-type buried layer, and the N-type epitaxial layer: the P-type buried layer is the bottom surface, the P+ shielding area is the center, and the N-type epitaxial layer is arranged around the P+ shielding area; the P+ shielding area and the N-type epitaxial layer are one of a strip structure, a square structure, a hexagonal structure, an octagonal structure, and a dodecagonal structure.

8. A method for preparing a JBS diode device with multi-level trenches connected to the buried layer, characterized in that: The preparation method comprises: Select N-type SiC substrate; epitaxially growing an N-type buffer layer and an N-type epitaxial layer in sequence on the upper surface of the N-type SiC substrate; Performing ion implantation on the N-type epitaxial layer in the middle region to form a P-type buried layer; Growing an N-type current transport layer on the N-type epitaxial layer and the P-type buried layer; the doping concentration of the N-type current transport layer is greater than the doping concentration of the N-type epitaxial layer; Plasma etching is performed multiple times on the N-type current transmission layer in the middle region to form a multi-level groove structure, and ion implantation is performed on the N-type current transmission layer at the multi-level groove structure to form a P+ shielding region, so that the P-type buried layer in the N-type epitaxial layer is connected to the P+ shielding region; wherein the formed P+ shielding region is a multi-level groove structure, and the multi-level groove structure is a stepped structure with axisymmetric left and right sides; the lowest upper surface of all upper surfaces of the P+ shielding region is at a certain distance from the P-type buried layer; Performing ion implantation on the N-type current transport layer at both ends of the device to form a P+ source region that is not in contact with the P+ shielding region; Depositing anode metal on the P+ source region, the N-type current transport layer, and the P+ masking region to form an anode; A cathode metal is deposited on the lower surface of the N-type SiC substrate to form a cathode.

9. The method for preparing a JBS diode device with multi-level trenches connected to the buried layer according to claim 8, characterized in that: The step structure includes a three-step step structure.

10. The method for preparing a JBS diode device with multi-level trenches connected to the buried layer according to claim 8, characterized in that: Looking from the top direction along the cross section including the P+ shielding area, the N-type current transmission layer, and the P+ source area: the N-type current transmission layer is the bottom surface, the P+ shielding area is the center, and the P+ source area is arranged around the P+ shielding area; the P+ shielding area and the P+ source area are one of a strip structure, a square structure, a hexagonal structure, an octagonal structure, and a dodecagonal structure; Looking from the top direction along the cross section including the P+ shielding area, the P-type buried layer, and the N-type epitaxial layer: the P-type buried layer is the bottom surface, the P+ shielding area is the center, and the N-type epitaxial layer is arranged around the P+ shielding area; the P+ shielding area and the N-type epitaxial layer are one of a strip structure, a square structure, a hexagonal structure, an octagonal structure, and a dodecagonal structure.

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