Low-specific-on-resistivity GaN HEMT device and preparation method thereof

Abstract

The invention provides a low-specific-on-resistivity GaN HEMT device and a preparation method thereof. The preparation method comprises the following steps: obtaining a thick-barrier GaN epitaxial structure; manufacturing a low-loss etched hard mask medium on a thick-barrier GaN epitaxial structure of the GaN HEMT device with low specific on-resistivity to form a passivation medium film; defining a gate region of the medium by utilizing a photoetching process, and defining a hard mask medium pattern by adopting a medium etching process; carrying out barrier layer groove etching by adopting a GaN low-loss etching process; etching is accurately stopped; adopting a molecular beam epitaxy process to perform secondary epitaxy on a p-GaN layer in a selected area so as to realize complete depletion of two-dimensional electron gas in a grid area; removing the polycrystalline GaN on the hard mask medium; and after horizontal GaN HEMT tape-out, metal deposition of a source electrode, a drain electrode and a grid electrode of the GaN HEMT is carried out. According to the method, a thick barrier layer structure is adopted, the specific on-resistivity limitation of the device is reduced, the device has low specific on-resistivity, the reliability of the grid electrode is improved, and the stability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly relates to a low specific on-resistance GaN HEMT device and a preparation method thereof. Background Art

[0002] Due to its high critical breakdown electric field and relatively large carrier mobility, gallium nitride (GaN) is very suitable for manufacturing high-efficiency power switching devices compared with traditional silicon (Si) materials, which has greatly promoted the development of advanced GaN components.

[0003] However, in a conventional gallium nitride high electron mobility transistor (GaN HEMT), there is still a high concentration of two-dimensional electron gas (2DEG) in the channel without any bias voltage. The conventional AlGaN / GaN HEMT device is in an on state when no voltage is applied between the gate and the source, and only turns off when a negative voltage is applied to the gate. This characteristic easily causes the device to be misconducted when the gate signal is lost, thus leading to a short circuit in the circuit. Therefore, its application in the circuit is limited.

[0004] In order to meet the requirements of circuit reliability and safety, an enhancement-mode GaN HEMT has emerged. The enhancement-mode GaN HEMT is in an off state when no voltage is applied between the gate and the source, and only conducts when a positive voltage is applied. Therefore, it has become a more conventional and mainstream GaN power device.

[0005] Currently, the main implementation schemes of enhancement-mode HEMTs include p-GaN gates and recessed gates. Existing p-GaN HEMTs generally have problems such as a relatively large specific on-resistance and dynamic resistance degradation at high frequencies, while recessed-gate enhancement-mode GaN HEMTs have defects in the reliability of the gate dielectric.

[0006] In view of the above technical problems, the present invention proposes a new low specific on-resistance GaN HEMT device and a preparation method thereof. Summary of the Invention

[0007] Based on the above description, the present invention provides a low specific on-resistance GaN HEMT device and a preparation method thereof to solve the technical problem of the large specific on-resistance existing in the existing enhancement-mode GaN HEMT.

[0008] The technical solution of the present invention to solve the above technical problems is as follows: In a first aspect, the present invention provides a preparation method of a low specific on-resistance GaN HEMT device, including the following steps: S1: Using MOCVD technology, grow a starting layer, a buffer layer, a channel layer, an insertion layer, and a thick barrier layer on a hetero-substrate wafer from bottom to top in sequence to obtain a thick-barrier GaN epitaxial structure; S2: Use ALD, PECVD, and LPCVD methods to fabricate a hard mask dielectric for low-loss etching on the thick barrier GaN epitaxial structure to form a passivation dielectric film; S3: Use photolithography to define the gate region of the dielectric, and use dielectric etching to define the hard mask dielectric pattern; S4: Continue to use the GaN low-loss etching process to etch the barrier layer grooves to weaken the two-dimensional electron gas in the gate region; selectively stop the etching precisely by means of the insertion layer; S5: Use molecular beam epitaxy to selectively re-epitaxially grow the p-GaN layer in the selected area to completely deplete the two-dimensional electron gas in the gate region; S6: Use a wet process to selectively remove polycrystalline GaN on the hard mask dielectric; S7: On the obtained structural wafer, after fabricating the horizontal GaN HEMT, deposit metals for the source, drain, and gate of the GaN HEMT to obtain a low specific on-resistance GaN HEMT device.

[0009] Based on the above technical solutions, the present invention can be further improved as follows.

[0010] Further, in step S1, the hetero-substrate wafer is a p-type conductive silicon wafer or a top silicon conductive SOI wafer.

[0011] Further, in step S1, the channel layer is an i-GaN layer; The insertion layer is an AlN layer with a high Al composition; The thick barrier layer is an AlGaN layer.

[0012] Further, the thickness of the channel layer is 50 - 800 nm, the thickness of the insertion layer is 0 - 5 nm, and the thickness of the thick barrier layer is 15 - 35 nm.

[0013] Further, in step S6, the re-growth temperature of the molecular beam epitaxy process is 550 - 900 °C; The thickness of the p-GaN layer is 50 - 200 nm.

[0014] In a second aspect, the present invention also provides a low specific on-resistance GaN HEMT device, which is prepared according to the preparation method of the low specific on-resistance GaN HEMT device described in the first aspect, and includes: a thick barrier GaN epitaxial structure, a passivation dielectric film, a p-GaN layer, a gate, a source, and a drain; The passivation dielectric film is disposed on the thick barrier GaN epitaxial structure; A trench region is provided in the middle region of the thick barrier GaN epitaxial structure and the passivation dielectric film; The p-GaN layer is disposed in the trench region, and its bottom and side surfaces are in contact with the thick-barrier GaN epitaxial structure; The gate is disposed on the p-GaN layer and is in contact with the passivation dielectric film; The source electrode and the drain electrode are respectively disposed on both sides of the overall structure.

[0015] On the basis of the above technical solutions, the present invention can also be improved as follows.

[0016] Further, the cross-section of the trench region is in an inverted trapezoidal shape.

[0017] Further, the thick-barrier GaN epitaxial structure includes a starting layer, a buffer layer, a channel layer, an insertion layer, and a thick-barrier layer arranged in sequence from bottom to top.

[0018] The low specific on-resistance GaN HEMT device, device structure and preparation method thereof provided by the present invention. The preparation method is to use a GaN epitaxial wafer with a thick barrier to form a gate groove through low-loss etching, and then realize an enhancement-mode high-voltage power device with a lower specific on-resistance and better dynamic stability through MBE secondary epitaxy of p-GaN. Compared with the prior art, it has the following beneficial effects: 1. A GaN HEMT power device is obtained through MBE secondary epitaxy of p-GaN. By adopting a thick barrier layer structure, the limitation of the device specific on-resistance decreases. More devices can be fabricated from epitaxial wafers of the same size, which is conducive to reducing the cost of a single device.

[0019] 2. By adopting a thick barrier layer structure, the distance between the channel electrons and the surface of the barrier layer is farther, and there is no etching damage on the surface of the barrier layer above the channel layer. The device has better high-frequency dynamic characteristics.

[0020] 3. By adopting a thick barrier layer structure, a groove in the gate region is fabricated using a GaN low-loss etching process. On this basis, secondary epitaxy of p-GaN is carried out to achieve enhancement mode. The repair of the low-loss etching interface can be realized before the secondary epitaxy, and no gate dielectric is required for the gate in this solution, thus improving the stability and consistency of the gate threshold voltage.

[0021] 4. An enhancement-mode GaN HEMT power device is realized through MBE secondary epitaxy of p-GaN, which can minimize the degradation of the two-dimensional electron gas of the grown HEMT, reduce the risk of cracks in the epitaxial wafer, and the p-GaN grown by MBE does not require subsequent activation treatment.

[0022] 5. The opening of the hard mask in the gate region is realized by dielectric etching. On this basis, secondary epitaxy of p-GaN is carried out to achieve enhancement mode. The repair of the etched surface can be realized before the secondary epitaxy, improving the reliability of the gate and further enhancing the stability of the device. Description of the Drawings

[0023] Figures 1 to 5 Schematic diagram of the preparation method of the low specific on-resistance GaN HEMT device provided in Embodiment 1 of the present invention; Figure 6 Schematic diagram of the structure of the low specific on-resistance GaN HEMT device provided in Embodiment 6 of the present invention; In the drawings, the list of components represented by each reference numeral is as follows: 1. Thick-barrier GaN epitaxial structure; 2. Passivation dielectric film; 3. p-GaN layer; 4. Gate; 5. Source; 6. Drain. Detailed implementation manners

[0024] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0025] The following further describes in detail the implementation manners of the present invention in conjunction with the drawings and embodiments. The following embodiments are used to illustrate the present invention but cannot be used to limit the scope of the present invention.

[0026] Embodiment 1 As Figure 1 shown, this embodiment provides a preparation method of a low specific on-resistance GaN HEMT device, including the following steps: Step 1, as Figure 1 shown, epitaxially grow a thick-barrier GaN structure: Use MOCVD (Metal Organic Chemical Vapor Deposition) technology to grow a starting layer, a buffer layer, an i-GaN channel layer, a high-Al-component AlN insertion layer, and an AlGaN thick-barrier layer on a p-type conductive silicon wafer from bottom to top. Among them, the thickness of the channel layer is 50 - 800 nm, the thickness of the insertion layer is 0 - 5 nm, and the thickness of the thick-barrier layer is 15 - 35 nm.

[0027] In an optional specific example, the starting layer (200 nm thickness), buffer layer (2 µm thickness), i-GaN channel layer (400 nm thickness), high-Al-component AlN insertion layer (1 nm thickness), and AlGaN thick-barrier layer (25 nm thickness) of the channel layer, high-Al-component AlN insertion layer, and AlGaN thick-barrier layer.

[0028] The above-mentioned MOCVD epitaxial structure is different from the conventional E-mode GaN HEMT epitaxial wafer. It has a thicker barrier layer and no p-GaN layer. It essentially uses the secondary epitaxy of the D-mode GaN epitaxial wafer to achieve the E-mode function.

[0029] like Figure 2 As shown, including steps 2 to 4: Step 2: Making a hard mask medium for low-loss etching: The ALD (atomic layer deposition) method is used to make a low-loss etching hard mask dielectric on the thick barrier GaN epitaxial structure to form a passivation dielectric film.

[0030] In an optional specific example, the passivation dielectric film is composed of a layer of Al2O3 with a thickness of 3 nm and a layer of SiO2 with a thickness of 200 nm.

[0031] Step 3: Define the gate region: A photolithography process is used to define the gate region of the dielectric, and a dielectric etching process (such as inductively coupled plasma etching, ICP, or reactive ion etching, RIE) is used to define the hard mask dielectric pattern.

[0032] Step 4: Etching the barrier layer groove: Continue to use GaN low-loss etching process (such as ICP etching) to etch the barrier layer groove. In the specific example, the groove depth can be selectively about 15 nm to achieve the weakening of the two-dimensional electron gas in the gate area; selectively use the insertion layer to achieve precise stopping of etching.

[0033] Step 5: Figure 3 As shown, the secondary epitaxial p-GaN layer is selected: The MBE (molecular beam epitaxy) process is used to selectively grow the p-GaN layer for secondary epitaxy. The regrowth temperature is 550~900℃, and the p-GaN layer thickness is 50~200nm. In the specific example, the regrowth temperature is 700℃, and the p-GaN layer thickness is 100 nm.

[0034] Different from the groove-type GaN MISHEMT scheme, the groove of this scheme undergoes secondary epitaxy through MBE selective area growth to achieve the filling of the groove with p-GaN.

[0035] Cross-sectional SEM / TEM can characterize the features of the groove gate structure filled with p-GaN, and the hard mask dielectric etched opening is further etched with low loss to form a gate groove. Therefore, there is no overlap between the dielectric opening and the groove, and there is no overlapping feature when p-GaN is filled through the AlGaN barrier layer.

[0036] Step 6: Figure 4 As shown, removing polycrystalline GaN: Selectively remove polycrystalline GaN on the hard mask medium using a wet process (such as a mixed solution of hydrofluoric acid and phosphoric acid). Ensure that the surface of the gate region is flat and there is no residual excess material.

[0037] Step 7: As Figure 5 shown, wafer processing and metal deposition: Based on the obtained structural wafer, after wafer processing of horizontal GaN HEMT, deposit metals (such as Ti / Al / Ni / Au) for the source, drain, and gate of GaN HEMT to obtain a low specific on-resistance GaN HEMT device.

[0038] Example 2 Based on Example 1, the difference from Example 1 is: In Step 1: Use MOCVD (Metal Organic Chemical Vapor Deposition) technology to grow an initial layer (150 nm thickness), a buffer layer (800 nm thickness), an i-GaN channel layer (200 nm thickness), a high-Al component AlN insertion layer (1 nm thickness), and an AlGaN thick barrier layer (22 nm thickness) sequentially from bottom to top on a top-silicon-conductive SOI substrate.

[0039] Example 3 Based on Example 1, the difference from Example 1 is: Add a step: High-frequency characteristic test Conduct a high-frequency characteristic test on the fabricated device. The results show that the device exhibits excellent dynamic characteristics in high-frequency applications, and the dynamic resistance degradation at high frequencies is significantly reduced, making it suitable for high-frequency power switching applications.

[0040] Example 4 Based on Example 1, the difference from Example 1 is: Add a step: Reliability test Conduct a reliability test on the fabricated device, including high-temperature reverse bias (HTRB), high-temperature and high-humidity (H3TRB), and high-accelerated life test (HALT). The test results show that the device exhibits excellent stability and reliability under high-stress conditions, making it suitable for high-reliability applications.

[0041] Example 5 Based on Example 1, the difference from Example 1 is: Add a step: Cost analysis and optimization Conduct a cost analysis on the entire fabrication process. By optimizing the epitaxial growth conditions, reducing material waste, and simplifying the process steps, significantly reduce the production cost of the device, making it more suitable for mass production.

[0042] Example 6 This embodiment provides a device structure corresponding to Embodiment 1, such as Figure 6 shown, including: a thick-barrier GaN epitaxial structure 1, a passivation dielectric film 2, a p-GaN layer 3, a gate 4, a source 5, and a drain 6.

[0043] The passivation dielectric film 2 is disposed on the thick-barrier GaN epitaxial structure 1.

[0044] A trench region is provided in the middle region of the thick-barrier GaN epitaxial structure 1 and the passivation dielectric film 2; the cross-section of the trench region is trapezoidal in reverse.

[0045] The p-GaN layer 3 is disposed in the trench region, and the bottom and sides are in contact with the thick-barrier GaN epitaxial structure 1.

[0046] The gate 4 is disposed on the p-GaN layer 3 and is in contact with the passivation dielectric film 2.

[0047] The source 5 and the drain 6 are respectively disposed on both sides of the overall structure.

[0048] In an optional example, the thick-barrier GaN epitaxial structure 1 includes a starting layer, a buffer layer, a channel layer, an insertion layer, and a thick-barrier layer arranged in sequence from bottom to top.

[0049] In summary, the low specific on-resistance GaN HEMT devices and the corresponding preparation methods provided in the above Embodiments 1 to 6 all have the following technical effects: 1. By MBE secondary epitaxy of p-GaN to obtain a GaN HEMT power device, adopting a thick barrier layer structure, the specific on-resistance limit of the device decreases, and more devices can be fabricated on the same-size epitaxial wafer, which is beneficial to reducing the cost of a single device.

[0050] 2. Adopting a thick barrier layer structure, the distance between the channel electrons and the surface of the barrier layer is farther, and there is no etching damage on the surface of the barrier layer above the channel layer, so the device has better high-frequency dynamic characteristics.

[0051] 3. Adopting a thick barrier layer structure, using a GaN low-loss etching process to prepare the groove in the gate region, and then realizing enhancement by secondary epitaxy of p-GaN. The repair of the low-loss etching interface can be achieved before the secondary epitaxy, and in this scheme, the gate does not require a gate dielectric, and the stability and consistency of the gate threshold voltage are improved.

[0052] 4. By MBE secondary epitaxy of p-GaN to realize an enhancement-mode GaN HEMT power device, the degradation of the grown HEMT two-dimensional electron gas can be small, the risk of cracks in the epitaxial wafer is low, and the p-GaN grown by MBE does not require subsequent activation treatment.

[0053] 5. The hard mask opening in the gate region is achieved by medium etching. On this basis, secondary epitaxial growth of p-GaN is carried out to achieve enhancement. The repair of the etched surface can be realized before the secondary epitaxial growth, the gate reliability is improved, and the device stability is further enhanced.

[0054] In the description of this specification, the description with reference to terms such as "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a low specific on-resistivity GaN HEMT device, characterized in that: The following steps are involved: S1: Using MOCVD technology, a starting layer, a buffer layer, a channel layer, an insertion layer and a thick barrier layer are grown sequentially from bottom to top on a heterogeneous substrate to obtain a thick barrier GaN epitaxial structure; S2: using ALD, PECVD and LPCVD methods to produce a hard mask dielectric for low-loss etching on the thick barrier GaN epitaxial structure to form a passivation dielectric film; S3: using a photolithography process to define a gate region of the dielectric, and using a dielectric etching process to define a hard mask dielectric pattern; S4: Continue to use the GaN low-loss etching process to perform barrier layer groove etching to achieve weakening of the two-dimensional electron gas in the gate area; selectively use the insertion layer to achieve precise etching stop; S5: Selectively grow a secondary epitaxial p-GaN layer using a molecular beam epitaxy process to achieve complete depletion of the two-dimensional electron gas in the gate region; S6: selectively removing polycrystalline GaN on the hard mask dielectric using a wet process; S7: Based on the obtained structure wafer, after the horizontal GaN HEMT is taped out, metal deposition of the GaN HEMT source, drain and gate is performed to obtain a low specific on-resistivity GaN HEMT device.

2. The preparation method according to claim 1, characterized in that: In step S1, the foreign substrate wafer is a p-type conductive silicon wafer or a top silicon conductive SOI wafer.

3. The preparation method according to claim 1, characterized in that: In step S1, the channel layer is an i-GaN layer; The insertion layer is an AlN layer with a high Al component; The thick barrier layer is an AlGaN layer.

4. The preparation method according to claim 3, characterized in that: The thickness of the channel layer is 50-800 nm, the thickness of the insertion layer is 0-5 nm, and the thickness of the thick barrier layer is 15-35 nm.

5. The preparation method according to claim 1, characterized in that: In step S5, the regrowth temperature of the molecular beam epitaxy process is 550-900°C; The thickness of the p-GaN layer is 50~200nm.

6. A low specific on-resistivity GaN HEMT device, wherein the low specific on-resistivity GaN HEMT device is prepared according to the method for preparing a low specific on-resistivity GaN HEMT device according to any one of claims 1 to 5, characterized in that: include: Thick barrier GaN epitaxial structure, passivation dielectric film, p-GaN layer, gate, source and drain; The passivation dielectric film is disposed on the thick barrier GaN epitaxial structure; The thick barrier GaN epitaxial structure and the middle region of the passivation dielectric film are provided with a groove region; The p-GaN layer is disposed in the groove region, and the bottom and side surfaces are in contact with the thick barrier GaN epitaxial structure; The gate is disposed on the p-GaN layer and is in contact with the passivation dielectric film; The source electrode and the drain electrode are respectively arranged on two sides of the overall structure.

7. The low specific on-resistivity GaN HEMT device according to claim 6, characterized in that: The cross section of the groove region is in an inverted trapezoidal shape.

8. The low specific on-resistivity GaN HEMT device according to claim 6, characterized in that: The thick barrier GaN epitaxial structure comprises a starting layer, a buffer layer, a channel layer, an insertion layer and a thick barrier layer which are arranged in sequence from bottom to top.

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