Wafer fabrication methods based on laser stealth

Abstract

This invention provides a wafer processing method based on laser stealth. The method includes: Step A, performing a first-round laser stealth processing to obtain multiple first kerfs and multiple inter-kerf regions distributed side-by-side within the wafer; Step C, performing subsequent laser stealth processing to obtain multiple subsequent kerfs and multiple inter-kerf regions distributed side-by-side within the wafer. The subsequent kerfs include multiple second kerfs located within the multiple inter-kerf regions, and the inter-kerf regions include multiple second inter-kerf regions and third inter-kerf regions. Each second kerf divides the first inter-kerf region into a second inter-kerf region and a third inter-kerf region. This invention can reduce the difficulty of wafer stripping and can also reduce the thickness of the wafer's loss layer, thereby reducing the wafer's production cost. Since it eliminates the need to repeatedly move the laser focus along the kerfs, this invention can reduce the number of times the laser focus moves along the kerfs, reducing the probability of defects inside the wafer and thus improving the wafer's production yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a wafer processing method based on laser stealth. Background Technology

[0002] Laser stealth is a semiconductor processing method. Taking laser stealth of silicon carbide as an example, the laser stealth processing method will cause complex physical and chemical modifications within the silicon carbide wafer. Existing laser stealth processes often lead to thicker wafer loss layers and an increased probability of internal defects, which increases wafer production costs and reduces wafer production yield. Changing the process parameters of laser stealth may cause the cracks generated by laser cutting to fail to meet the requirements for wafer slicing, making it difficult to peel off the wafer. Summary of the Invention

[0003] In view of this, the present invention provides a wafer processing method based on laser stealth, which enables wafers to be more easily stripped and diced, reduces wafer loss and improves wafer yield.

[0004] The laser stealth-based wafer fabrication method of the present invention includes:

[0005] A. The first round of laser stealth processing was carried out, resulting in multiple parallel and spaced first cuts and multiple inter-cut regions within the wafer;

[0006] C. Perform subsequent laser stealth processing to obtain multiple parallel and spaced subsequent cuts and multiple subsequent cut regions within the wafer.

[0007] The subsequent cuts include multiple second cuts located in multiple first inter-cut regions. The subsequent inter-cut regions include multiple second inter-cut regions and third inter-cut regions. Each second cut divides the first inter-cut region into a second inter-cut region and a third inter-cut region.

[0008] This invention obtains all required cuts in at least two rounds of laser stealth processing. These cuts include the first cut and subsequent cuts obtained from steps A and C. Simultaneously, these cuts divide the wafer into multiple second and third inter-cut regions. Compared to the first inter-cut regions, the width of the second and third inter-cut regions is narrower. Compared to two adjacent first cuts or two adjacent subsequent cuts, any subsequent cut is closer to its adjacent first cut and more likely to interact, making it easier for cracks to propagate at the cut. This invention reduces the difficulty of wafer stripping by eliminating the need to increase the laser source power to increase the energy of the laser acting on the cuts and by eliminating the need to repeatedly move the laser focus along the cuts. Because it eliminates the need to increase the laser source power, this invention can thin the wafer's loss layer, thereby reducing wafer production costs. Furthermore, because it eliminates the need to repeatedly move the laser focus along the cuts, this invention reduces the number of times the laser focus moves along the cuts, decreasing the probability of defects inside the wafer and thus improving wafer production yield.

[0009] In some implementations, each second cut equally divides the first inter-cut region, and the second and third inter-cut regions are of equal width.

[0010] In some implementations...

[0011] Step A includes:

[0012] A1. Control the laser source to move relative to the wafer along the cutting direction, so that the laser focus moves relative to the wafer along the cutting direction;

[0013] A2. Control the laser source to move relative to the wafer along the moving direction perpendicular to the cutting direction and the wafer axis, so that the laser focus position is translated relative to the wafer along the moving direction. The stroke of the moving motion is equal to the single-wheel cutting row spacing and equal to the width of the first inter-mark region.

[0014] A3. Repeat steps A1 and A2 several times;

[0015] The laser stealth-based wafer fabrication method also includes:

[0016] B. Control the laser source to move relative to the wafer in a misalignment direction perpendicular to the cutting direction and the wafer axis, so that the laser focus position is translated relative to the wafer in the cutting direction. The stroke of the misalignment movement is half of the single-wheel cutting row distance.

[0017] Step C includes:

[0018] C1. Control the laser source to move relative to the wafer along the cutting direction, so that the laser focus moves relative to the wafer along the cutting direction;

[0019] C2. Control the laser source to move relative to the wafer along the moving direction perpendicular to the cutting direction and the wafer axis, so that the laser focus position is translated relative to the wafer along the moving direction. The stroke of the moving motion is equal to the single-wheel cutting row spacing and equal to the width of the first inter-mark region.

[0020] C3. Repeat steps C1 and C2 several times.

[0021] In some embodiments, the laser source moves relative to the wafer along the cutting direction at a speed between 150 mm / s and 250 mm / s.

[0022] In some implementations, the single-wheel cut line spacing is 500. The displacement motion has a range of 250. .

[0023] In some implementations, steps A and C are performed over the entire back surface of the wafer;

[0024] The laser stealth-based wafer fabrication method also includes:

[0025] D. Perform compensating laser stealth processing in the low-transmittance area on the back of the wafer to obtain multiple parallel and spaced compensating cuts in the wafer. The multiple compensating cuts correspond one-to-one with the multiple subsequent cuts in the low-transmittance area; or, the multiple compensating cuts correspond one-to-one with the multiple first cuts in the low-transmittance area.

[0026] In some embodiments, the width of the low light transmittance range along the length of the cut surface is X1, the diameter of the wafer is X, and the width of the highest light transmittance range of the wafer is Y, where X1 = X - (2Y ± 10). .

[0027] In some implementations, the laser source is controlled to configure the power P across the entire domain. 全 Generate laser light and perform steps A and C, 40W ≤ P 全 ≤50W.

[0028] In some implementations, the laser source is controlled to compensate for the configuration power P. 补 Generate laser light and perform step D, 30W ≤ P 补 ≤40W.

[0029] In some embodiments, the laser stealth-based wafer fabrication method further includes:

[0030] S. Using the back side of the wafer as the laser incident surface, the laser focal point is positioned within the wafer, and the distance between the laser focal point and the back side of the wafer is controlled to be between 150°. ~250 .

[0031] In some implementations, step A is performed first to obtain N first cuts and N-1 inter-cut regions, and then step C is performed, where N is the expected number of first cuts. Attached Figure Description

[0032] Figure 1 This is a schematic diagram showing the distribution of wafer cut marks obtained after wafer processing using the laser stealth-based wafer processing method of the present invention.

[0033] Figure 2 This is a schematic diagram showing the distribution of the first cut marks obtained after processing a wafer using the laser stealth-based wafer processing method of the present invention.

[0034] Figure 3 This is a schematic diagram showing the distribution of the second cut marks obtained after processing a wafer using the laser stealth-based wafer processing method of the present invention.

[0035] Figure 4 This is a schematic diagram showing the distribution of compensation marks obtained after processing a wafer using the laser stealth-based wafer processing method of the present invention.

[0036] Figure 5 This is a schematic diagram illustrating the generation of nicks in the laser stealth-based wafer fabrication method of the present invention;

[0037] Figure 6 This is a schematic diagram of the resistivity distribution in a wafer.

[0038] Reference numerals: 100, wafer; 101, carbon surface; 102, low transmittance area; 103, silicon surface; 104, dicing surface; 20, first dicing mark; 30, first dicing interval region; 40, second dicing mark; 51, second dicing interval region; 52, third dicing interval region; 60, compensation dicing mark; 70, laser beam; 71, laser focus. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0041] This invention provides a wafer processing method based on laser stealth. This method utilizes laser irradiation of the interior of a wafer 100 to modify the irradiated area and generate kerfs. These kerfs facilitate subsequent wafer stripping and slicing. To improve modification efficiency and kerf quality, the laser enters through the carbon surface 101 of the wafer 100, modifying the location of the laser focus 71 and generating a light spot. As the laser focus 71 moves, a series of light spots generated within the wafer 100 are arranged along the trajectory of the laser focus 71, thus forming kerfs. The moving speed of the laser focus 71 is called the cutting speed of the laser stealth processing. The lower the cutting speed, the denser the light spots arranged along the trajectory of the laser focus 71, the better the cutting effect, and the easier it is to strip the wafer 100.

[0042] Because laser stealth involves thermal expansion of the wafer 100, excessively low cutting speeds will exacerbate this thermal expansion. Existing laser stealth processing technologies result in wafers 100 with low yield, a high probability of internal defects, large damaged layer thickness, and high production costs. Factors contributing to internal defects include cutting power and the number of cuts. Cutting power refers to the power of the laser source used to generate the laser beam 70, and the number of cuts refers to the number of times the laser focus 71 moves along the trajectory corresponding to the cut during the process of obtaining a single cut. Cutting power is a factor contributing to the large damaged layer thickness of the wafer 100. Although the industry recognizes that reducing cutting power and the number of cuts is beneficial for improving yield, reducing internal defects in the wafer 100, and controlling and reducing the damaged layer thickness, lower cutting power and fewer cuts can prevent the cut from expanding to the point required for slicing, making it more difficult to peel and slice the wafer 100.

[0043] Therefore, the wafer fabrication method based on laser stealth of the present invention includes the following steps:

[0044] Step A: Perform the first round of laser stealth processing to obtain multiple first cuts 20 and multiple first cut regions 30 that are distributed side by side and spaced apart within the wafer 100;

[0045] Step C: Perform subsequent laser stealth processing to obtain multiple parallel and spaced subsequent cuts and multiple subsequent cut regions within the wafer 100.

[0046] The subsequent cuts include multiple second cuts 40 located within multiple first inter-cut regions 30. The subsequent inter-cut regions include multiple second inter-cut regions 51 and third inter-cut regions 52. Each second cut 40 divides the first inter-cut region 30 into a second inter-cut region 51 and a third inter-cut region 52.

[0047] After implementing step A, the multiple first cuts 20 and multiple inter-first cut regions 30 obtained are as follows: Figure 2As shown; after implementing step C, the multiple second cuts 40, multiple second inter-cut regions 51, and multiple third inter-cut regions 52 obtained are as follows. Figure 1 and Figure 3 As shown; Figure 1 As shown, multiple first cuts 20 and multiple second cuts 40 are arranged side by side and alternately spaced. Each second cut 40 divides the first cut area 30 in which it is located into a second cut area 51 and a third cut area 52. The second cut area 51 and the third cut area 52 in each first cut area 30 are located on both sides of the second cut 40 in the first cut area 30.

[0048] Both the first cut 20 and the second cut 40 are used to propagate cracks. After the wafer 100 is peeled and slid to form multiple strip-shaped slitting products, multiple second inter-crack regions 51 and multiple third inter-crack regions 52 correspond to multiple strip-shaped slitting products respectively. The fracture surface of each strip-shaped slitting product during the peeling process is formed by cracks propagated from the first cut 20 and the second cut 40. The multiple strip-shaped slitting products can be divided into two groups. In one group of strip-shaped slitting products, the width of the strip-shaped slitting products is the width of the second inter-crack region 51. In the other group of strip-shaped slitting products, the width of the strip-shaped slitting products is the width of the third inter-crack region 52.

[0049] The width of each first inter-mark region 30 is equal to the distance between two adjacent first cuts 20 that define the first inter-mark region 30; for the same first inter-mark region 30, the width of its second inter-mark region 51 is equal to the distance from the second cut 40 to the first cut 20 on one side of the second cut 40, and the width of its third inter-mark region 52 is equal to the distance from the second cut 40 to the first cut 20 on the other side of the second cut 40.

[0050] Optionally, see Figures 1-3 Multiple first cuts 20 are arranged parallel to each other and at equal intervals, and multiple second cuts 40 are arranged parallel to each other and at equal intervals. The number of first inter-cut regions 30, second inter-cut regions 51, and third inter-cut regions 52 are all equal, that is, the sum of the number of second inter-cut regions 51 and third inter-cut regions 52 is twice the number of first inter-cut regions 30. With this configuration, the total number of multiple strip-shaped slice products obtained after the wafer 100 is peeled and sliced ​​is equal to the sum of the number of second inter-cut regions 51 and third inter-cut regions 52, and each strip-shaped slice product has a structure with a uniform width.

[0051] In some embodiments, each second cut 40 equally divides the first inter-cut region 30, and the second inter-cut region 51 and the third inter-cut region 52 are of equal width. With this configuration, the multiple strip-shaped wafer products obtained after wafer 100 is peeled and slab-divided have a uniform width. The width of each strip-shaped wafer product is equal to the width of each second inter-cut region 51 and also equal to the width of each third inter-cut region 52. The width of each first inter-cut region 30 is twice the width of each strip-shaped wafer product. This configuration ensures that cracks propagating from the first cut 20 and cracks propagating from the second cut 40 meet the requirements for easy peeling. In other embodiments, the second inter-cut region 51 and the third inter-cut region 52 may also be of non-equal width.

[0052] In some implementations, step A includes:

[0053] Step A1: Control the laser source to move relative to the wafer 100 along the cutting direction, so that the laser focus 71 translates relative to the wafer 100 along the cutting direction;

[0054] Step A2: Control the laser source to move relative to the wafer 100 along the moving direction perpendicular to the cutting direction and the wafer 100 axis, so that the position of the laser focus 71 is translated relative to the wafer 100 along the moving direction. The stroke of the moving motion is equal to the single-wheel cutting row spacing and equal to the width of the first inter-mark region 30.

[0055] Step A3: Repeat steps A1 and A2 several times;

[0056] The laser stealth-based wafer fabrication method also includes:

[0057] Step B: Control the laser source to move relative to the wafer 100 in a misalignment direction perpendicular to the cutting direction and the wafer 100 axis, so that the position of the laser focus 71 is translated relative to the wafer 100 in the moving direction. The stroke of the misalignment movement is half of the single-wheel cutting row distance.

[0058] Step C includes:

[0059] Step C1: Control the laser source to move relative to the wafer 100 along the cutting direction, so that the laser focus 71 is translated relative to the wafer 100 along the cutting direction;

[0060] Step C2: Control the laser source to move relative to the wafer 100 along the moving direction perpendicular to the cutting direction and the wafer 100 axis, so that the position of the laser focus 71 is translated relative to the wafer 100 along the moving direction. The stroke of the moving motion is equal to the single-wheel cutting row spacing and equal to the width of the first inter-mark region 30.

[0061] Step C3: Repeat steps C1 and C2 several times.

[0062] The cutting direction and the tracing direction are both perpendicular to the axial direction of the wafer 100. The extension direction of the first cut 20, the second cut 40, and all subsequent cuts except the second cut 40 are all in the cutting direction, that is, the first cut 20, the second cut 40, and all subsequent cuts except the second cut 40 are parallel to each other, and each cut is composed of several light spots arranged in a straight line along the cutting direction. Optionally, in some embodiments, the cutting surface 104 of the wafer 100 is parallel to the axial direction of the wafer 100, the cutting direction is perpendicular to the cutting surface 104, the tracing direction is parallel to the cutting surface 104, and the first cut 20, the second cut 40, and all subsequent cuts except the second cut 40 are perpendicular to the cutting surface 104. See reference. Figures 1-3 After removing the bow-shaped mechanism from the wafer 100, the remaining cross-section forms the cutting surface 104.

[0063] Each execution of step A1 yields a first slit 20, and step A2 prepares for obtaining the next first slit 20; each execution of step C1 yields a second slit 40, and step C2 prepares for obtaining the next second slit 40. The row spacing of a single round of slits is equal to the distance between any two adjacent first slits 20, and also equal to the distance between any two adjacent second slits 40. By repeating steps A1 and A2 several times, multiple first slits 20 arranged side by side can be generated within the wafer 100. By repeating steps C1 and C2 several times, multiple second slits 40 arranged side by side can be generated within the wafer 100. Executing step B before step C ensures that the multiple subsequent slits obtained by the subsequent laser stealth processing do not overlap with the multiple first slits 20 obtained by the first round of laser stealth processing. Therefore, the second slits 40 do not overlap with the first slits 20, and the multiple second slits 40 fall within the multiple first slit regions 30. The staggered motion stroke in control step B is half the single wheel cut line spacing, which can achieve multiple second cuts 40 to equally divide multiple first cut inter-regions 30.

[0064] Furthermore, in some embodiments, the laser source moves relative to the wafer 100 at a speed between 150 mm / s and 250 mm / s along the kerf direction, that is, the laser focus 71 moves within the wafer 100 at a speed between 150 mm / s and 250 mm / s. With this configuration, compared to the existing laser stealth processing which uses a cutting speed of 400 mm / s or higher, this embodiment significantly reduces the cutting speed of laser stealth processing. Moreover, the present invention selects a larger single-round kerf spacing when performing single-round laser stealth processing, thus making it less likely for the wafer 100 to warp when cutting at a lower speed. The reason why the warping of the wafer 100 in the existing laser stealth process is aggravated as the cutting speed decreases is mainly because the single-round slit spacing selected during single-round laser stealth processing is too small. The thermal expansion of the wafer 100 and the dense arrangement of laser spots on the slit cause severe thermal deformation of the wafer 100. In addition, in order to facilitate the expansion of cracks at the slit, the number of cuts is increased so that the laser focus 71 moves along the slit multiple times, which further aggravates the warping of the wafer 100.

[0065] For example, in order to obtain 250 after wafer 100 is stripped and diced. For strip-shaped products of varying widths, existing laser stealth processes select 250 when performing single-round laser stealth processing. The single-wheel cutting row spacing, and in order to facilitate the expansion of cracks at the cutting marks, the number of cuts is at least 5;

[0066] In order to obtain a width of 250 In one embodiment of the present invention, the strip-shaped product has a single-wheel cut spacing of 500 and a misalignment motion stroke of 250. That is, when performing steps A and C, the width of each first inter-mark region 30 is 500. The distance between any two adjacent first cuts 20 is 500. The distance between any two adjacent second cuts 40 is 500. The width of each second inter-mark region 51 and the width of each third inter-mark region 52 are both 250. .

[0067] With this configuration, the row spacing of the single-round cuts during the first round of laser stealth processing and subsequent rounds of stealth processing is doubled compared to the existing single-round cut row spacing, thus mitigating the impact of the single-round cut row spacing on the warping of the wafer 100; the distance between any first cut 20 and its adjacent second cut 40 remains 250. This is consistent with the slit spacing obtained by existing laser stealth technology. The interaction between the first slit 20 and the second slit 40 to expand the crack is easy and does not require increasing the number of cuts. When generating a first slit 20, the laser focus 71 only needs to move along the first slit 20 once, and when generating a second slit 40, the laser focus 71 only needs to move along the second slit 40 once. This avoids the influence of the number of cuts on the warping of the wafer 100.

[0068] Furthermore, in some embodiments, steps A and C are performed over the entire back surface of the wafer 100. The back surface of the wafer 100 is the carbon surface 101 of the wafer 100, and all locations on the carbon surface 101 can be used as locations for laser penetration into the wafer 100, such as... Figures 1-3 Both ends of any first cut 20 extend to the circular outline of the carbon surface 101, and both ends of any second cut 40 also extend to the circular outline of the carbon surface 101. This arrangement ensures that the first cut 20 and subsequent cuts can extend into cracks that reach the outer peripheral wall of the wafer 100, so that the wafer 100 can be peeled and slicing to obtain qualified strip-shaped sliced ​​products with smooth edges.

[0069] Furthermore, laser stealth-based wafer fabrication methods also include:

[0070] Step D: Perform compensating laser stealth processing within the low-transmittance area 102 on the back side of the wafer 100, obtaining multiple parallel and spaced compensating cuts 60 within the wafer 100. These multiple compensating cuts 60 correspond one-to-one with multiple subsequent cuts within the low-transmittance area 102; or, the multiple compensating cuts 60 correspond one-to-one with multiple first cuts 20 within the low-transmittance area 102. During the process of obtaining the compensating cuts 60, the laser source is also controlled to move relative to the wafer 100 along a cutting direction perpendicular to the cutting direction and the wafer 100 axis. The first cut 20, all subsequent cuts including the second cut 40, and the compensating cuts 60 extend along the cutting direction.

[0071] With this setup, step D enables the laser to perform compensatory cutting on the wafer 100, making it easier for the first cut 20 or subsequent cuts to propagate cracks. The effect of compensatory cutting is particularly significant for wafers 100 with larger diameters, as it can fully modify the first cut 20 or subsequent cuts within the low-transmittance range 102 of the wafer 100, reducing the mechanical energy required for crack propagation. When the diameter of the wafer 100 is small, step D can be performed or skipped. Compared to large-diameter wafers 100, smaller-diameter wafers 100 have a smaller low-transmittance range 102, making it easier for the first cut 20 and subsequent cuts to propagate cracks, requiring less mechanical energy, and thus reducing the need to generate compensatory cuts 60 through compensatory cutting.

[0072] The low-transmittance range 102 is specifically a cylindrical spatial region. The low-transmittance range 102 is essentially coaxial with the entire wafer 100. If viewed from above with the carbon surface 101 directly opposite the wafer 100, the low-transmittance range 102 is roughly circular, with its center being the center of the carbon surface 101. The low-transmittance range 102 has even lower transmittance than the area outside it. Generally, the transmittance within the wafer 100 is strongly correlated with its resistivity. (See [reference needed]). Figure 6 Within chip 100, there is a range of relatively low resistivity, which overlaps with the low transmittance range 102. Figure 6 The colors yellow, light green, dark green, and blue represent the distribution ranges of resistivity, from highest to second highest, lowest to lowest, respectively. The low light transmittance range 102 is roughly within the dark green range.

[0073] See Figure 4 , Figure 4 This illustrates the multiple compensation cuts 60 generated within the low light transmittance range 102 through step D. Figure 4 The circular region encompassing the low-transmittance range 102 is coaxial with the end face of the wafer 100, and the diameter of the circular region encompassing the low-transmittance range 102 is smaller than the diameter of the wafer 100. The distance between any two adjacent compensation nicks 60 is equal to the aforementioned single-round nick row spacing, or equal to two, three, or more integer multiples of the single-round nick row spacing. The number of compensation nicks 60 does not exceed the number of the first nicks 20, nor does it exceed the number of subsequent nicks. Optionally, as... Figure 4 The distribution span of the compensation cut 60 along the length of the cutting surface 104 is X1, the diameter of the wafer 100 is X, the maximum light transmission range width of the wafer 100 is Y, and X1 = X - (2Y ± 10). The length direction of the cutting surface 104 is perpendicular to the axial direction and the cutting direction of the wafer 100. The highest light transmittance range of the wafer 100 is located between the edge of the end face of the wafer 100 and the edge of the circular region including the low light transmittance range 102. The width Y of the highest light transmittance range of the wafer 100 is equal to the difference between the diameter of the wafer 100 and the diameter of the circular region including the low light transmittance range 102.

[0074] Furthermore, in some implementations, the laser source is controlled to configure the power P across the entire domain. 全 Generate laser light and perform steps A and C, 40W ≤ P 全 ≤50W; control the laser source to compensate for the configuration power P 补 Generate laser light and perform step D, 30W ≤ P 补 ≤40W. This setting reduces the cutting power of laser stealth processing, and the resulting cut marks make it relatively easy to peel off and slice the wafer 100.

[0075] Achieving 250 using existing laser stealth technology For the sliced ​​product of a certain width, the laser source needs to generate laser power of 60-80W. Each time a cut is generated, the laser focus 71 needs to move multiple times along the cut to achieve multiple rounds of repeated cutting. Only in this way can the cut expand to create cracks that meet the requirements for sliced ​​production. However, since the single-round cut spacing is 250mm... The wafer 100 exhibits significant thermal expansion and severe warping.

[0076] The laser stealth-based wafer fabrication method of the present invention yields 250 The width of the segmented product is controlled by setting the single-round cut row spacing to 500 during the first round of laser stealth processing to generate the first cut 20. During the generation of the second cut 40, the single-wheel cut row spacing is controlled to be 500. The warping of wafer 100 is not obvious, and the deformation of wafer 100 is alleviated and improved. The distance between the first cut 20 and the second cut 40 is 250. Less than 500 The single-wheel cutting row spacing, the first cut 20 and the second cut 40 can easily propagate cracks through interaction, reducing the mechanical energy required for crack propagation. Therefore, it is no longer necessary to repeatedly cut the wafer 100 with a high-power laser, thus allowing the power of the laser source to be reduced and the number of times the laser focus 71 moves along the cut to be reduced.

[0077] In some embodiments, the wafer fabrication method based on laser stealth also includes:

[0078] Step S: Using the back surface of wafer 100 as the laser incident surface, ensure the laser focus 71 falls within wafer 100, and control the distance between the laser focus 71 and the back surface of wafer 100 to be between 150 mm. ~250 .

[0079] See Figure 5 The carbon surface 101 and silicon surface 103 of the wafer 100 are the two end faces of the wafer 100, respectively. The carbon surface 101 is the back surface of the wafer 100 and serves as the incident surface for the laser. The laser focus 71 is located at... Figure 5 The height position indicated by the dashed line acts on the interior of the wafer 100, thereby generating a light spot at the height position indicated by the dashed line, which in turn produces a cut. The distance from the laser focus 71 to the carbon surface 101 is represented by d, 150. ≤d≤250 .

[0080] In some implementations, step A is performed first to obtain N first cuts 20 and N-1 inter-cut regions 30, and then step C is performed, where N is the expected number of first cuts 20. In other words, step C is performed to obtain the second cuts 40 only after the first round of laser stealth processing is completed and all the required first cuts 20 and inter-cut regions 30 are obtained, rather than obtaining a portion of the first cuts 20, performing step C to obtain a portion of the second cuts 40, and then performing step A to obtain the remaining first cuts 20.

[0081] The technical features of the above-described embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] Those skilled in the art should recognize that the above embodiments are merely illustrative of the present invention and are not intended to limit the present invention. Any appropriate changes and variations made to the above embodiments within the essential spirit of the present invention fall within the scope of protection claimed by the present invention.

Claims

1. A wafer fabrication method based on laser stealth, characterized in that, include: A. The first round of laser stealth processing was carried out to obtain multiple first cuts (20) and multiple inter-cut regions (30) in the wafer (100) with parallel spacing. C. Perform subsequent laser stealth processing to obtain multiple parallel and spaced subsequent cuts and multiple subsequent cut regions within the wafer (100). The subsequent cuts include multiple second cuts (40) located in multiple first inter-cut regions (30), and the subsequent inter-cut regions include multiple second inter-cut regions (51) and third inter-cut regions (52). Each second cut (40) divides the first inter-cut region (30) into a second inter-cut region (51) and a third inter-cut region (52). First, execute step A to obtain N first cuts (20) and N-1 inter-cut regions (30), and then execute step C, where N is the expected number of first cuts (20).

2. The wafer fabrication method based on laser stealth as described in claim 1, characterized in that, Each second cut (40) equally divides the first inter-cut region (30), and the second inter-cut region (51) and the third inter-cut region (52) are of equal width.

3. The wafer fabrication method based on laser stealth as described in claim 2, characterized in that, Step A includes: A1. Control the laser source to make a cutting motion relative to the wafer (100) along the cutting direction, so that the laser focus (71) translates relative to the wafer (100) along the cutting direction; A2. Control the laser source to move relative to the wafer (100) along the moving direction perpendicular to the cutting direction and the wafer (100) axis, so that the position of the laser focus (71) is translated relative to the wafer (100) along the moving direction. The stroke of the moving motion is equal to the single-wheel cutting row spacing and equal to the width of the first inter-mark region (30). A3. Repeat steps A1 and A2 several times; The laser stealth-based wafer fabrication method also includes: B. Control the laser source to move relative to the wafer (100) in a misalignment direction perpendicular to the cutting direction and the wafer (100) axis, so that the position of the laser focus (71) is translated relative to the wafer (100) in the cutting direction. The stroke of the misalignment movement is half of the single-wheel cutting row distance. Step C includes: C1. Control the laser source to make a cutting motion relative to the wafer (100) along the cutting direction, so that the laser focus (71) translates relative to the wafer (100) along the cutting direction; C2. Control the laser source to move relative to the wafer (100) along the moving direction perpendicular to the cutting direction and the wafer (100) axis, so that the position of the laser focus (71) is translated relative to the wafer (100) along the moving direction. The stroke of the moving motion is equal to the single-wheel cutting row spacing and equal to the width of the first inter-mark region (30). C3. Repeat steps C1 and C2 several times.

4. The wafer fabrication method based on laser stealth as described in claim 3, characterized in that, The laser source moves relative to the wafer (100) along the cutting direction at a speed between 150 mm / s and 250 mm / s.

5. The wafer fabrication method based on laser stealth as described in claim 3, characterized in that, The single-wheel cut line spacing is 500. The displacement motion has a range of 250. .

6. The wafer fabrication method based on laser stealth as described in claim 1, characterized in that, Steps A and C are performed over the entire back surface of the wafer (100); The laser stealth-based wafer fabrication method also includes: D. Compensation laser stealth processing is performed in the low-transmittance area (102) on the back of the wafer (100) to obtain multiple parallel and spaced compensation cuts (60) in the wafer (100). Among them, multiple compensation cuts (60) correspond one-to-one with multiple subsequent cuts in the low light transmittance range (102); or, multiple compensation cuts (60) correspond one-to-one with multiple first cuts (20) in the low light transmittance range (102).

7. The wafer fabrication method based on laser stealth as described in claim 6, characterized in that, The width of the low light transmittance range (102) along the length of the cut surface (104) is X1, the diameter of the wafer (100) is X, the width of the highest light transmittance range of the wafer (100) is Y, and X1 = X - (2Y ± 10). .

8. The wafer fabrication method based on laser stealth as described in claim 6, characterized in that, Control the laser source to configure the power P over the entire domain 全 Generate laser light and perform steps A and C, 40W ≤ P 全 ≤50W.

9. The wafer fabrication method based on laser stealth as described in claim 8, characterized in that, Control the laser source to compensate for the configuration power P 补 Generate laser light and perform step D, 30W ≤ P 补 ≤40W.

10. The wafer fabrication method based on laser stealth as described in any one of claims 1 to 9, characterized in that, The laser stealth-based wafer fabrication method also includes: Step S: Using the back surface of the wafer (100) as the laser incident surface, the laser focus (71) is positioned within the wafer (100), and the distance between the laser focus (71) and the back surface of the wafer (100) is controlled to be between 150°. ~250 .

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