Floating-point-free pseudo code generator implementation method and device, equipment and medium
By using the combination of preset accumulator and counter in the pseudocode generator, floating-point pseudocode generation is achieved, which solves the problem of floating-point calculation complexity of the pseudocode generator processing accuracy requirements on the FPGA, and improves the tracking efficiency and hardware resource utilization of the receiver.
Patent Information
- Application Number
- CN202410006243.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-02
- Publication Date
- 2025-07-04
AI Technical Summary
The existing pseudocode generator implementation methods have insufficient flexibility and hardware resource consumption, especially on FPGA processing floating point calculations that require accuracy, which increases the computational complexity and is difficult to compatible with multiple signal positioning.
The implementation method of pseudocode generator without floating point is adopted. By prestoring the pseudocode sampling period in read-only memory, using preset accumulators and counters to control the count bits when each pulse clock arrives, determining the target address count bits, realizing pseudocode generation and avoiding floating point operations.
It reduces the complexity of tracking loop computing, alleviates the use of FPGA hardware resources, and improves the tracking efficiency of the receiver.
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Figure CN120254905A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of baseband signal processing research of global satellite navigation system receivers, and particularly relates to a method, device, equipment and medium for implementing a pseudo-code generator without floating point. Background Art
[0002] In the process of signal processing of satellite navigation signal receivers, pseudo-codes play a very important role. The pseudo-code is also known as the Pseudo-Random Noise (PRN) code, also known as the spreading code. At the satellite end, data is spread by modulating a spreading code with a modulation rate much higher than the data rate. Since the pseudo-code has good autocorrelation, the receiver despreads the received signal by matching with the pseudo-code. Despreading requires generating a pseudo-code corresponding to the signal locally, so the pseudo-code generator is an essential part of the spread-spectrum receiver.
[0003] Currently, there are mainly four implementation methods for pseudo-code generators in receivers: the generator method based on pseudo-code generation logic, the generator method based on ROM (Read-Only Memory) storage, the generator method based on RAM (Random Access Memory) storage, and the generator method based on shift registers. The first method performs various permutations and combinations of the media for pseudo-code generation and storage. If the pseudo-code is generated on an FPGA (Field Programmable Gate Array), the hardware resources consumed are very small, but the design difficulty of the pseudo-code generator is increased, and different navigation signals require different generators, with poor compatibility; the second method has great advantages for non-configurable signal processing channels, but lacks flexibility. When multiple signal positioning needs to be compatible, the required ROM storage capacity is very large; the third method requires external devices such as DSP (Digital Signal Process) or ARM (Advanced RISC Machines) CPU (Central Processing Unit) processors, which is a relatively flexible processing method with a moderate storage capacity, but reliable transmission needs to be established in cooperation with the DSP, and it is not applicable in some scenarios with high security requirements such as aviation; the fourth method has a relatively high degree of flexibility, but the required hardware resources are greater than those of the second method. Therefore, in practical applications, the implementation methods of pseudo-code generators are not ideal. Summary of the Invention
[0004] In view of this, the object of the present invention is to provide a method, device, equipment and medium for implementing a floating-point-free pseudo-code generator, which can improve the pseudo-code generator method based on ROM storage and provide a pseudo-code generator without floating-point calculation. The specific scheme is as follows:
[0005] In a first aspect, the present application discloses a method for implementing a floating-point-free pseudo-code generator, including:
[0006] Deposit the pseudo-code of the corresponding multiple of the sampling period into the read-only memory in advance according to the pseudo-code phase accuracy of the tracking navigation signal;
[0007] Initialize the pseudo-code generator, and based on the initial values of the parameters in the pseudo-code generator after initialization, control the counting bits of the preset counter by using the preset accumulator in the pseudo-code generator when each pulse clock arrives to determine the target addressing counting bits;
[0008] Read the corresponding pseudo-code from the read-only memory according to the target addressing counting bits to obtain the target pseudo-code.
[0009] Optionally, the initialization of the pseudo-code generator includes:
[0010] Obtain the code phase result and the code loop filter result output by the pre-signal processing unit of the pseudo-code generator;
[0011] Initialize the preset accumulator and the preset counter in the pseudo-code generator by using the code phase result and the code loop filter result.
[0012] Optionally, the parameters that need to be initialized in the pseudo-code generator include the initial phase, the initial value of the preset accumulator, the phase control word, the control clock, the number of loop executions of the pseudo-code generator, and the number of whole-cycle chips;
[0013] Correspondingly, the initialization of the pseudo-code generator includes:
[0014] Calculate the frequency control word and the initial values of the leading code, the prompt code, and the lag code corresponding to the preset accumulator and the preset counter respectively based on the parameters.
[0015] Optionally, the step of controlling the counting bits of the preset counter by using the preset accumulator in the pseudo-code generator when each pulse clock arrives to determine the target addressing counting bits includes:
[0016] When each pulse clock arrives, add the initial values of the leading code, the prompt code, and the lag code of the preset accumulator with a frequency control word;
[0017] When the leading code initial value, the timely code initial value, and the lagging code initial value of the preset accumulator overflow, increment the initial value of the corresponding preset counter for the overflowed code by one, and increment the number of loop executions by one;
[0018] Determine whether the preset counter has traversed the corresponding multiple of the sampling period according to the current number of loop executions;
[0019] If the preset counter has traversed the corresponding multiple of the sampling period, stop the operation of the pseudo-code generator and output the target addressing count bits;
[0020] If the preset counter has not traversed the corresponding multiple of the sampling period, jump to the step of adding the frequency control word to the leading code initial value, the timely code initial value, and the lagging code initial value of the preset accumulator when each pulse clock arrives until the corresponding multiple of the sampling period is traversed to obtain the target addressing count bits.
[0021] Optionally, when the tracking and navigation signal is a Global Positioning System signal in the L1 band, the determining whether the preset counter has traversed the corresponding multiple of the sampling period according to the current number of loop executions includes:
[0022] Determine whether the current number of loop executions is greater than 1023×n; n corresponds to n times the sampling period;
[0023] If the current number of loop executions is greater than 1023×n, it is determined that the preset counter has traversed the corresponding multiple of the sampling period;
[0024] If the current number of loop executions is not greater than 1023×n, it is determined that the preset counter has not traversed the corresponding multiple of the sampling period.
[0025] Optionally, the method for implementing the floating-point-free pseudo-code generator further includes:
[0026] Determine whether the external control signal is input as a valid signal;
[0027] When the external control signal is input as a valid signal, re-execute the step of initializing the pseudo-code generator.
[0028] Optionally, after reading the corresponding pseudo-code from the read-only memory according to the target addressing count bits to obtain the target pseudo-code, it further includes:
[0029] Perform validity verification based on a field-programmable gate array.
[0030] In a second aspect, the present application discloses a device for implementing a floating-point-free pseudo-code generator, including:
[0031] A pseudo-code storage module for pre-storing pseudo-codes of a corresponding multiple of the sampling period into a read-only memory according to the pseudo-code phase accuracy of the tracking navigation signal;
[0032] An address output module for initializing a pseudo-code generator and, based on the initial values of the parameters in the pseudo-code generator after initialization, controlling the counting bits of a preset counter by using a preset accumulator in the pseudo-code generator when each pulse clock arrives to determine the target addressing counting bits;
[0033] A pseudo-code determination module for reading a corresponding pseudo-code from the read-only memory according to the target addressing counting bits to obtain a target pseudo-code.
[0034] In a third aspect, the present application discloses an electronic device, which includes a processor and a memory; wherein, the memory is used for storing a computer program, and the computer program is loaded and executed by the processor to implement the method for implementing a floating-point-free pseudo-code generator as described above.
[0035] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the method for implementing a floating-point-free pseudo-code generator as described above.
[0036] The present application provides a method for implementing a floating-point-free pseudo-code generator, including: pre-storing pseudo-codes of a corresponding multiple of the sampling period into a read-only memory according to the pseudo-code phase accuracy of the tracking navigation signal; initializing a pseudo-code generator and, based on the initial values of the parameters in the pseudo-code generator after initialization, controlling the counting bits of a preset counter by using a preset accumulator in the pseudo-code generator when each pulse clock arrives to determine the target addressing counting bits; reading a corresponding pseudo-code from the read-only memory according to the target addressing counting bits to obtain a target pseudo-code. The beneficial technical effects of the present application are as follows: Based on the code generator scheme stored in the ROM, aiming at the characteristic that the FPGA is not good at processing floating-point operations, a pseudo-code generator implementation scheme without calculation is realized. Based on the working principle of the classical ROM-stored pseudo-code generator, that is, the pseudo-code generator is divided into an accumulator and a counter, and the accumulator is used to control the counting bits of the counter, without going through floating-point operations. Under the condition of maintaining the code discrimination accuracy of the tracking loop, the calculation complexity of the tracking loop is reduced, and the occupation of FPGA hardware resources is alleviated, and the tracking efficiency of the receiver is improved.
[0037] In addition, a floating-point-free pseudo-code generator implementation device, equipment and storage medium provided by the present application correspond to the above-mentioned method for implementing a floating-point-free pseudo-code generator, and the effects are the same. Description of the Drawings
[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.
[0039] Figure 1 Flowchart of an implementation method of a floating - point - free pseudo - code generator disclosed in this application;
[0040] Figure 2 Principle block diagram of a pseudo - code generator disclosed in this application;
[0041] Figure 3 Flowchart of a pseudo - code generator disclosed in this application;
[0042] Figure 4 Schematic diagram of an implementation device of a floating - point - free pseudo - code generator disclosed in this application;
[0043] Figure 5 Structural diagram of an electronic device disclosed in this application. Specific implementation manners
[0044] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.
[0045] Currently, among the implementation methods of pseudo - code generators in receivers, the generator method based on ROM storage has great advantages for non - configurable signal processing channels, but it lacks flexibility. If it is necessary to be compatible with multiple signal localizations, the required ROM storage capacity is very large. Combining the characteristics of very little hardware resource consumption for generating pseudo - codes on FPGAs, the FPGA design of a floating - point - free pseudo - code generator is a new idea. However, the pseudo - code phase accuracy for capturing and tracking navigation signals is at least less than 0.5 chip. While FPGAs generally use floating - point calculation methods for calculations with accuracy requirements, it is necessary to increase the definition of calculations during code design, thus increasing the operation complexity.
[0046] Therefore, this application provides an implementation scheme of a floating - point - free pseudo - code generator, which can improve the pseudo - code generator method based on ROM storage. When generating the pseudo - code generator, floating - point calculations are not used, and the pseudo - code sampling rate is changed to change the output of the pseudo - code generator, providing a new design method for the FPGA design of the pseudo - code generator.
[0047] An embodiment of the present invention discloses a method for implementing a pseudo-code generator without floating point. Refer to Figure 1 As shown, the method includes:
[0048] Step S11: According to the pseudo-code phase accuracy of the tracking navigation signal, deposit the pseudo-code of the corresponding multiple of the sampling period into the read-only memory in advance.
[0049] It can be understood that the pseudo-code phase accuracy of capturing and tracking the navigation signal is at least less than 0.5 chip. In order to implement the FPGA design of the pseudo-code generator without floating point, since the FPGA (Field Programmable Gate Array) generally uses floating-point calculation for processing calculations with accuracy requirements, in the embodiments of the present application, according to the pseudo-code phase accuracy of the tracking navigation signal, deposit the pseudo-code of the corresponding multiple of the sampling period into the read-only memory (ROM) in advance. That is, pre-store the pseudo-code of n-fold sampling to adjust the code offset of the addressing offset. In this way, the adjustable accuracy is 1 / n chip. If a 0.5-chip accuracy is required, only need to adjust the pseudo-code sampling rate stored in the ROM to 2 times the code rate, without going through floating-point operations. It can realize the FPGA design of the pseudo-code generator without floating point for the characteristic that the FPGA is not good at processing floating-point operations.
[0050] Step S12: Initialize the pseudo-code generator, and based on the initial values of the parameters in the pseudo-code generator after initialization, control the counting bits of the preset counter with the preset accumulator in the pseudo-code generator when each pulse clock arrives to determine the target addressing counting bits.
[0051] In the embodiments of the present application, the pseudo-code generator is divided into a preset accumulator and a preset counter. The preset accumulator is the phase accumulator cnt1, and the preset counter is the ROM addressing counter cnt2. Initializing the pseudo-code generator includes: obtaining the code phase result and the code loop filter result output by the front-end signal processing unit of the pseudo-code generator; using the code phase result and the code loop filter result to initialize the preset accumulator and the preset counter in the pseudo-code generator.
[0052] In the embodiments of the present application, the front-end signal processing unit of the pseudo-code generator is a front-end module unit in the receiver structure that can input parameters to the pseudo-code generator, including a capture module and a tracking module. The capture module can input the captured code phase result to the pseudo-code generator, and the tracking module can input the obtained code loop filter result to the pseudo-code generator. Initialize cnt1 and cnt2 respectively using the code phase result and the code loop filter result.
[0053] Specifically, the parameters that need to be initialized in the pseudo-code generator include the initial phase, the initial value of the preset accumulator, the phase control word, the control clock, the number of loop executions of the pseudo-code generator, and the number of full-cycle chips.
[0054] Exemplarily, when initializing the pseudo-code generator, the parameters are input respectively: the initial value cnt1 of the preset accumulator (i.e., the input phase value corresponding to the captured code phase result), the initial value cnt2 of the preset counter, the code rate (phase control word) fout, and the PRN number. Given that the captured code phase result is the initial phase input ph, when entering the loop for the first time, the initial value of the preset counter cnt2 = ph, the initial value of the preset accumulator cnt1 = ph, fout = 1.023 MHz (for the generated signal being the GPS L1 C / A signal), and the PRN number is obtained by the capture module.
[0055] In addition, the sampling frequency (control clock) f clk = 62 MHz, the number of bits of the phase accumulator cnt1 is set to L = 20, this value can control the number of loops of the pseudo-code generator, and the frequency adjustment granularity δf = f clk / 2 L = 59.1278 Hz, which is related to the number of full-cycle chips.
[0056] Furthermore, based on the above parameters, calculate the frequency control word and the initial values of the early code, prompt code, and late code corresponding to the preset accumulator and the preset counter respectively.
[0057] Frequency control word Optionally, in a specific implementation manner, when using the carrier loop to assist the code loop to generate a pseudo-code with a superimposed corresponding Doppler frequency, K can be adjusted.
[0058] The preset accumulator and the preset counter of the early, prompt, and late codes are the initial values of the phase accumulator and the ROM addressing counter. The pseudo-code generator outputs codes with three different code phases of early, prompt, and late simultaneously, and the initial values are set as follows:
[0059] Initial value of the early code phase accumulator: cnt_1e = ph;
[0060] Initial value of the prompt code phase accumulator: cnt_1p = ph;
[0061] Initial value of the late code phase accumulator: cnt_1l = ph;
[0062] Initial phase of the early code ROM addressing: cnt_2e = 0;
[0063] Initial phase of the prompt code ROM addressing: cnt_2p = 2^(L - 1);
[0064] Initial phase of the lag code ROM addressing: cnt_2l = 2^L;
[0065] Among them, the subscripts e, p, and l represent lead, prompt, and lag respectively.
[0066] It should be noted that the relationship between the accumulator cnt1 and the code offset: If the externally input code offset obtained by capture is ph, the sampling point under fs sampling has ph_fs = ph * fs / fout, and the corresponding preset accumulator value is cnt1 = rem(ph_fs * K, 2^L); where K is the frequency control word and L is the number of bits of the preset accumulator cnt1. The corresponding preset integer count value is ph. It can be seen that since the phase accumulator in this scheme can be directly set to 0, the smallest unit that the phase can represent is 1 / n chip, and the fractional part of the code offset is controlled by ROM addressing, so there is no need for fractional calculation.
[0067] After the initialization is completed, it enters the loop process of the pseudorandom code generator. The accumulation and overflow of the accumulator phase are controlled by the clock, and at the same time, the accumulation of the ROM addressing count bit of the counter is triggered. In the embodiment of the present application, the DDS (Direct Digital Synthesis) idea is adopted for the accumulator part. The overflow makes the addressing count bit of the integer accumulator increment by 1 to control the count bit of the preset counter, and the final target addressing count bit is determined.
[0068] Step S13: Read the corresponding pseudorandom code from the read-only memory according to the target addressing count bit to obtain the target pseudorandom code.
[0069] In the embodiment of the present application, according to the target addressing count bit output by the preset counter in the pseudorandom code generator, the corresponding pseudorandom code is read from the ROM to obtain the target pseudorandom code. It should be noted that if the external control signal is valid at this time, that is, when the enable signal is pulled high, then cnt1 and cnt2 are re-initialized. At this time, first update the output code frequency fout = fout + Δf; then re-execute the initialization step of the pseudorandom code generator. Where Δf is the output of the first-order code tracking loop, corresponding to the result of the code loop loop filter output by the tracking module.
[0070] Specifically, it is judged whether the external control signal is an effective signal; when the external control signal input is an effective signal, the step of initializing the pseudorandom code generator is re-executed.
[0071] In addition, after reading the corresponding pseudorandom code from the read-only memory according to the target addressing count bit to obtain the target pseudorandom code, it further includes: performing validity verification based on a field-programmable gate array. The method of the pseudorandom code generator based on ROM storage is improved, and the FPGA design of the pseudorandom code generator is realized.
[0072] The present application provides a method for implementing a pseudo-code generator without floating point, including: depositing pseudo-codes of corresponding multiple sampling periods into a read-only memory in advance according to the pseudo-code phase accuracy of a tracking navigation signal; initializing the pseudo-code generator, and based on the initial values of each parameter in the pseudo-code generator after initialization, controlling the counting bits of a preset counter by using a preset accumulator in the pseudo-code generator when each pulse clock arrives to determine the target addressing counting bits; and reading the corresponding pseudo-code from the read-only memory according to the target addressing counting bits to obtain the target pseudo-code. The beneficial technical effects of the present application are as follows: Based on the code generator scheme stored in the ROM, aiming at the characteristic that the FPGA is not good at processing floating point operations, a pseudo-code generator implementation scheme without decimal calculation is realized. Based on the working principle of the pseudo-code generator stored in the classic ROM, that is, the pseudo-code generator is divided into two parts, an accumulator and a counter, and the accumulator is used to control the counting bits of the counter, without going through floating point operations. Under the condition of maintaining the code discrimination accuracy of the tracking loop, the calculation complexity of the tracking loop is reduced, and the occupation of FPGA hardware resources is alleviated, and the tracking efficiency of the receiver is improved.
[0073] In this embodiment, the loop process of the pseudo-code generator is described in detail, and its principle block diagram is as Figure 2 shown. The step of controlling the counting bits of the preset counter by using the preset accumulator in the pseudo-code generator when each pulse clock arrives to determine the target addressing counting bits includes:
[0074] Step 1: When each pulse clock arrives, add a frequency control word to the leading code initial value, the prompt code initial value, and the lag code initial value of the preset accumulator;
[0075] When each pulse clock arrives, the preset accumulator accumulates a frequency control word once, that is
[0076] cnt_1e = cnt_1e + K;
[0077] cnt_1p = cnt_1p + K;
[0078] cnt_1l = cnt_1l + K;
[0079] where K is the frequency control word.
[0080] Step 2: When the leading code initial value, the prompt code initial value, and the lag code initial value of the preset accumulator overflow, add 1 to the initial value of the corresponding preset counter of the overflowing code, and add 1 to the number of loop executions;
[0081] When cnt_1e / cnt_1p / cnt_1l overflows, it means the end of a chip time. At this time, if a certain code overflows, the corresponding counter will be increased by 1, that is:
[0082] cnt_2e = cnt_2e + 1;
[0083] cnt_2p = cnt_2p + 1;
[0084] cnt_2l = cnt_2l + 1;
[0085] At the same time, the loop count T is incremented by 1: T = T + 1.
[0086] Step 3: Determine whether the preset counter has traversed the corresponding multiple of the sampling period according to the current loop execution count;
[0087] Step 4: If the preset counter has traversed the corresponding multiple of the sampling period, stop the operation of the pseudo-code generator and output the target addressing count bits;
[0088] Step 5: If the preset counter has not traversed the corresponding multiple of the sampling period, jump to the step of adding the leading code initial value, timely code initial value, and lagging code initial value of the preset accumulator by one frequency control word when each pulse clock arrives until the corresponding multiple of the sampling period is traversed to obtain the target addressing count bits.
[0089] When cnt_2e / cnt_2p / cnt_2l traverses the entire pseudo-code period, that is, after n times the sampling period, stop the operation of the pseudo-code generator; otherwise, return to Step 1 to continue running the pseudo-code generator.
[0090] In a specific embodiment, when the tracking and navigation signal is a Global Positioning System (GPS) signal in the L1 band, determining whether the preset counter has traversed the corresponding multiple of the sampling period according to the current loop execution count includes: determining whether the current loop execution count is greater than 1023×n; n corresponds to n times the sampling period; if the current loop execution count is greater than 1023×n, it is determined that the preset counter has traversed the corresponding multiple of the sampling period; if the current loop execution count is not greater than 1023×n, it is determined that the preset counter has not traversed the corresponding multiple of the sampling period. That is, taking GPS L1 as an example, determine whether T > 1023×n, and 1023×n is n times the sampling period of the GPS L1 C / A code.
[0091] As Figure 3 shown is the overall flowchart implemented based on the above steps. Among them, for the more specific working process of the above steps, reference can be made to the corresponding content disclosed in the previous steps, and details will not be elaborated here.
[0092] Correspondingly, the embodiment of the present application also discloses a non-floating-point pseudo-code generator implementation device. Refer to Figure 4 As shown in
[0093] A pseudo-code storage module 11, configured to pre-store pseudo-codes of a corresponding multiple of sampling periods into a read-only memory according to the pseudo-code phase accuracy of the tracking navigation signal;
[0094] An address output module 12, configured to initialize the pseudo-code generator, and based on the initial values of the parameters in the pseudo-code generator after initialization, control the counting bits of a preset counter by using a preset accumulator in the pseudo-code generator when each pulse clock arrives, so as to determine the target addressing counting bits;
[0095] A pseudo-code determination module 13, configured to read a corresponding pseudo-code from the read-only memory according to the target addressing counting bits to obtain a target pseudo-code.
[0096] Wherein, for the more specific working processes of the above-mentioned various modules, reference may be made to the corresponding content disclosed in the foregoing embodiments, and details are not described herein again.
[0097] It can be seen that through the above solution of this embodiment, including: pre-storing pseudo-codes of a corresponding multiple of sampling periods into a read-only memory according to the pseudo-code phase accuracy of the tracking navigation signal; initializing the pseudo-code generator, and based on the initial values of the parameters in the pseudo-code generator after initialization, controlling the counting bits of a preset counter by using a preset accumulator in the pseudo-code generator when each pulse clock arrives, so as to determine the target addressing counting bits; reading a corresponding pseudo-code from the read-only memory according to the target addressing counting bits to obtain a target pseudo-code. The beneficial technical effects of the present application are as follows: Based on the code generator scheme stored in the ROM, aiming at the characteristic that the FPGA is not good at processing floating-point operations, a pseudo-code generator implementation scheme without decimal calculation is realized. Based on the working principle of the classic ROM-stored pseudo-code generator, that is, the pseudo-code generator is divided into an accumulator and a counter, and the accumulator is used to control the counting bits of the counter, without going through floating-point operations. Under the condition of maintaining the code discrimination accuracy of the tracking loop, the calculation complexity of the tracking loop is reduced, and the occupation of FPGA hardware resources is alleviated, and the tracking efficiency of the receiver is improved.
[0098] Furthermore, the embodiment of the present application also discloses an electronic device. Figure 5 It is the structural diagram of the electronic device 20 shown according to an exemplary embodiment. The content in the figure cannot be regarded as any limitation on the use scope of the present application.
[0099] Figure 5Schematic diagram of the structure of an electronic device 20 provided by an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the method for implementing a floating-point-free pseudo-code generator disclosed in any of the foregoing embodiments.
[0100] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and no specific limitation is imposed thereon here; the input / output interface 25 is used to obtain external input data or output data to the outside, and the specific interface type thereof can be selected according to specific application requirements, and no specific limitation is made here.
[0101] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, a random access memory, a magnetic disk, an optical disk, etc., and the resources stored thereon can include an operating system 221, a computer program 222, and data 223, etc., and the data 223 can include various kinds of data. The storage method can be temporary storage or permanent storage.
[0102] Among them, the operating system 221 is used to manage and control each hardware device and the computer program 222 on the electronic device 20, and it can be Windows Server, Netware, Unix, Linux, etc. The computer program 222, in addition to including a computer program capable of implementing the method for implementing a floating-point-free pseudo-code generator executed by the electronic device 20 disclosed in any of the foregoing embodiments, may further include a computer program capable of performing other specific tasks.
[0103] Further, the present application also provides an embodiment corresponding to a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements the steps of the method for implementing a floating-point-free pseudo-code generator as described in the above method embodiment. The computer-readable storage medium mentioned here includes medium memories of relatively high speeds such as SRAM (Static Random-Access Memory), SDRAM (Synchronous Dynamic Random-Access Memory), and SSD (Solid State Drives) that can store program codes. Among them, when the computer program is executed by the processor, it implements the foregoing method for implementing a floating-point-free pseudo-code generator. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be repeated here.
[0104] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple. For related parts, reference can be made to the description in the method section.
[0105] The steps of the method for implementing a floating-point-free pseudo-code generator or algorithm described in combination with the embodiments disclosed in this article can be directly implemented by hardware, software modules executed by a processor, or a combination of the two. The software module can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.
[0106] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.
[0107] The above has introduced in detail a method, device, equipment and medium for implementing a floating-point-free pseudo-code generator. In this article, specific examples are used to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation on the present invention.
Claims
1. A method for implementing a floating-point-free pseudo-code generator, characterized in that Including: Storing the pseudo-code of the corresponding multiple sampling periods into the read-only memory in advance according to the pseudo-code phase accuracy of the tracking navigation signal; Initializing the pseudo-code generator, and based on the initial values of the parameters in the pseudo-code generator after initialization, controlling the counting bits of the preset counter by using the preset accumulator in the pseudo-code generator when each pulse clock arrives to determine the target addressing counting bits; Reading the corresponding pseudo-code from the read-only memory according to the target addressing counting bits to obtain the target pseudo-code.
2. The method for implementing a floating-point-free pseudo-code generator according to claim 1, wherein The initializing the pseudo-code generator includes: Obtaining the code phase result and the code loop filter result output by the pre-signal processing unit of the pseudo-code generator; Initializing the preset accumulator and the preset counter in the pseudo-code generator by using the code phase result and the code loop filter result.
3. The method for implementing a floating-point-free pseudo-code generator according to claim 1, wherein The parameters that need to be initialized in the pseudo-code generator include the initial phase, the initial value of the preset accumulator, the phase control word, the control clock, the number of loop executions of the pseudo-code generator, and the number of integral period chips; Correspondingly, the initializing the pseudo-code generator includes: Calculating the frequency control word and the initial values of the leading code, the prompt code, and the lag code corresponding to the preset accumulator and the preset counter respectively based on the parameters.
4. The method for implementing a floating-point-free pseudo-code generator according to claim 3, wherein The controlling the counting bits of the preset counter by using the preset accumulator in the pseudo-code generator when each pulse clock arrives to determine the target addressing counting bits includes: When each pulse clock arrives, adding the initial values of the leading code, the prompt code, and the lag code of the preset accumulator with a frequency control word; When the initial values of the leading code, the prompt code, and the lag code of the preset accumulator overflow, adding one to the initial value of the corresponding preset counter of the overflowed code, and adding one to the number of loop executions; Judging whether the preset counter has traversed the corresponding multiple sampling periods according to the current number of loop executions; If the preset counter has traversed the corresponding multiple sampling periods, stopping the operation of the pseudo-code generator and outputting the target addressing counting bits; If the preset counter has not traversed the corresponding multiple sampling periods, jumping to the step of adding the initial values of the leading code, the prompt code, and the lag code of the preset accumulator with a frequency control word when each pulse clock arrives until the corresponding multiple sampling periods are traversed to obtain the target addressing counting bits.
5. The method for implementing a floating-point-free pseudo-code generator according to claim 4, wherein When the tracking navigation signal is the Global Positioning System signal in the L1 frequency band, the judging whether the preset counter has traversed the corresponding multiple sampling periods according to the current number of loop executions includes: Judging whether the current number of loop executions is greater than 1023×n; n corresponds to n times the sampling period; If the current number of loop executions is greater than 1023×n, it is determined that the preset counter has traversed the corresponding multiple sampling periods; If the current number of loop executions is not greater than 1023×n, it is determined that the preset counter has not traversed the corresponding multiple sampling periods.
6. The method for implementing a floating-point-free pseudo-code generator according to claim 1, characterized in that Also including: Judging whether the external control signal is input as a valid signal; When the input of the external control signal is a valid signal, the step of initializing the pseudo-code generator is re-executed.
7. The method for implementing a floating-point-free pseudo-code generator according to any one of claims 1 to 6, characterized in that, After obtaining the target pseudo-code by reading the corresponding pseudo-code from the read-only memory according to the target addressing count bits, the method further includes: Performing validity verification based on a field-programmable gate array.
8. An apparatus for implementing a pseudo-code generator without floating point, characterized in that, The method includes: A pseudo-code storage module, configured to pre-store the pseudo-code of a corresponding multiple of the sampling period in the read-only memory according to the pseudo-code phase accuracy of the tracking navigation signal; An address output module, configured to initialize the pseudo-code generator, and based on the initial values of the parameters in the pseudo-code generator after initialization, control the count bits of a preset counter by using a preset accumulator in the pseudo-code generator when each pulse clock arrives, so as to determine the target addressing count bits; A pseudo-code determination module, configured to obtain the target pseudo-code by reading the corresponding pseudo-code from the read-only memory according to the target addressing count bits.
9. An electronic device, characterized in that, The electronic device includes a processor and a memory; wherein, the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the method for implementing a floating-point-free pseudo-code generator according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, For storing a computer program; wherein the computer program, when executed by a processor, implements the method for implementing a floating-point-free pseudo-code generator according to any one of claims 1 to 7.