A high-density RRAM sparse digital in-memory computing method and circuit

Abstract

The present invention discloses a high-density RRAM sparse digital in-memory computing method and circuit, relating to the field of integrated circuit design. The method and circuit comprise: a plurality of RRAM in-memory computing units, configured to store data through resistance states, perform digital computing, and obtain output results; a plurality of digital logic units, electrically connected to the RRAM in-memory computing units, configured to perform multiplication and accumulation on the output results to obtain multiplication and accumulation results; and a peripheral circuit unit, electrically connected to the RRAM in-memory computing units, comprising a read path and a write path, configured to simultaneously read and write the resistance states of the RRAM in-memory computing units. One peripheral circuit unit is provided for each column of RRAM in-memory computing units. The present invention can significantly improve data reading and writing efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to a high-density RRAM sparse digital memory calculation method and circuit. Background Art

[0002] With the advancement of satellite technology, the complexity of payload data processing continues to increase, and onboard intelligent computing systems face the need for real-time and energy-efficient computing. Traditional von Neumann architectures face significant bottlenecks in addressing these demands. This is primarily due to the frequent transfer of computing data between the processor and memory, resulting in low computing energy efficiency and high latency, especially in data-intensive applications such as satellite image processing, neural network inference, and large-scale data analysis. To address this issue, in-memory computing technology has emerged. By embedding the computing process within the memory, it reduces data transfer between the memory and processor, significantly improving computing efficiency and energy efficiency. However, existing in-memory computing architectures, particularly those based on resistive random access memory (RRAM), still face several technical challenges.

[0003] First, the complexity of the read circuits for high-density RRAM arrays is an urgent issue that needs to be addressed. RRAM offers high array density and non-volatility, but its read process requires converting the stored resistance into digital signals, which requires complex and power-intensive read circuits. Especially in high-density arrays, existing read circuits are often unable to efficiently and accurately read the stored digital information, thus impacting the overall system performance and energy efficiency. Second, existing sparse neural network computing hardware resource utilization is inefficient. Traditional hardware architectures, especially when processing neural network calculations, rely on traditional adders and multipliers to perform operations. While these components are generally effective, many multipliers and adders are not fully utilized in the calculations when processing sparse neural networks.

[0004] Therefore, how to improve the computing efficiency of sparse networks by optimizing the hardware architecture has become a key technical problem. Summary of the Invention

[0005] To address the aforementioned issues in the prior art, the present invention provides a high-density RRAM sparse digital memory computing method and circuit. The technical problems to be solved by the present invention are achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a high-density RRAM sparse digital in-memory computing circuit, comprising:

[0007] A plurality of RRAM in-memory computing units arranged in an array, wherein the RRAM in-memory computing units are configured to store data through resistance states, perform digital calculations, and obtain output results;

[0008] A plurality of digital logic units arranged in an array, the digital logic units being electrically connected to the RRAM in-memory computing units, the digital logic units being configured to perform multiplication and accumulation on the output results to obtain a multiplication and accumulation result; wherein one digital logic unit is provided for each of the plurality of RRAM in-memory computing units in the same column of RRAM in-memory computing units;

[0009] The peripheral circuit unit is electrically connected to the RRAM in-memory computing unit. The peripheral circuit unit includes a read path and a write path, and is configured to simultaneously read and write the resistance state of the RRAM in-memory computing unit. Among them, one peripheral circuit unit is correspondingly provided for one column of the RRAM in-memory computing unit.

[0010] In a second aspect, the present invention further provides a high-density RRAM sparse digital in-memory computing method, comprising:

[0011] Writing the resistance state of the computing unit in the RRAM memory through the write path of the peripheral circuit unit; wherein a preset binary weight matrix is used as a basis for writing the resistance state of the computing unit in the RRAM memory, the preset binary weight matrix is obtained according to a trained neural network, and each row of the preset binary weight matrix has at most one non-zero weight;

[0012] Setting a word line WL voltage and a bit line BL voltage input to a computing unit in the RRAM memory; wherein a preset characteristic value is used as a basis for the bit line BL voltage input to the computing unit in the RRAM memory, and the preset characteristic value is obtained based on a trained neural network;

[0013] The calculation unit in the RRAM memory performs digital calculations based on the received resistance state, word line WL voltage and bit line BL voltage to obtain the output result;

[0014] The digital logic unit performs multiplication and accumulation calculation on the output result to obtain a multiplication and accumulation result.

[0015] Beneficial effects of the present invention:

[0016] The present invention provides a high-density RRAM sparse digital in-memory computing method and circuit, comprising an RRAM in-memory computing unit, a digital logic unit, and a peripheral circuit unit. The RRAM in-memory computing unit is composed of RRAM and NMOS transistors and has an in-memory computing function. The peripheral circuit unit includes a read path and a write path, which realize the simultaneous reading and writing functions of a row of RRAM in-memory computing units and has a storage function. The digital logic unit is a sparse logic gate and an addition tree, which multiplies and accumulates the output results and outputs the final result. In this way, to address the array density problem caused by the contradiction between high-density RRAM memory computing arrays and complex read circuits, the peripheral circuit unit provided by the present invention has a read path and a write path, realizes the simultaneous reading and writing functions of the same row of RRAM, can significantly improve data reading and writing efficiency, and reduce energy consumption and delay in traditional RRAM computing architectures.

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of a high-density RRAM sparse digital memory computing circuit provided by an embodiment of the present invention;

[0019] Figure 2 This is a flow chart of a high-density RRAM sparse digital memory computing method provided by an embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of a digital logic unit calculation provided by an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of the weight mask fine-tuning training provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0023] In existing RRAM digital in-memory computing architectures, the most common approach is to perform calculations by reading the resistance value of the RRAM cell. For example, a high-density 1T1R cell array is used to store data, and multiplication and accumulation operations are performed by reading the resistance value. However, due to the poor direct compatibility of RRAM's resistance state with digital computing, existing computing methods often require complex analog-to-digital conversion circuits, which consume high power and are easily affected by accuracy. In particular, when the array size increases, the complexity and power consumption of the read circuit become more prominent. In addition, the non-ideality of resistance changes, such as errors and resistance drift in read and write operations, is also a key factor limiting the widespread application of RRAM as an in-memory computing unit.

[0024] In addition, existing sparse neural networks are increasingly used in neural network reasoning and training. In the sparse neural networks used in existing applications, many connection weights are zero, and traditional hardware architectures cannot fully utilize this feature. Most current sparse computing architectures reduce storage requirements and computational burdens through hardware-level sparse representation (e.g., filtering out zero weights). However, existing sparse optimization methods optimize sparsity during the training and reasoning phases of the network, and at the hardware level, many architectures do not truly implement hardware acceleration for sparse computing. This limitation prevents most sparse neural network architectures from fully utilizing the maximum efficiency of their hardware resources.

[0025] In summary, the existing methods have the following defects:

[0026] (1) High-density RRAM arrays require complex read circuits, which limits the speed and energy efficiency of the system.

[0027] (2) The hardware adders and multipliers in traditional sparse network computing occupy a lot of hardware resources, resulting in low computing efficiency.

[0028] In view of this, the present invention provides a high-density RRAM sparse digital memory computing method and circuit, providing a high-density RRAM array with parallel read and write functions to resolve the contradiction between traditional RRAM computing arrays and complex read circuits.

[0029] See Figure 1 , Figure 1 1 is a schematic diagram of a high-density RRAM sparse digital in-memory computing circuit provided by an embodiment of the present invention. The high-density RRAM sparse digital in-memory computing circuit provided by the present invention includes:

[0030] A plurality of RRAM in-memory computing units 10 arranged in an array, wherein the RRAM in-memory computing units 10 are configured to store data through resistance states, perform digital calculations, and obtain output results;

[0031] A plurality of digital logic units 20 arranged in an array, the digital logic units 20 being electrically connected to the RRAM in-memory computing units 10, and the digital logic units 20 being configured to perform multiplication and accumulation on the output results to obtain a multiplication and accumulation result; wherein, one digital logic unit 20 is provided for each of the plurality of RRAM in-memory computing units 10 in the same column of RRAM in-memory computing units;

[0032] The peripheral circuit unit 30 is electrically connected to the RRAM in-memory computing unit 10. The peripheral circuit unit 30 includes a read path and a write path, and is configured to simultaneously read and write the resistance state of the RRAM in-memory computing unit 10. One column of RRAM in-memory computing units corresponds to one peripheral circuit unit 30.

[0033] For more details, please see Figure 1 The high-density RRAM sparse digital in-memory computing circuit provided in this embodiment includes an RRAM in-memory computing unit 10, a digital logic unit 20, and a peripheral circuit unit 30. The RRAM in-memory computing unit 10 is composed of RRAM and NMOS transistors 11 and has an in-memory computing function. The peripheral circuit unit 30 includes a read path and a write path to achieve simultaneous reading and writing functions for a row of RRAM in-memory computing units and has a storage function. The digital logic unit 20 is a sparse logic gate and an adder tree that multiplies and accumulates the output results and outputs the final result. In this way, to address the array density problem caused by the contradiction between high-density RRAM memory computing arrays and complex read circuits, the peripheral circuit unit 30 provided by the present invention has a read path and a write path to achieve simultaneous reading and writing functions for the same row of RRAM, which can significantly improve data reading and writing efficiency and reduce energy consumption and latency in traditional RRAM computing architectures.

[0034] In an optional embodiment of the present invention, please continue to refer to Figure 1 , the RRAM in-memory computing unit 10 includes an NMOS transistor 11, a first RRAM 12 and a buffer 13; wherein,

[0035] The gate of the NMOS transistor 11 is electrically connected to the word line WL, the drain of the NMOS transistor 11 is electrically connected to the peripheral circuit unit 30, the source of the NMOS transistor 11 is electrically connected to the first node N1, the first end of the first RRAM 12 is electrically connected to the first node N1, the second end of the first RRAM 12 is electrically connected to the bit line BL, the input end of the buffer 13 is electrically connected to the first node N1, and the output end of the buffer 13 is electrically connected to the digital logic unit 20.

[0036] For more details, please see Figure 1 In this embodiment, the RRAM in-memory computation unit 10 is composed of RRAM and NMOS transistors 11, and performs in-memory computation. The digital result stored in the RRAM is obtained by voltage division between the RRAM and the gated NMOS transistor 11, thereby reducing area. For multiple rows of RRAM in the same column, the multiplication result is transmitted to an adder tree for multiplication-accumulation calculations, resulting in a multiplication-accumulation result. This result is then transmitted to a shift-accumulation circuit for shift-accumulation to obtain the final output. It can be understood that by voltage division between the RRAM and the gated NMOS transistor and increasing the swing amplitude to obtain the digital result stored in the RRAM, a compatible design is achieved between RRAM and digital in-memory computation, addressing the challenge of large area overhead.

[0037] An optional solution for the RRAM in-memory computing unit 10 requires reading the RRAM resistance value before performing digital in-memory computing. The RRAM's 1-bit value is obtained by voltage division between the RRAM and the select NMOS transistor 11. When the RRAM is in a low-resistance state, i.e., storing a 1, the voltage division point is a high voltage; when the RRAM is in a high-resistance state, i.e., storing a 0, the voltage division point is a low voltage. This high or low voltage is amplified by a buffer 13 and then input into the logic gate and adder tree unit for digital computing, resulting in a multiplication-accumulation result. The buffer 13 uses a cascaded inverter circuit structure to simplify circuit design. Using this unit circuit effectively reduces the power consumption and area overhead of the in-memory computing core, achieving compatibility between RRAM and digital in-memory computing.

[0038] In an optional embodiment of the present invention, please continue to refer to Figure 1 , the peripheral circuit unit 30 includes a single-pole double-throw switch 31, a second RRAM 32 and an operational amplifier 33; wherein,

[0039] When the common terminal of the single-pole double-throw switch 31 is connected to the first terminal, a write operation is performed on the resistance state of the calculation unit 10 in the RRAM memory;

[0040] When the common terminal and the second terminal of the single-pole double-throw switch 31 are conductive, the second terminal of the single-pole double-throw switch 31 is electrically connected to the second node N2, the first terminal of the second RRAM 32 is electrically connected to the second node N2, the second terminal of the second RRAM 32 is electrically connected to the output terminal of the operational amplifier 33, one input terminal of the operational amplifier 33 is connected to the second node N2, and the other input terminal of the operational amplifier 33 receives the Vclp voltage signal to perform a read operation on the resistance state of the calculation unit 10 in the RRAM memory.

[0041] For more details, please see Figure 1 In this embodiment, the peripheral circuit unit 30 includes a read path and a write path, enabling simultaneous reading and writing of a row of RRAM in-memory computing units 10, and also providing storage functionality. To accurately read the RRAM resistance, a low-power, high-precision negative feedback read circuit is designed. The negative feedback resistors are manufactured using the same process as the RRAM to reduce read circuit errors. This implements an RRAM resistance-to-voltage readout method, improving read accuracy and effectively reducing power consumption, particularly advantageous in high-density storage arrays. This enables high-speed, low-power RRAM parallel read and write functionality, enabling simultaneous reading and writing of a row of RRAM.

[0042] In an optional solution, a read path and a write path are provided for each column of RRAM in-memory computing units in the SL driver. The write path simultaneously changes the resistance of a row of first RRAMs. At this time, the BL voltage is set to VDD / 2 and the SL voltage is 0. The low-resistance (SET) write process for the first RRAM 12 (i.e., editing the first RRAM 12 to a low-resistance state and storing a weight of 1) is performed. The high-resistance (RESET) write process for the RRAM is performed by setting the BL voltage to VDD / 2 and the SL voltage to VDD. Each row of first RRAMs 12 is then edited sequentially through the controller. The read path uses a negative feedback circuit to achieve high-precision readout. The BL voltage and Vclp voltage are set to convert the resistance of the second RRAM 32 into a voltage output. The second RRAM 32 resistor in the negative feedback circuit uses the same RRAM process as the first RRAM 12 in the RRAM in-memory computing unit 10 to reduce readout errors caused by negative feedback resistance errors.

[0043] In an optional embodiment of the present invention, the first RRAM 12 and the second RRAM 32 have the same structure.

[0044] Based on the same inventive concept, see Figure 2 , Figure 2 : This is a flow chart of a high-density RRAM sparse digital memory calculation method provided by an embodiment of the present invention. The present invention also provides a high-density RRAM sparse digital memory calculation method, which is applied to the circuit provided by the above embodiment of the present invention. The embodiment of the circuit is referred to above and will not be repeated here. The method includes:

[0045] S101. Writing the resistance state of the computing unit 10 in the RRAM memory through the write path of the peripheral circuit unit 30; wherein a preset binary weight matrix is used as a basis for writing the resistance state of the computing unit 10 in the RRAM memory, the preset binary weight matrix being obtained according to a trained neural network, and each row of the preset binary weight matrix having at most one non-zero weight; it is understood that there is at most one non-zero weight in each row, or there is no non-zero weight in each row;

[0046] S102, setting a word line WL voltage and a bit line BL voltage input to the RRAM in-memory computing unit 10; wherein a preset characteristic value is used as a basis for the bit line BL voltage input to the RRAM in-memory computing unit 10, and the preset characteristic value is obtained based on a trained neural network;

[0047] S103, the RRAM in-memory calculation unit 10 performs digital calculation based on the received resistance state, word line WL voltage, and bit line BL voltage to obtain an output result;

[0048] S104 , the digital logic unit 20 performs a multiplication-accumulation calculation on the output result to obtain a multiplication-accumulation result.

[0049] In an optional embodiment of the present invention, writing the resistance state of the computing unit 10 in the RRAM memory through the write path of the peripheral circuit unit 30 includes:

[0050] The peripheral circuit unit 30 is driven to conduct the write path and write the resistance state of the calculation unit in a column of RRAM memory; wherein,

[0051] When the bit line BL voltage received by the RRAM in-memory calculation unit 10 is VDD / 2 and the source line SL voltage is 0, the resistance state of the RRAM in-memory calculation unit 10 is written to a low resistance state, and the storage logic is 1; when the bit line BL voltage received by the RRAM in-memory calculation unit 10 is VDD / 2 and the source line SL voltage is VDD, the resistance state of the RRAM in-memory calculation unit 10 is written to a high resistance state, and the storage logic is 0.

[0052] In an optional embodiment of the present invention, when the resistance state of the RRAM in-memory computing unit 10 is written to a low resistance state, the first node N1 is a high voltage; when the resistance state of the RRAM in-memory computing unit 10 is written to a high resistance state, the first node N1 is a low voltage.

[0053] In an optional embodiment of the present invention, it also includes:

[0054] The peripheral circuit unit 30 is driven to conduct the read path and read the resistance state of the calculation unit 10 in a row of RRAM memory; wherein,

[0055] The resistance state of the RRAM in-memory calculation unit 10 is read by setting the bit line BL voltage received by the RRAM in-memory calculation unit 10 and the Vclp voltage input to one input terminal of the operational amplifier 33 through the read path of the peripheral circuit unit 30 .

[0056] In an optional embodiment of the present invention, the digital logic unit 20 performs a multiplication-accumulation calculation on the output result to obtain a multiplication-accumulation result, including:

[0057] Multiply the preset binary weight matrix by the preset eigenvalue to obtain the output result in matrix form;

[0058] The output voltages of the same row of the matrix output results are input to the same level OR gate to obtain the calculation results of one row, and the calculation results of all rows are input to the full adder for addition to obtain a calculation result in the matrix form;

[0059] The calculation results in the form of multiple matrices are input into the 2b adder for addition to obtain the calculation results in the form of multiple matrices, and are accumulated into the 3b addition tree for accumulation, and so on to obtain the multiplication and accumulation results.

[0060] Specifically, see Figure 3 , Figure 3 This is a schematic diagram of a digital logic unit calculation provided by an embodiment of the present invention, which is based on a sparse digital in-memory computing architecture that replaces logic gates, replacing the full adder in the conventional addition tree with an OR gate. Figure 3 In the left part, without considering the sparseness of the neural network, for 3 3 The first row of 1-bit values of the convolution result is Figure 3 In the sparse digital in-memory computing method proposed in this embodiment, the convolution kernel of the neural network is trained so that each row has at most one non-zero weight, such as Figure 3 As shown in the figure on the right, replacing the full adder with a three-input OR gate does not cause a loss in calculation accuracy. At the same time, the number of MOS tubes is reduced from 28T to 8T, and the number of adders for subsequent calculations is further reduced, effectively reducing hardware overhead. 3 and assuming that each row has at most one non-zero weight is used as an example to illustrate. In actual applications, the sparsity of the convolution kernel and the number of inputs of the OR gate can be determined according to requirements.

[0061] An alternative option, such as Figure 3 The right side is shown as follows:

[0062] 1. The 9-bit weights of the convolution kernel are "1, 0, 0", "0, 1, 0", and "0, 0, 0", and the 9-bit inputs are "1, 1, 1", "0, 0, 0", and "1, 1, 1", respectively. The product results X0 to X8 are "1, 0, 0, 0, 0, 0, 0, 0", respectively.

[0063] 2. X0 to X2 are input to the first OR gate, the output is 1, X3 to X5 are input to the second OR gate, the output is 0, X6 to X8 are input to the third OR gate, the output is 0;

[0064] 3. Input the three outputs from the previous step into the full adder, which outputs two bits of data 0 and 1. The results are then accumulated into the addition tree.

[0065] In this embodiment, the full adders in the traditional addition tree are innovatively replaced with logic gates (such as "OR gates"). By training the neural network convolution kernel to have at most one non-zero weight per row, the use of multiple full adders is avoided, thereby reducing the number of MOS transistors from 28T to 8T, effectively reducing hardware overhead and power consumption, and improving hardware resource utilization without affecting calculation accuracy.

[0066] Furthermore, this embodiment optimizes computation based on sparsity. By using logic gates and adder tree modules, it significantly reduces redundant computations in sparse neural network calculations, improving computational efficiency. Regardless of the sparsity of the neural network, using logic gates instead of adders can reduce hardware resources in the computation and effectively reduce system energy consumption.

[0067] In an optional embodiment of the present invention, see Figure 4 , Figure 4 This is a schematic diagram of weight mask fine-tuning training provided by an embodiment of the present invention. The training process of a trained neural network includes:

[0068] Using the preset floating-point training to obtain a floating-point model; based on the floating-point model, using the preset pruning training to obtain a sparse model; based on the sparse model, using the preset quantization training to obtain a quantized model, and performing weight mask fine-tuning training on the quantized model to obtain a fine-tuned model;

[0069] Perform weight mask fine-tuning training on the quantized model to obtain a fine-tuned model, including:

[0070] Record the position of the maximum weight in each row of the neural network convolution kernel and generate a weight mask , , 、 and Represent the weights in each row respectively; among them, the mask value of the largest weight position in each row of the neural network convolution kernel is set to 1, and the mask values of the remaining positions in each row are set to 0;

[0071] Apply the weight mask to the weight to get the updated weight , , Represents weight; the updated weight retains the maximum value of each row of the neural network convolution kernel, and the rest are 0. At the same time, the updated weight is used for convolution calculation, which is expressed as , Indicates the current convolution calculation result, Indicates the result of the last convolution calculation;

[0072] Through back propagation, the error is calculated and the weights are updated according to the learning rate , , represents the learning rate, Represents the error, and iterates to obtain the fine-tuning model.

[0073] Specifically, in this embodiment, by recording the position of the maximum weight of each row of the convolution kernel and generating a weight mask, the hardware acceleration efficiency of the sparse neural network is further improved by fine-tuning training while maintaining accuracy. This method combines the advantages of quantization training and pruning training, and provides an effective solution for the implementation of sparse neural networks in hardware. It is understandable that in order to solve the problem of computing energy efficiency caused by the contradiction between lightweight sparse networks and the utilization of digital in-memory computing hardware resources, a sparse digital in-memory computing architecture based on logic gate replacement and a sparse network training method based on weight mask fine-tuning training are proposed to realize a digital in-memory computing architecture with coordinated optimization of software and hardware, solve the challenges of high power consumption and area overhead, and meet the accuracy requirements of neural networks.

[0074] In summary, the present invention provides a high-density RRAM sparse digital in-memory computing circuit. By designing a high-density RRAM digital in-memory computing array, the RRAM array can realize parallel read and write functions, solving the contradiction between the high-density RRAM array and the complex read circuit, and significantly improving the read and write efficiency. Secondly, the present invention adopts algorithm-hardware collaborative design, and by using logic gates to replace traditional adders, it effectively reduces hardware overhead and optimizes the computational efficiency of sparse neural networks. On this basis, the present invention also proposes a sparse neural network training method, which further improves the utilization of hardware resources, reduces power consumption and area overhead, and meets the requirements of high energy efficiency and high performance by fine-tuning the weight mask.

[0075] Through the above innovations, the present invention not only solves the problems of read circuit complexity and resource waste in the prior art, but also provides efficient hardware support for the calculation of sparse neural networks, and has broad application prospects.

[0076] It should be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device comprising the element. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. References to orientations or positional relationships, such as "upper," "lower," "left," and "right," are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the description of the present invention. They do not indicate or imply that the device or element referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present invention.

[0077] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0078] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A high-density RRAM sparse digital in-memory computing circuit, characterized in that: include: A plurality of RRAM in-memory computing units arranged in an array, wherein the RRAM in-memory computing units are configured to store data through resistance states, perform digital calculations, and obtain output results; a plurality of digital logic units arranged in an array, the digital logic units being electrically connected to the RRAM in-memory computing units, the digital logic units being configured to perform multiplication and accumulation on the output results to obtain a multiplication and accumulation result; wherein one digital logic unit is provided for each of the plurality of RRAM in-memory computing units in the same column of RRAM in-memory computing units; a peripheral circuit unit electrically connected to the RRAM in-memory computing unit, the peripheral circuit unit including a read path and a write path, configured to simultaneously read and write the resistance state of the RRAM in-memory computing unit; wherein one peripheral circuit unit is provided for each column of the RRAM in-memory computing unit; The RRAM in-memory computing unit includes an NMOS transistor, a first RRAM, and a buffer; wherein the gate of the NMOS transistor is electrically connected to a word line WL, the drain of the NMOS transistor is electrically connected to the peripheral circuit unit, the source of the NMOS transistor is electrically connected to a first node, the first end of the first RRAM is electrically connected to the first node, the second end of the first RRAM is electrically connected to a bit line BL, the input end of the buffer is electrically connected to the first node, and the output end of the buffer is electrically connected to the digital logic unit; The peripheral circuit unit includes a single-pole double-throw switch, a second RRAM, and an operational amplifier; wherein, when the common end of the single-pole double-throw switch is connected to the first end, a write operation is performed on the resistance state of the calculation unit in the RRAM; when the common end of the single-pole double-throw switch is connected to the second end, the second end of the single-pole double-throw switch is electrically connected to the second node, the first end of the second RRAM is electrically connected to the second node, the second end of the second RRAM is electrically connected to the output end of the operational amplifier, one input end of the operational amplifier is connected to the second node, and the other input end of the operational amplifier receives a Vclp voltage signal, so that a read operation is performed on the resistance state of the calculation unit in the RRAM.

2. The high-density RRAM sparse digital in-memory computing circuit according to claim 1, characterized in that: The first RRAM and the second RRAM have the same structure.

3. A high-density RRAM sparse digital in-memory computing method, applied to the high-density RRAM sparse digital in-memory computing circuit according to any one of claims 1 to 2, characterized in that: include: Writing the resistance state of the computing unit in the RRAM memory through the write path of the peripheral circuit unit; wherein a preset binary weight matrix is used as a basis for writing the resistance state of the computing unit in the RRAM memory, the preset binary weight matrix is obtained according to a trained neural network, and each row of the preset binary weight matrix has at most one non-zero weight; Setting a word line WL voltage and a bit line BL voltage input to the RRAM in-memory computing unit; wherein a preset characteristic value is used as a basis for the bit line BL voltage input to the RRAM in-memory computing unit, and the preset characteristic value is obtained based on a trained neural network; The RRAM in-memory calculation unit performs digital calculation based on the received resistance state, word line WL voltage and bit line BL voltage to obtain an output result; The digital logic unit performs multiplication and accumulation calculation on the output result to obtain a multiplication and accumulation result.

4. The high-density RRAM sparse digital in-memory computing method according to claim 3, characterized in that: Writing the resistance state of the computing unit in the RRAM memory through the write path of the peripheral circuit unit includes: The peripheral circuit unit is driven to conduct the write path and write the resistance state of a column of the calculation unit in the RRAM memory; wherein, When the bit line BL voltage received by the RRAM in-memory calculation unit is VDD / 2 and the source line SL voltage is 0, the resistance state of the RRAM in-memory calculation unit is written as a low resistance state, and the storage logic is 1; when the bit line BL voltage received by the RRAM in-memory calculation unit is VDD / 2 and the source line SL voltage is VDD, the resistance state of the RRAM in-memory calculation unit is written as a high resistance state, and the storage logic is 0.

5. The high-density RRAM sparse digital in-memory computing method according to claim 4, characterized in that: When the resistance state of the RRAM in-memory computing unit is written as a low resistance state, the first node is a high voltage; when the resistance state of the RRAM in-memory computing unit is written as a high resistance state, the first node is a low voltage.

6. The high-density RRAM sparse digital in-memory computing method according to claim 3, characterized in that: Also includes: The peripheral circuit unit is driven to conduct the read path and read the resistance state of a row of computing units in the RRAM memory; wherein, The bit line BL voltage received by the RRAM in-memory calculation unit and the Vclp voltage input to one input terminal of the operational amplifier are set through the read path of the peripheral circuit unit to read the resistance state of the RRAM in-memory calculation unit.

7. The high-density RRAM sparse digital in-memory computing method according to claim 3, characterized in that: The digital logic unit performs a multiplication-accumulation calculation on the output result to obtain a multiplication-accumulation result, including: Multiplying the preset binary weight matrix by the preset eigenvalue to obtain an output result in matrix form; Inputting the output voltages of the same row of the matrix output results into the same level OR gate to obtain a calculation result of one row, and inputting the calculation results of all rows into a full adder for addition to obtain a calculation result in a matrix form; The calculation results in the form of multiple matrices are input into the 2b adder for addition to obtain the calculation results in the form of multiple matrices, and are accumulated into the 3b addition tree for accumulation, and so on to obtain the multiplication and accumulation results.

8. The high-density RRAM sparse digital in-memory computing method according to claim 3, characterized in that: The training process of the trained neural network includes: Using a preset floating-point training method to obtain a floating-point model; based on the floating-point model, using a preset pruning training method to obtain a sparse model; based on the sparse model, using a preset quantization training method to obtain a quantized model, and performing weight mask fine-tuning training on the quantized model to obtain a fine-tuned model; The step of performing weight mask fine-tuning training on the quantization model to obtain a fine-tuning model includes: Record the position of the maximum weight in each row of the neural network convolution kernel and generate a weight mask; the mask value of the position with the maximum weight in each row of the neural network convolution kernel is set to 1, and the mask values of the remaining positions in each row are set to 0; Apply the weight mask to the weight to obtain the updated weight; the updated weight retains the maximum value of each row of the neural network convolution kernel, and the rest are 0. At the same time, the updated weight is used for convolution calculation; Through back propagation, the error is calculated and the weights are updated according to the learning rate. This is repeated to obtain a fine-tuned model.

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