Hardware-based access pattern recognition apparatus and method

Abstract

The application provides a memory access mode recognition device and method based on hardware implementation. The device comprises: a plurality of parallel memory access mode recognition units, each of which is implemented through an independent state machine logic and is configured to dynamically adjust a confidence value according to a memory trace of an application program and recognize a specific type of memory access mode; a plurality of data storage units connected with the plurality of memory access mode recognition units, and some of the memory access mode recognition units share the same data storage unit; a plurality of confidence counters used to record the confidence values of the memory access modes by using a program counter as an index; and a control unit used to coordinate the working time sequence of the memory access mode recognition units, the data storage units and the confidence counters. The memory access mode recognition units, the data storage units, the confidence counters and the control unit are all implemented through hardware RTL, which significantly improves the efficiency of memory access mode recognition and reduces the hardware resource occupation.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computer architecture and hardware design, and particularly relates to a memory access mode recognition device and method based on hardware implementation. BACKGROUND

[0002] Cache is a key component in modern computer storage systems, and its performance directly affects the overall efficiency of the central processing unit (CPU). Whether the data prefetcher in the cache can accurately prefetch the data block that the CPU will need is an important factor in determining the system performance. Memory access pattern analysis provides important support for the design and testing of cache data prefetchers: by analyzing the memory access behavior of an application, specific memory access patterns can be identified, and hardware prefetchers can be designed for these patterns. During the design process, selecting an application that contains a high proportion of target memory access patterns as a test set can effectively verify the performance of the prefetcher.

[0003] However, existing memory access pattern analysis tools are mainly based on software implementation, and have problems such as low running efficiency, large storage overhead, and difficulty in meeting real-time and resource efficiency requirements. To address this problem, the present application proposes a memory access pattern hardware circuit based on hardware implementation to improve the speed of memory access pattern analysis and reduce storage overhead, providing efficient support for the design and optimization of cache prefetchers. SUMMARY

[0004] In view of the deficiencies of the prior art, the present application proposes a memory access pattern recognition device and method based on hardware implementation, which is based on hardware RTL implementation to meet the recognition needs of different memory access patterns, and designs a dedicated storage structure and read-write control logic, including a block-shared storage unit and a parallel recognition unit. By optimizing the data storage and access process, the efficiency of memory access pattern recognition is significantly improved, while the hardware resource occupation is reduced, achieving high resource utilization.

[0005] In one aspect, the present application provides a memory access pattern recognition device based on hardware implementation, comprising:

[0006] A plurality of parallel memory access pattern recognition units, each implemented by an independent state machine logic and configured to dynamically adjust the confidence value recorded by the confidence counter according to the memory trace of an application program, and recognize a specific type of memory access pattern;

[0007] A plurality of data storage units adopting a block storage structure, connected to the plurality of memory access pattern recognition units, and sharing the same data storage unit between some of the memory access pattern recognition units, for storing the memory trace and intermediate data output by each of the memory access pattern recognition units;

[0008] a plurality of confidence counters, each confidence counter corresponding to one of the memory access pattern recognition units and configured to record a confidence value of each memory access pattern using a program counter as an index;

[0009] a control unit connected to the plurality of memory access pattern recognition units, the plurality of data storage units, and the plurality of confidence counters, and configured to coordinate the working timing of the memory access pattern recognition units, the data storage units, and the confidence counters;

[0010] wherein the memory access pattern recognition units, the data storage units, the confidence counters, and the control unit are implemented by hardware RTL.

[0011] In an embodiment of the present application, the memory access pattern recognition unit comprises a first recognition unit configured to recognize a static memory access pattern, and is configured to:

[0012] compare the consistency of the current memory access address in the memory access trace with the historical memory access address of the same instruction, and increase the confidence value if the consistency is consistent, or decrease the confidence value if the consistency is inconsistent;

[0013] recognize the static memory access pattern when the confidence value is greater than or equal to a first threshold value.

[0014] In an embodiment of the present application, the memory access pattern recognition unit comprises a second recognition unit configured to recognize a stride memory access pattern, and is configured to:

[0015] calculate the difference between the memory access addresses of a given stride between the same instruction interval in the memory access trace, and verify whether the difference is continuously consistent;

[0016] increase the confidence value if the difference is continuously consistent, or decrease the confidence value if the difference is not continuously consistent;

[0017] recognize the stride memory access pattern when the confidence value is greater than or equal to a second threshold value.

[0018] In an embodiment of the present application, the memory access pattern recognition unit comprises:

[0019] a third recognition unit configured to recognize a pointer array memory access pattern, and is configured to perform matching detection on the current memory access address in the memory access trace and the historical memory access read-write value under a preset number of stride memory access patterns, increase the confidence value if the matching detection is successful, decrease the confidence value if the matching detection is unsuccessful and the confidence value is less than a third threshold value, and recognize the pointer array memory access pattern when the confidence value is greater than or equal to the third threshold value; and / or,

[0020] The fourth identification unit configured to identify the common pointer type access mode, is configured to: perform matching detection on the current access address in the access trace and a preset number of historical access read-write values; if the matching detection is successful, the confidence value is increased; if the matching detection is failed and the confidence value is less than a fourth threshold value, the confidence value is decreased; and when the confidence value is greater than or equal to the fourth threshold value, the common pointer type access mode is identified.

[0021] The fifth identification unit configured to identify the structure pointer type access mode, is configured to: calculate an absolute difference value between the current access address in the access trace and a preset number of historical access read-write values as a first difference value, and compare the first difference value with a preset difference threshold value; if the first difference value is greater than or equal to the preset difference threshold value, the confidence value is increased; otherwise, the confidence value is decreased; and when the confidence value is greater than or equal to a fifth threshold value, the structure pointer type access mode is identified.

[0022] The sixth identification unit configured to identify the pointer chasing type access mode, is configured to: calculate a difference value between the access address and the access read-write value of each time of the same instruction in the access trace as a second difference value; compare whether the second difference values obtained by the current time and the last time are the same; if the second difference values are consistent, the confidence value is increased; if the second difference values are inconsistent and the confidence value is less than a sixth threshold value, the confidence value is decreased; and when the confidence value is greater than or equal to the sixth threshold value, the pointer chasing type access mode is identified.

[0023] In an embodiment of the present application, the access mode identification unit comprises a seventh identification unit configured to identify the indirect type access mode, which is configured to:

[0024] calculate a difference value between the current access address in the access trace and the historical access address of the same instruction as a third difference value;

[0025] calculate a stride difference value of a preset number of historical access read-write values in the stride type access mode as a fourth difference value;

[0026] if a proportional relationship between the third difference value and the fourth difference value meets a preset proportional factor, the confidence value is increased; if the proportional relationship does not meet the preset proportional factor and the confidence value is less than a seventh threshold value, the confidence value is decreased; and when the confidence value is greater than or equal to the seventh threshold value, the indirect type access mode is identified.

[0027] In an embodiment of the present application, the access mode identification unit comprises an eighth identification unit configured to identify the heap access mode, which is configured to: calculate whether a proportional difference value between the access addresses of the same instruction in the access trace meets the characteristics of the heap; if yes, the confidence value is increased; if no, the confidence value is decreased; and when the confidence value is greater than or equal to an eighth threshold value, the heap access mode is identified.

[0028] In an embodiment of the present application, the plurality of data storage units comprises:

[0029] A first data storage unit, connected to the first identification unit and the seventh identification unit, the first identification unit and the seventh identification unit sharing the first data storage unit;

[0030] A second data storage unit, connected to the second identification unit and the eighth identification unit, the second identification unit and the eighth identification unit sharing the second data storage unit;

[0031] A third data storage unit, connected to the fourth identification unit and the fifth identification unit, the fourth identification unit and the fifth identification unit sharing the third data storage unit;

[0032] A fourth data storage unit, connected to the sixth identification unit;

[0033] A fifth data storage unit, connected to the third identification unit and the seventh identification unit, the third identification unit and the seventh identification unit sharing the fifth data storage unit.

[0034] In an embodiment of the present application, further comprising:

[0035] An input / output interface unit, connected to the plurality of data storage units and the plurality of confidence counters, supporting user-defined protocols, for receiving externally inputted memory access trace data, and outputting the final identified memory access patterns and the confidence values of each memory access pattern to an external storage medium or a computer.

[0036] According to the above-mentioned hardware-based memory access pattern recognition device, the present application further provides a hardware-based memory access pattern recognition method, comprising:

[0037] Receiving the memory access trace data of the application program and storing it in each data storage unit;

[0038] The control unit triggers each memory access pattern recognition unit and each confidence counter, calls the memory trace to determine the confidence values recorded by each confidence counter according to the preset pattern recognition strategy, and recognizes each type of memory access pattern.

[0039] In an embodiment of the present application, the identification of the stride type memory access pattern is triggered first, and then the identification of the pointer array type memory access pattern and / or the indirect type memory access pattern is triggered.

[0040] In an embodiment of the present application, the preset pattern recognition strategy comprises:

[0041] A first identification strategy configured to identify the static memory access pattern, the first identification strategy configured to: compare consistency of a current memory access address in the memory access trace with a historical memory access address of a same instruction, increase the confidence value if the consistency is consistent, and decrease the confidence value if the consistency is inconsistent; and identify the static memory access pattern when the confidence value is greater than or equal to a first threshold value; and / or,

[0042] A second identification strategy configured to identify the stride memory access pattern, the second identification strategy configured to: calculate a difference value between memory access addresses of a same instruction interval in the memory access trace, verify whether the difference value is continuously consistent; increase the confidence value if the difference value is continuously consistent, and decrease the confidence value if the difference value is not continuously consistent; and identify the stride memory access pattern when the confidence value is greater than or equal to a second threshold value;

[0043] A third identification strategy configured to identify the pointer array memory access pattern, the third identification strategy configured to: perform matching detection on the current memory access address in the memory access trace with a preset number of historical memory access read-write values in the stride memory access pattern, increase the confidence value if the matching detection is successful, and decrease the confidence value if the matching detection is not successful and the confidence value is less than a third threshold value; and identify the pointer array memory access pattern when the confidence value is greater than or equal to the third threshold value.

[0044] A fourth identification strategy configured to identify the ordinary pointer memory access pattern, the fourth identification strategy configured to: perform matching detection on the current memory access address in the memory access trace with a preset number of historical memory access read-write values; increase the confidence value if the matching detection is successful, and decrease the confidence value if the matching detection is not successful and the confidence value is less than a fourth threshold value; and identify the ordinary pointer memory access pattern when the confidence value is greater than or equal to the fourth threshold value.

[0045] A fifth identification strategy configured to identify the structure pointer memory access pattern, the fifth identification strategy configured to: calculate an absolute difference value between the current memory access address in the memory access trace and a preset number of historical memory access read-write values as a first difference value, compare the first difference value with a preset difference value threshold value, increase the confidence value if the first difference value is greater than or equal to the preset difference value threshold value, and decrease the confidence value if the first difference value is less than the preset difference value threshold value; and identify the structure pointer memory access pattern when the confidence value is greater than or equal to a fifth threshold value.

[0046] A sixth identification strategy is configured to identify a pointer chasing memory access pattern, and the sixth identification strategy is configured to: calculate a difference between a memory access address and a memory read-write value of a same instruction in the memory access trace as a second difference, compare whether the second difference calculated in a current time and a last time is same, increase the confidence value if the second difference is consistent, decrease the confidence value if the second difference is inconsistent and the confidence value is less than a sixth threshold value, and identify the memory access pattern as the pointer chasing memory access pattern when the confidence value is greater than or equal to the sixth threshold value.

[0047] A seventh identification strategy is configured to identify an indirect memory access pattern, and the seventh identification strategy is configured to: calculate a difference between a current memory access address and a historical memory access address of a same instruction in the memory access trace as a third difference, calculate a stride difference between historical memory read-write values in a preset number of stride memory access patterns as a fourth difference, increase the confidence value if a proportional relationship between the third difference and the fourth difference meets a preset proportional factor, decrease the confidence value if the proportional relationship does not meet the preset proportional factor and the confidence value is less than a seventh threshold value, and identify the memory access pattern as the indirect memory access pattern when the confidence value is greater than or equal to the seventh threshold value.

[0048] An eighth identification strategy is configured to identify a heap memory access pattern, and the eighth identification strategy is configured to: calculate whether a proportional difference between memory access addresses of a same instruction in the memory access trace meets a characteristic of a heap, increase the confidence value if the proportional difference meets the characteristic of the heap, decrease the confidence value if the proportional difference does not meet the characteristic of the heap, and identify the memory access pattern as the heap memory access pattern when the confidence value is greater than or equal to an eighth threshold value.

[0049] According to the above scheme, the application has the following advantages:

[0050] The memory access pattern identification device based on hardware provided by the application is implemented based on hardware RTL, and a special storage structure and read-write control logic are designed, including a block-shared storage unit and a parallel identification unit. The memory access pattern identification unit is implemented by an independent state machine logic, and is configured to dynamically adjust a confidence value according to a memory access trace of an application program, and identify a specific type of memory access pattern. The same data storage unit is shared between part of the memory access pattern identification units. A plurality of confidence counters are used to record the confidence values of the memory access patterns by using a program counter as an index. A control unit is used to coordinate the working time sequence of the memory access pattern identification unit, the data storage unit and the confidence counter. The memory access pattern identification unit, the data storage unit, the confidence counter and the control unit are all implemented by hardware RTL. The efficiency of the memory access pattern identification is improved, the hardware resource occupation is reduced, and high resource utilization is achieved by optimizing the data storage and access process. The application supports the addition of a new identification unit. The expandable design makes the system flexible and adaptable to new identification requirements. BRIEF DESCRIPTION OF DRAWINGS

[0051] Figure 1 Fig. 1 shows a schematic diagram of the overall structure of a hardware-based memory access pattern recognition device according to an embodiment of the present application;

[0052] Figure 2 Fig. 2 shows a schematic diagram of the detailed structure of a hardware-based memory access pattern recognition device according to an embodiment of the present application;

[0053] Figure 3 Fig. 3 shows a schematic diagram of the overall flow of a hardware-based memory access pattern recognition method according to an embodiment of the present application.

[0054] In the drawings:

[0055] 10: memory access pattern recognition device;

[0056] 110: memory access pattern recognition unit;

[0057] 1101: first recognition unit;

[0058] 1102: second recognition unit;

[0059] 1103: third recognition unit;

[0060] 1104: fourth recognition unit;

[0061] 1105: fifth recognition unit;

[0062] 1106: sixth recognition unit;

[0063] 1107: seventh recognition unit;

[0064] 1108: eighth recognition unit;

[0065] 120: data storage unit;

[0066] 1201: first data storage unit;

[0067] 1202: second data storage unit;

[0068] 1203: third data storage unit;

[0069] 1204: fourth data storage unit;

[0070] 1205: fifth data storage unit;

[0071] 130, 1301-1308: confidence counter;

[0072] 140: control unit;

[0073] 1501: input interface unit;

[0074] 1502: output interface unit;

[0075] 160: storage medium. DETAILED DESCRIPTION

[0076] It should be noted that the relational terms herein such as first and second and the like are used solely to distinguish one from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0077] Without further limitation, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0078] Embodiment One:

[0079] Figure 1 An overall structure schematic diagram of a hardware-based memory access pattern recognition device provided by an embodiment of the present application is shown. The memory access pattern recognition device 10 includes a plurality of memory access pattern recognition units 110, a plurality of data storage units 120, a plurality of confidence counters 130, a control unit 140, and an input / output interface unit. The plurality of memory access pattern recognition units 110 adopt a parallel processing architecture to accelerate the memory access pattern recognition process. Each memory access pattern recognition unit is implemented by an independent state machine logic and is configured to dynamically adjust the confidence value recorded by the confidence counter according to the memory access trace of an application program to recognize a specific type of memory access pattern.

[0080] The plurality of data storage units 120 are connected to the plurality of memory access pattern recognition units 110. The plurality of data storage units 120 are used to store the memory access trace and the intermediate data output by each memory access pattern recognition unit 110. The plurality of data storage units 120 adopt a block storage structure to reduce storage overhead and improve data access efficiency. In an embodiment, some of the memory access pattern recognition units 110 share the same data storage unit 120. Some of the same data storage units 120 are configured to support at least two memory access pattern recognition units 110 to share access, and efficient sharing of data is achieved through time-sharing multiplexing or parallel access mechanisms.

[0081] Each confidence counter 130 corresponds to a memory access pattern recognition unit 110, and is used to record the confidence value of each memory access pattern using the program counter (PC) as the index, so that each memory access pattern recognition unit uses the corresponding confidence value to identify the corresponding memory access pattern.

[0082] It should be noted that in the embodiment, each memory access pattern corresponds to a memory access pattern recognition unit 110, and each memory access pattern recognition unit 110 corresponds to a confidence counter 130, which only records the confidence value of the corresponding memory access pattern, but not the confidence values of other memory access pattern recognition units. The confidence counters 130 of each memory access pattern recognition unit 110 are independent of each other, and the confidence values of each memory access pattern are only collectively referred to as the parameter of confidence value. The confidence values of different memory access patterns are not calculated in the same way, that is, each memory access pattern corresponds to a different confidence value.

[0083] The control unit 140 is connected to the plurality of memory access pattern recognition units 110, the plurality of data storage units 120, and the plurality of confidence counters 130, and is used to coordinate the working timing of the memory access pattern recognition units 110, the data storage units 120, and the confidence counters 130. For example, a read / write signal is sent to the data storage unit to schedule the access of memory trace data and intermediate data; an enable signal is sent to the memory access pattern recognition unit to trigger the state machine to start the analysis process to identify the memory access pattern; and the update result of the confidence counter is received to determine whether the confidence value recorded by each confidence counter exceeds the threshold value corresponding to each memory access pattern, and the corresponding memory access pattern identifier is output.

[0084] The input / output interface unit is connected to the plurality of data storage units 120, the plurality of confidence counters 130, and the external storage medium 160, supports user-defined protocols, supports FIFO buffering and bus protocols. The input / output interface unit includes an input interface unit 1501 and an output interface unit 1502. The input interface unit 1501 is used to retrieve the memory trace data stored in the external storage medium 160 to the data storage unit 120 for temporary storage, and then the memory access pattern recognition unit 110 performs memory access pattern recognition. The intermediate data generated in the identification process is stored in the data storage unit 120, and the output interface unit 1502 outputs the final identified memory access pattern and confidence value to the external storage medium 160 or computer.

[0085] The memory access pattern recognition unit 110, the data storage unit 120, the confidence counter 130, the control unit 140, and the input / output interface unit are all implemented by hardware RTL.

[0086] In this embodiment, multiple memory access mode recognition units are configured to run in parallel to meet the recognition needs of different memory access modes, and each memory access mode recognition unit independently processes one memory access mode, and the timing is coordinated by the control unit. At the same time, the data storage unit adopts a block and shared design to reduce resource competition. The memory access mode recognition unit relies on a state machine to implement the operation process, and the confidence counter update and mode determination are completed synchronously in the state machine to ensure the timing correctness. Through optimizing the data storage and access process, the efficiency of memory access mode recognition is significantly improved, the hardware resource occupation is reduced, and high resource utilization is realized.

[0087] Embodiment two:

[0088] Figure 2 A detailed structure diagram of a hardware-based memory access mode recognition device provided by another embodiment of the application is shown. The memory access mode recognition device 10 includes multiple memory access mode recognition units 110, multiple data storage units 120, multiple confidence counters 130, a control unit 140, and an input / output interface unit. The memory access mode recognition units 110, the data storage units 120, the confidence counters 130, the control unit 140, and the input / output interface unit are all implemented by hardware RTL.

[0089] Among them, for the recognition needs of different memory access modes, this embodiment specifically needs to recognize eight memory access modes: static memory access mode, stride memory access mode, pointer array memory access mode, ordinary pointer memory access mode, structure pointer memory access mode, pointer chasing memory access mode, indirect memory access mode, and heap memory access mode. For the recognition of these eight memory access modes, the multiple memory access mode recognition units 110 in this embodiment specifically include a first recognition unit 1101 for recognizing static memory access mode, a second recognition unit 1102 for stride memory access mode, a third recognition unit 1103 for recognizing pointer array memory access mode, a fourth recognition unit 1104 for ordinary pointer memory access mode, a fifth recognition unit 1105 for structure pointer memory access mode, a sixth recognition unit 1106 for recognizing pointer chasing memory access mode, a seventh recognition unit 1107 for indirect memory access mode, and an eighth recognition unit 1108 for recognizing heap memory access mode. Among them, the first recognition unit 1101, the second recognition unit 1102, the third recognition unit 1103, the fourth recognition unit 1104, the fifth recognition unit 1105, the sixth recognition unit 1106, the seventh recognition unit 1107, and the eighth recognition unit 1108 adopt a parallel processing architecture to speed up the memory access mode recognition process. Each memory access mode recognition unit is implemented by an independent state machine logic and is configured to dynamically adjust the confidence value recorded by the confidence counter according to the memory trace of the application program to recognize a specific type of memory access mode.

[0090] The plurality of data storage units 120 are connected with the plurality of memory access pattern identification units 110, and the plurality of data storage units 120 are used to store the memory access traces and the intermediate data output by each of the memory access pattern identification units 110. The plurality of data storage units 120 adopt a block storage structure, which is used to reduce storage overhead and improve data access efficiency. In an embodiment, some of the memory access pattern identification units 110 share the same data storage unit 120. Specifically, the plurality of data storage units 120 include a first data storage unit 1201, a second data storage unit 1202, a third data storage unit 1203, a fourth data storage unit 1204, and a fifth data storage unit 1205. The first data storage unit 1201 is connected with the first identification unit 1101 and the seventh identification unit 1107, and the first identification unit 1101 and the seventh identification unit 1107 share the first data storage unit 1201, i.e., the intermediate data output by the first identification unit 1101 and the seventh identification unit 1107 can be stored in the first data storage unit 1201. The second data storage unit 1202 is connected with the second identification unit 1102 and the eighth identification unit 1108, and the second identification unit 1102 and the eighth identification unit 1108 share the second data storage unit 1202, and the intermediate data output by the second identification unit 1102 and the eighth identification unit 1108 is stored in the second data storage unit 1202. The third data storage unit 1203 is connected with the fourth identification unit 1104 and the fifth identification unit 1105, and the fourth identification unit 1104 and the fifth identification unit 1105 share the third data storage unit 1203, i.e., the intermediate data output by the fourth identification unit 1104 and the fifth identification unit 1105 is stored in the third data storage unit 1203. The fourth data storage unit 1204 is connected with the sixth identification unit 1106, and the intermediate data output by the sixth identification unit 1106 is stored in the fourth data storage unit 1204. The fifth data storage unit 1205 is connected with the third identification unit 1103 and the seventh identification unit 1107, and the third identification unit 1103 and the seventh identification unit 1107 share the fifth data storage unit 1205, and the intermediate data output by the third identification unit 1103 and the seventh identification unit 1107 can be stored in the fifth data storage unit 1205. In this embodiment, some of the same data storage units 120 are configured to support at least two memory access pattern identification units 110 to share access, and the efficient sharing of data is realized through time multiplexing or parallel access mechanisms.

[0091] Each confidence counter 130 corresponds to a memory access pattern recognition unit 110, and is used to record the confidence value of each memory access pattern using program counter (PC) as index, so that each memory access pattern recognition unit uses the corresponding confidence value to identify the corresponding memory access pattern. In this embodiment, each memory access pattern corresponds to a memory access pattern recognition unit 110, and each memory access pattern recognition unit 110 corresponds to a confidence counter 130. Specifically, as shown in Figure 2 The first recognition unit 1101, the second recognition unit 1102, the third recognition unit 1103, the fourth recognition unit 1104, the fifth recognition unit 1105, the sixth recognition unit 1106, the seventh recognition unit 1107, and the eighth recognition unit 1108 correspond to the confidence counters 1301-1308, respectively. The confidence counters 1301-1307 are independent of each other, and each confidence counter only records the confidence value of the corresponding memory access pattern, but not the confidence values of other memory access pattern recognition units.

[0092] The control unit 140 is connected to the plurality of memory access pattern recognition units 110, the plurality of data storage units 120, and the plurality of confidence counters 130, and is used to coordinate the working timing of the memory access pattern recognition units 110, the data storage units 120, and the confidence counters 130. The input / output interface unit is connected to the plurality of data storage units 120, the plurality of confidence counters 130, and the external storage medium 160, supports user-defined protocols, supports FIFO buffering and bus protocols. The input interface unit 1501 is used to retrieve the memory access trace data stored in the external storage medium 160 to the data storage unit 120 for temporary storage, and then the memory access pattern recognition unit 110 performs memory access pattern recognition. The intermediate data generated in the recognition process is stored in the data storage unit 120, and the output interface unit 1502 outputs the final recognized memory access pattern and confidence value to the external storage medium 160 or computer.

[0093] In an embodiment, the first identification unit 1101 is configured to identify the static access pattern, and the first identification unit 1101 is configured to compare the consistency of the current access address in the access trace and the historical access address of the same instruction, increase the confidence value if the consistency is correct, and decrease the confidence value if the consistency is incorrect; and identify the static access pattern when the confidence value is greater than or equal to a first threshold value. Specifically, the input signals of the first identification unit 1101 include: the current access address, the historical access address of the same instruction, the clock signal, the enable signal, and the current confidence value of the instruction; and the output signals include: the updated confidence value and the flag bit of the confidence counter 1301. The first identification unit 1101 analyzes the instruction as the granularity, and the data required for each analysis is the current access address in the access trace and the historical access address of the same instruction. The logic of the first identification unit 1101 is implemented by a state machine, which includes three main states: an idle state, a confidence counter modification state, and an end state. In the idle state, the enable signal is triggered. If the enable signal is true, the flag bit of the first confidence counter 1301 connected to the first identification unit 1101 is checked first. If the flag bit indicates that the current mode has been confirmed, the end state is directly jumped to; if the flag bit is 0, the confidence counter modification state is entered, and the confidence value is updated. In the confidence counter modification state, it is determined whether the current access address is the same as the historical access address (for example, the last access address) of the same instruction, that is, the consistency of the current access address in the access trace and the historical access address of the same instruction is compared. If the same, the confidence value is increased, for example, in a linear increasing, nonlinear increasing, or conditional increasing manner, such as increasing the confidence counter by one; if different, the confidence value is decreased, for example, in a linear decreasing, nonlinear decreasing, or proportional decay manner, such as dividing the confidence counter by two. When the confidence value is greater than or equal to the first threshold value, the static access pattern is identified. At this time, the end state is entered, and the end signal is sent, and the identification process of the static access pattern is completed. In this embodiment, the increasing or decreasing manner of the confidence value is not limited to the above manner, and the first threshold value can be set as a static threshold value or an adaptive dynamic threshold value to balance the identification accuracy and speed. For example, the static threshold value can be set in combination with hardware resources such as memory consumption or counter bit width. For example, the adaptive dynamic threshold value can be set based on the historical mode frequency (if a certain instruction frequently triggers the static access pattern, the threshold value can be dynamically increased to reduce the misjudgment), or the threshold value is set according to the rules of increasing or decreasing the confidence value, and the present application is not limited thereto.

[0094] In addition, in this embodiment, the first identification unit 1101 can store the current access address in the access trace required for each analysis, the historical access address of the same instruction (for example, the access address of the last instruction), and the output updated confidence value, the flag of the confidence counter, and the like in the first data storage unit 1201, thereby supporting parallel access of multiple instructions.

[0095] In an embodiment, the second identification unit 1102 is configured to identify the stride access pattern by calculating the difference between the memory addresses of a given stride of the same instruction interval in the memory access trace, verifying whether the difference is consistent, increasing the confidence value if the difference is consistent, decreasing the confidence value if the difference is not consistent, and identifying the stride access pattern when the confidence value is greater than or equal to a second threshold. Specifically, the input signals of the second identification unit 1102 include the current memory address, the historical memory addresses of the same instruction, a clock signal, an enable signal, the current confidence value of the instruction, and the stride length recorded by the historical memory addresses. The output signals include the calculated stride length, the updated confidence value, and the flag of the confidence counter 1302. The second identification unit 1102 analyzes the instructions and requires the current memory address and the historical memory addresses of the same instruction. For a stride of 2, the stride length is determined by calculating the difference between the current memory address and the memory address of the previous instruction. The second identification unit 1102 is implemented by a state machine and includes an idle state, a confidence counter modification state, and an end state. In the idle state, the second identification unit 1102 waits for the enable signal. If the enable signal is true, the flag of the confidence counter 1302 connected to the second identification unit 1102 is checked. If the flag indicates that the stride access pattern has been confirmed, the end state is directly jumped to. If the flag is 0, the confidence counter modification state is entered. In the confidence counter modification state, it is determined whether the difference between the current memory address and the memory address of the previous instruction is equal to the stride length recorded by the memory address of the previous instruction. If the difference is equal, the confidence value is increased, for example, by linearly increasing, nonlinearly increasing, or conditionally increasing the confidence counter. If the difference is not equal, the confidence value is decreased, for example, by linearly decreasing, nonlinearly decreasing, or proportionally decreasing the confidence counter. When the confidence value is greater than or equal to the second threshold, the stride access pattern is identified. At this time, the end state is entered, the end signal is sent, and the identification process of the stride access pattern is completed. In this embodiment, the increasing or decreasing manner of the confidence value is not limited to the above manner, and the second threshold can be set as a static threshold or an adaptive dynamic threshold to balance the identification accuracy and speed. For example, the static threshold can be set in combination with hardware resources such as memory consumption or counter bit width. For example, the adaptive dynamic threshold can be set based on the historical pattern frequency (if a certain instruction frequently triggers the stride access pattern, the threshold can be dynamically increased to reduce false positives), or the confidence value increasing or decreasing rule, which is not limited in the present application.

[0096] In addition, in this embodiment, the second identification unit 1102 can store the current memory access address in the memory access trace to be analyzed, the historical memory access address of the same instruction (e.g., the last memory access address on each instruction), and the updated confidence value, the calculated stride length, the flag of the confidence counter, and other data outputted each time in the second data storage unit 1202.

[0097] In an embodiment, the third identification unit 1103 is configured to identify the pointer array type memory access mode, and is configured to: perform matching detection on the current memory access address in the memory access trace and the preset number of historical memory read / write values in the stride type memory access mode, and if matching is detected, increase the confidence value; if matching is not detected and the confidence value is less than a third threshold value, decrease the confidence value; and when the confidence value is greater than or equal to the third threshold value, identify the pointer array type memory access mode. The input signals of the third identification unit 1103 include: the current memory access address, the preset number of historical memory read / write values in the stride type memory access mode, a clock signal, an enable signal, and the current confidence value of the instruction. The output signals include: the updated confidence value and the flag bit of the confidence counter 1303. The determination condition of the third identification unit 1103 is based on the input historical memory read / write values in the stride type memory access mode, and whether the characteristics of the pointer array type memory access mode are met is determined by directly analyzing these values. In an embodiment, the historical memory read / write values of 8 stride type memory access modes are split and stored in registers, and the current memory access address is matched with the historical memory read / write values of the 8 stride type memory access modes respectively. If matching is successful, the matching result is recorded in a 1-bit register. In the timing circuit part, the third identification unit 1103 is implemented by using a state machine, and four states are set, including an idle state, a confidence counter increasing state, a confidence counter decreasing state, and an end state. In the idle state, the enable signal is waited for triggering. In the confidence counter increasing state, if the matching register is true, the confidence counter increasing state is entered and the confidence value is increased, for example, the confidence value is increased in a linear increasing, non-linear increasing, or conditional increasing manner, such as increasing the confidence counter by 1. In the confidence counter decreasing state, if the matching register is false and the confidence value is less than the third threshold value, the confidence counter decreasing state is entered and the confidence value is decreased, for example, the confidence value is decreased in a linear decreasing, non-linear decreasing, or proportional decay manner, such as dividing the confidence counter by 2. When the confidence value is greater than or equal to the third threshold value, the pointer array type memory access mode is identified. At this time, the end state is entered, an end signal is sent, and the identification process of the pointer array type memory access mode is completed. In this embodiment, the increasing or decreasing manner of the confidence value is not limited to the above manner, and the third threshold value can be set as a static threshold value or an adaptive dynamic threshold value to balance the identification accuracy and speed. For example, the static threshold value can be set in combination with hardware resources such as memory consumption or counter bit width. For example, the adaptive dynamic threshold value can be set based on the historical mode frequency (if a certain instruction frequently triggers the pointer array type memory access mode, the threshold value can be dynamically increased to reduce misjudgment), or the threshold value is set according to the rules of increasing or decreasing the confidence value, and the present application is not limited thereto.

[0098] In addition, in this embodiment, the third identification unit 1103 analyzes the current access address in the required access trace each time, which is stored in the first data storage unit 1201, and the historical access read / write values in the preset number of stride access modes, which are stored in the fifth data storage unit 1205 that is specially used to store the historical access read / write values in the stride access modes that have been judged. The output updated confidence value, the flag of the confidence counter 1303, and other data can be stored in the fifth data storage unit 1205, supporting multiple instruction parallel access.

[0099] In an embodiment, the fourth identification unit 1104 is configured to identify the normal pointer type memory access mode by matching the current memory access address in the memory access trace with a preset number of historical memory read / write values, increasing the confidence value if a match is detected, decreasing the confidence value if a match is not detected and the confidence value is less than a fourth threshold value, and identifying the normal pointer type memory access mode when the confidence value is greater than or equal to the fourth threshold value. Specifically, the fourth identification unit 1104 inputs include the current memory access address, the preset number of historical memory read / write values, a clock signal, an enable signal, and the current confidence value of the instruction. The output signals include the updated confidence value and the flag of the confidence counter 1304. In the determination of the normal pointer type memory access mode, the current memory access address in the memory access trace can be related to the historical memory read / write values, and therefore the above signals are required as inputs. In order to improve the analysis efficiency, the historical memory read / write values of the last 32 instructions can be selected for analysis at one time, which significantly improves the processing rate. The number of 32 historical memory read / write values is an adjustable parameter and can be configured according to actual requirements. The logic of the fourth identification unit 1104 is implemented by a state machine, and a match success flag is set. The match success flag is compared with the preset number of historical memory read / write values by combination logic, and if a match is successful, the flag is set to high. The state machine includes four main states: an idle state, a confidence counter increasing state, a confidence counter decreasing state, and an end state. In the idle state, the enable signal is triggered. In the confidence counter increasing state, if the current memory access address matches the preset number of historical memory read / write values, the confidence value is increased, for example, by linearly increasing, nonlinearly increasing, or conditionally increasing, such as adding one to the confidence counter. In the confidence counter decreasing state, if no match occurs and the confidence value is less than the fourth threshold value, the confidence value is decreased, for example, by linearly decreasing, nonlinearly decreasing, or proportionally decreasing, such as dividing the confidence counter by two. When the confidence value is greater than or equal to the fourth threshold value, the normal pointer type memory access mode is identified. At this time, the end state is entered, an end signal is sent, and the identification process of the normal pointer type memory access mode is completed. In this embodiment, the increasing or decreasing method of the confidence value is not limited to the above method, and the fourth threshold value can be set as a static threshold value or an adaptive dynamic threshold value to balance the identification accuracy and speed. For example, a static threshold value can be set in combination with hardware resources such as memory consumption or counter bit width. For example, an adaptive dynamic threshold value can be set based on historical mode frequency (if a certain instruction frequently triggers the normal pointer type memory access mode, the threshold value can be dynamically increased to reduce misjudgment), or the threshold value can be set according to the rules of confidence value increase or decrease, and the present application is not limited thereto.

[0100] In addition, in this embodiment, the fourth identification unit 1104 can store the data required for each analysis, such as the current memory address, the preset number of historical memory read / write values, the updated confidence value, the flag of the confidence counter 1304, and the like in the third data storage unit 1203, to support multiple instruction parallel access.

[0101] In an embodiment, the fifth identification unit 1105 is configured to identify the structure pointer type memory access mode, and is configured to: calculate the absolute difference between the current memory access address in the memory access trace and a preset number of historical memory read / write values as a first difference, and compare the first difference with a preset difference threshold value, if greater than or equal to the preset difference threshold value, increase the confidence value, otherwise decrease the confidence value; and when the confidence value is greater than or equal to a fifth threshold value, identify the structure pointer type memory access mode. The input signals of the fifth identification unit 1105 include: the current memory access address, the preset number of historical memory read / write values, the clock signal, the enable signal, and the current confidence value of the instruction. The output signals include: the updated confidence value and the flag bit of the confidence counter 1305. The determination of the structure pointer type memory access mode and the ordinary pointer type memory access mode is similar. In order to improve the analysis efficiency, the historical memory read / write values of the last 32 instructions can be input at one time for analysis, which significantly improves the processing rate. The number of 32 historical memory read / write values is an adjustable parameter, which can be configured according to actual needs. The logic of the fifth identification unit 1105 is similar to that of the fourth identification unit 1104, and both are implemented by a state machine. The main difference lies in the different conditions for jumping from the idle state to the confidence counter addition and subtraction state. For the fifth identification unit 1105, the absolute difference between the current memory access address in the memory access trace and a preset number of historical memory read / write values is calculated as a first difference, and the first difference is compared with a preset difference threshold value. If the first difference is greater than or equal to the preset difference threshold value, the confidence value is increased, for example, increased in a linear, nonlinear or conditional manner, such as increasing the confidence counter by one. If the first difference is less than the preset difference threshold value, the confidence value is decreased, for example, decreased in a linear, nonlinear or proportional manner, such as dividing the confidence counter by two. When the confidence value is greater than or equal to the fifth threshold value, the structure pointer type memory access mode is identified. At this time, the end state is entered, the end signal is sent, and the identification process of the structure pointer type memory access mode is completed. In this embodiment, the increasing or decreasing manner of the confidence value is not limited to the above manner, and the fifth threshold value can be set as a static threshold value or an adaptive dynamic threshold value to balance the identification accuracy and speed. For example, a static threshold value can be set in combination with hardware resources such as memory consumption or counter bit width. For example, based on the historical mode frequency (if a certain instruction frequently triggers the structure pointer type memory access mode, the threshold value can be dynamically increased to reduce misjudgment), or the threshold value is set as an adaptive dynamic threshold value according to the confidence increasing or decreasing rule, etc. The present application is not limited thereto.

[0102] In addition, in the embodiment, the fifth identification unit 1105 shares the third data storage unit 1203 with the fourth identification unit 1104, and the current access address, the preset number of historical access read-write values, and the updated confidence value, the flag of the confidence counter 1305, and the like in the access trace required for each analysis can be stored in the third data storage unit 1203, thereby supporting multiple instruction parallel access.

[0103] In an embodiment, the sixth identification unit 1106 is configured to identify the pointer chasing type access mode, and is configured to: calculate the difference between the access address and the access read-write value of each time of the same instruction in the access trace as a second difference value, compare whether the second difference value of the current time and the last time is consistent, if the second difference value of the current time and the last time is consistent, increase the confidence value; if the second difference value of the current time and the last time is inconsistent, and the confidence value is less than a sixth threshold value, decrease the confidence value; and when the confidence value is greater than or equal to the sixth threshold value, identify the pointer chasing type access mode. Specifically, the input signals of the sixth identification unit 1106 include: the current access address, the access read-write value of the same instruction, the clock signal, the enable signal, and the current confidence value of the instruction; and the output signals include: the updated confidence value, and the flag of the confidence counter 1306. In the timing circuit part, the sixth identification unit 1106 is implemented by using a state machine, and four states are configured, including an idle state, a confidence counter increasing state, a confidence counter decreasing state, and an end state. In the idle state, the enable signal is waited for triggering. In the confidence counter increasing state, the difference between the access address and the access read-write value of each time of the same instruction in the access trace is calculated as a second difference value, and each time is compared with the second difference value, that is, if the second difference value of the current time and the last time is consistent, the confidence value is increased, for example, in a linear increasing, non-linear increasing, or conditional increasing manner, such as increasing the confidence counter by one. In the confidence counter decreasing state, if the second difference value of the current time and the last time is inconsistent, and the confidence value is less than the sixth threshold value, the confidence value is decreased, for example, in a linear decreasing, non-linear decreasing, or proportional decay manner, such as dividing the confidence counter by two. When the confidence value is greater than or equal to the sixth threshold value, the pointer chasing type access mode is identified. At this time, the end state is entered, an end signal is sent, and the identification process of the pointer chasing type access mode is completed. In the embodiment, the increasing or decreasing manner of the confidence value is not limited to the above manner, and the sixth threshold value can be set as a static threshold value or an adaptive dynamic threshold value to balance the identification accuracy and speed. For example, a static threshold value can be set in combination with hardware resources, such as memory consumption or counter bit width. For example, the adaptive dynamic threshold value can be set based on the historical mode frequency (if a certain instruction frequently triggers the pointer chasing type access mode, the threshold value can be dynamically increased to reduce misjudgment), or the threshold value can be set according to the rules of confidence value increase or decrease, and the present application is not limited thereto.

[0104] In addition, in this embodiment, the sixth identification unit 1106 can store the data of the memory access address and the memory read / write value of each time of the same instruction in the required memory access trace, and the updated confidence value, the flag of the confidence counter 1306, and the like, which are output each time, in the fourth data storage unit 1204.

[0105] In an embodiment, the seventh identification unit 1107 is configured to identify the indirect access mode, and is configured to: calculate a difference between the current access address in the access trace and the historical access address of the same instruction as a third difference; calculate a stride difference between the historical access read-write values in the preset number of stride access modes as a fourth difference; increase the confidence value if a proportional relationship between the third difference and the fourth difference meets a preset proportional factor; decrease the confidence value if the proportional relationship does not meet the preset proportional factor and the confidence value is less than a seventh threshold value; and identify the indirect access mode when the confidence value is greater than or equal to the seventh threshold value. Specifically, the input signals of the seventh identification unit 1107 include: the current access address, the historical access address of the same instruction, the historical access read-write values in the preset number of stride access modes, a clock signal, an enable signal, and the current confidence value of the instruction; and the output signals include: the updated confidence value and a flag bit of the confidence counter 1307. The seventh identification unit 1107 splits and stores the historical access read-write values in the preset number (for example, 8) of stride access modes into registers through combinatorial logic. The difference between the current access address in the access trace and the historical access address of the same instruction (i.e., A[x]-A[y] in a high-level language) is calculated as the third difference, and the stride difference between the historical access read-write values in the preset number of stride access modes (i.e., B[i]-B[j] in a high-level language) is calculated as the fourth difference. The matching state of the proportional relationship between the third difference and the fourth difference and the preset proportional factor is recorded in a 1-bit matching register. If the proportional relationship between the third difference and the fourth difference meets the preset proportional factor (for example, {1, 2, 4, 8}), the confidence value is increased. If the proportional relationship does not meet the preset proportional factor and the confidence value is less than the seventh threshold value, the confidence value is decreased. In the timing circuit part, the seventh identification unit 1107 is implemented by using a state machine, and four states are provided, including an idle state, a confidence counter increasing state, a confidence counter decreasing state, and an end state. In the idle state, the state machine waits for the enable signal to trigger. When the enable signal is at a low level, the state machine remains in the idle state. In the confidence counter increasing state, if the matching register is at a high level, the state machine enters this state and increases the confidence value, for example, in a linear increasing, non-linear increasing, or conditional increasing manner, such as adding one to the confidence counter. In the confidence counter decreasing state, if the matching register is at a low level and the confidence value is less than the seventh threshold value, the state machine enters this state and decreases the confidence value, for example, in a linear decreasing, non-linear decreasing, or proportional decay manner, such as dividing the confidence counter by two. When the confidence value is greater than or equal to the seventh threshold value, the indirect access mode is identified. At this time, the end state is entered, the end signal is sent, and the identification process of the indirect access mode is completed. In this embodiment, the increasing or decreasing manner of the confidence value is not limited to the above manner, and the seventh threshold value can be set as a static threshold value or an adaptive dynamic threshold value to balance the identification accuracy and speed.For example, a static threshold can be set in combination with hardware resources, such as memory consumption or counter bit width, etc. For example, a self-adaptive dynamic threshold can be set based on historical mode frequency (if an indirect type memory access mode is frequently triggered by a certain instruction, the threshold can be dynamically increased to reduce misjudgment), or according to a rule of increasing or decreasing the confidence, etc. The present application is not limited thereto.

[0106] In addition, in the embodiment, the seventh identification unit 1107 analyzes the current memory access address in the required memory access trace and the address accessed by the same instruction last time, which are stored in the first data storage unit 1201, and the historical memory read / write values in the preset number of stride type memory access modes, which are stored in the fifth data storage unit 1205 specially storing the historical memory read / write values in the stride type memory access mode. The output updated confidence value, flag bit of the confidence counter 1307 and other data can be stored in the first data storage unit 1201 or the fifth data storage unit 1205, supporting multiple instruction parallel access.

[0107] In an embodiment, the eighth identification unit 1108 is configured to identify the heap memory access mode by calculating the ratio difference between the memory addresses of a given step in the same instruction interval in the memory access trace to determine whether the ratio difference satisfies the characteristics of the heap memory access mode, and if so, increasing the confidence value, and if not, decreasing the confidence value, and identifying the heap memory access mode when the confidence value is greater than or equal to the eighth threshold value. Specifically, the input signals of the eighth identification unit 1108 include the long memory address, the clock signal, the enable signal, and the current confidence value of the instruction, and the output signals include the updated confidence value and the flag of the confidence counter 1308. The eighth identification unit 1108 records the matching state in a 1-bit matching register by calculating whether the ratio difference between the memory addresses of a given step in the same instruction interval in the memory access trace satisfies the characteristics of the heap memory access mode. In the timing circuit part, the eighth identification unit 1108 is implemented by using a state machine, which includes four states: an idle state, a confidence counter increasing state, a confidence counter decreasing state, and an end state. In the idle state, the state machine waits for the enable signal to trigger. When the enable signal is low, the state machine remains in the idle state. In the confidence counter increasing state, if the matching register is high, the state machine enters this state and increases the confidence value, for example, by linearly increasing, non-linearly increasing, or conditionally increasing, such as adding one to the confidence counter. In the confidence counter decreasing state, if the matching register is low and the confidence value is less than the eighth threshold value, the state machine enters this state and decreases the confidence value, for example, by linearly decreasing, non-linearly decreasing, or proportionally decreasing, such as dividing the confidence counter by two. When the confidence value is greater than or equal to the eighth threshold value, the heap memory access mode is identified. At this time, the state machine enters the end state, sends an end signal, and completes the identification process of the heap memory access mode. In this embodiment, the increasing or decreasing method of the confidence value is not limited to the above method, and the eighth threshold value can be set as a static threshold value or an adaptive dynamic threshold value to balance the identification accuracy and speed. For example, the static threshold value can be set in combination with hardware resources, such as memory consumption or counter bit width. For example, the adaptive dynamic threshold value can be set based on historical mode frequency (if a certain instruction frequently triggers the heap memory access mode, the threshold value can be dynamically increased to reduce false positives), or the confidence value increasing or decreasing rule, without being limited to the above.

[0108] In addition, in this embodiment, the current memory access address and the historical memory access address of the same instruction required by the eighth identification unit 1108 for analysis each time are stored in the second data storage unit 1202, and the output data such as the updated confidence value and the flag of the confidence counter 1308 can be stored in the second data storage unit 1202 to support multiple instruction parallel access.

[0109] In addition, in an embodiment, the confidence counter 130 is also configured with a hash collision processing unit for detecting the collision data of the same program counter (PC) index in the hash table and expelling the old data to write the new confidence counter. When the read request signal is triggered, the read signal of the internal hash table is pulled high, and the output result is obtained after the read signal is stabilized by two-stage flip-flop. When the write request signal is triggered, the write signal of the internal hash table is pulled high, and the write operation is completed after the write signal is stabilized by two-stage flip-flop, and the write end signal is outputted. If the hash position of the write has existed other PC corresponding data, the data is expelled and outputted.

[0110] In an embodiment, the logic of the control unit 140 is implemented by a state machine. When the reset signal is triggered, the control unit 140 resets the current state to the reset state and sends the reset signal to the confidence counter 130. Subsequently, the state machine jumps to the second phase of the reset, and the read signal of the confidence counter 130 is pulled high. When the read end signal transmitted by the confidence counter 130 is received, the state machine jumps to the reset state of the memory access pattern recognition unit 110, resets the state machine of each memory access pattern recognition unit 110, and pulls high the read data signal of each memory access pattern recognition unit 110 to read the data from the data storage unit 120.

[0111] When the data reading of all memory access pattern recognition units 110 is completed, the state machine enters the next state, and the enable signal of each memory access pattern recognition unit 110 is pulled high to identify each memory access pattern. When the processing end signal of a certain memory access pattern recognition unit 110 is received, the control unit 140 pulls high the corresponding write data signal to write the updated data to the corresponding data storage unit 120. When the write operation of all memory access pattern recognition units 110 is completed, the state machine enters the next state to write the updated confidence values of each memory access pattern to the corresponding confidence counter 130. At this point, the processing flow of a memory access trace is completed.

[0112] It should be noted that the fifth data unit 1105 shared by the third recognition unit 1103 and the seventh recognition unit 1107 needs to rely on the result of the stride type recognition of the second recognition unit 1102, so the enable signal of the fifth data unit 1105 is pulled high only after the identification of the second recognition unit 1102 is completed.

[0113] In one embodiment, the input / output interface unit is connected to multiple data storage units 120, multiple confidence counters 130, and an external storage medium 160. It supports user-defined protocols, FIFO buffering, and bus protocols. Specifically, the input interface unit 1501 retrieves memory access trace data stored in the external storage medium 160 and temporarily stores it in the data storage unit 120. The memory access pattern recognition unit 110 then performs memory access pattern recognition, generating intermediate data that is stored in the data storage unit 120. The output interface unit 1502 outputs the final recognized memory access pattern and confidence value, storing it in the external storage medium 160 or a computer. This data can then be visualized using data analysis tools. Specifically, the output interface unit 1502 outputs each memory access pattern and its corresponding confidence value as structured data. Through visualization tools, users can intuitively view the distribution of each memory access pattern, hotspot areas, and their confidence change trends, thereby providing data support for program optimization, hardware design debugging, and performance analysis.

[0114] In summary, the hardware-based memory access pattern recognition device provided by this invention defines eight memory access patterns to meet the recognition requirements of different memory access patterns: static memory access pattern, strafing memory access pattern, ordinary pointer memory access pattern, structure pointer memory access pattern, pointer chasing memory access pattern, indirect memory access pattern, pointer array memory access pattern, and heap memory access pattern. Based on hardware RTL implementation, it designs a dedicated storage structure and read / write control logic, including a block-shared storage unit and a parallel recognition unit. By optimizing the data storage and access process, the efficiency of memory access pattern recognition is significantly improved, while reducing hardware resource consumption and achieving high resource utilization.

[0115] Example 3:

[0116] The following are method embodiments corresponding to the above-described device embodiments, such as... Figure 3 As shown, Figure 3 A schematic flowchart of a hardware-based memory access pattern recognition method according to an embodiment of the present invention is shown. This method embodiment can be implemented in conjunction with the above-described device embodiment. The relevant technical details mentioned in the above device embodiment remain valid in this method embodiment, and will not be repeated here to avoid repetition.

[0117] A hardware-based memory access pattern recognition method specifically includes the following steps:

[0118] Step S1: Receive memory access trace data from the application and store it in each data storage unit.

[0119] Step S2, the control unit triggers each access pattern recognition unit and each confidence counter, calls the access trace to determine the confidence value recorded by the confidence counter according to the preset pattern recognition strategy, and recognizes each type of access pattern.

[0120] In an embodiment, the identification of the indirect access pattern and the identification of the pointer array type access pattern depend on the identification result of the stride type access pattern, so the identification of the stride type access pattern is triggered first, and then the identification of the pointer array type access pattern or the indirect access pattern is triggered. For example, the static type, stride type, normal pointer type, pointer chasing type, structure pointer type access pattern, and heap access pattern can be identified in parallel, and after the identification of the six types of access patterns is completed, the confidence values corresponding to the six types of patterns are updated first, and then the parallel identification of the indirect type and the pointer array type access pattern is performed. Finally, the confidence values corresponding to the two types of patterns are updated, and whether it belongs to the corresponding mode is output according to whether the confidence values corresponding to each mode reach the threshold value of each mode.

[0121] In an embodiment, the preset pattern recognition strategy includes:

[0122] The first identification strategy is used to identify the static type access pattern, and the first identification strategy is configured to compare the consistency of the current access address in the access trace and the historical access address of the same instruction, increase the confidence value if consistent, otherwise decrease the confidence value; and when the confidence value is greater than or equal to a first threshold value, it is identified as a static type access pattern.

[0123] The second identification strategy is used to identify the stride type access pattern, and the second identification strategy is configured to calculate the difference between the access addresses of the same instruction in the access trace at a given stride, verify whether the difference is continuous and consistent; if the difference is continuous and consistent, the confidence value is increased, otherwise the confidence value is decreased; and when the confidence value is greater than or equal to a second threshold value, it is identified as a stride type access pattern.

[0124] The third identification strategy is used to identify the pointer array type access pattern, and the third identification strategy is configured to perform matching detection on the current access address in the access trace and the historical access read-write value in the preset number of stride type access patterns, increase the confidence value if the matching detection is successful, and decrease the confidence value if the matching detection fails and the confidence value is less than a third threshold value; and when the confidence value is greater than or equal to the third threshold value, it is identified as a pointer array type access pattern.

[0125] A fourth identification strategy is configured to identify the normal pointer type memory access mode, and the fourth identification strategy is configured to: perform matching detection on the current memory access address in the memory access trace and a preset number of historical memory read-write values; increase the confidence value if the matching detection is successful; decrease the confidence value if the matching detection is failed and the confidence value is less than a fourth threshold value; and identify the normal pointer type memory access mode when the confidence value is greater than or equal to the fourth threshold value.

[0126] A fifth identification strategy is configured to identify the structure pointer type memory access mode, and the fifth identification strategy is configured to: calculate an absolute difference value between the current memory access address in the memory access trace and a preset number of historical memory read-write values as a first difference value, and compare the first difference value with a preset difference threshold value; increase the confidence value if the first difference value is greater than or equal to the preset difference threshold value; otherwise, decrease the confidence value; and identify the structure pointer type memory access mode when the confidence value is greater than or equal to a fifth threshold value.

[0127] A sixth identification strategy is configured to identify the pointer chasing type memory access mode, and the sixth identification strategy is configured to: calculate a difference value between the memory access address and the memory read-write value of the same instruction in the memory access trace as a second difference value; compare whether the second difference values of the current time and the last time are the same; increase the confidence value if the second difference values are consistent; decrease the confidence value if the second difference values are inconsistent and the confidence value is less than a sixth threshold value; and identify the pointer chasing type memory access mode when the confidence value is greater than or equal to the sixth threshold value.

[0128] A seventh identification strategy is configured to identify the indirect type memory access mode, and the seventh identification strategy is configured to: calculate a difference value between the current memory access address in the memory access trace and the historical memory access address of the same instruction as a third difference value; calculate a stride difference value of the historical memory read-write value in the preset number of stride type memory access modes as a fourth difference value; increase the confidence value if the proportional relationship between the third difference value and the fourth difference value meets a preset proportional factor; decrease the confidence value if the proportional relationship does not meet the preset proportional factor and the confidence value is less than a seventh threshold value; and identify the indirect type memory access mode when the confidence value is greater than or equal to the seventh threshold value.

[0129] An eighth identification strategy is configured to identify the heap memory access mode, and the eighth identification strategy is configured to: calculate whether a proportional difference value between the memory access addresses of the same instruction in the memory access trace meets the characteristics of the heap; increase the confidence value if the proportional difference value meets the characteristics of the heap; decrease the confidence value if the proportional difference value does not meet the characteristics of the heap; and identify the heap memory access mode when the confidence value is greater than or equal to an eighth threshold value.

[0130] The technical details of the above-mentioned various memory access mode identification in the second embodiment are still valid in the various identification strategies of the method. In order to reduce repetition, the details are not described here.

[0131] It should also be understood that, in various embodiments of the present application, the magnitude of the serial number of each process described above does not mean the order of execution, and the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0132] In addition, it should be understood that the storage medium in the device embodiment of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM) and direct rambus RAM (DR RAM).

[0133] Although the embodiments of the present application have been disclosed as above, it is not limited only to the application listed in the specification and embodiments, and can be fully applied to various fields suitable for the present application, and additional modifications can be easily implemented by those skilled in the art, and therefore the present application is not limited to specific details and the figures shown and described herein, without departing from the general concept defined by the claims and the equivalent scope.

Claims

1. A hardware-based memory access pattern recognition device, characterized in that, include: Multiple parallel memory access pattern recognition units, each implemented through independent state machine logic, are configured to dynamically adjust the confidence value recorded by the confidence counter according to the memory access traces of the application to identify memory access patterns. Multiple data storage units employing a block storage structure are connected to multiple memory access pattern recognition units. Some of the memory access pattern recognition units share the same data storage unit, which is used to store the memory access traces and intermediate data output by each memory access pattern recognition unit. Multiple confidence counters, each confidence counter is connected to one of the memory access mode identification units, which are used to record the confidence value of each memory access mode using the program counter as an index; The control unit is connected to multiple memory access pattern recognition units, multiple data storage units, and multiple confidence counters, and is used to coordinate the working timing of the memory access pattern recognition units, data storage units, and confidence counters. The memory access mode recognition unit, data storage unit, confidence counter, and control unit are all implemented using hardware RTL. The plurality of data storage units include: The first data storage unit is connected to the first identification unit and the seventh identification unit, and the first identification unit and the seventh identification unit share the first data storage unit. The second data storage unit is connected to the second identification unit and the eighth identification unit, and the second identification unit and the eighth identification unit share the second data storage unit. The third data storage unit is connected to the fourth identification unit and the fifth identification unit, and the fourth identification unit and the fifth identification unit share the third data storage unit; The fourth data storage unit is connected to the sixth identification unit; The fifth data storage unit is connected to the third identification unit and the seventh identification unit, and the third identification unit and the seventh identification unit share the fifth data storage unit.

2. The apparatus according to claim 1, characterized in that, The memory access mode identification unit includes a first identification unit for identifying static memory access modes, configured as follows: The consistency between the current memory access address in the memory access trace and the historical memory access address of the same instruction is compared. If they are consistent, the confidence value is increased; otherwise, the confidence value is decreased. When the confidence value is greater than or equal to the first threshold, it is identified as a static memory access mode.

3. The apparatus according to claim 2, characterized in that, The memory access mode identification unit includes a second identification unit for identifying strafing memory access modes, configured as follows: Calculate the difference between memory access addresses with the same instruction interval and a given step size in the memory access trace, and verify whether the difference is continuous and consistent; If the differences are consecutive and consistent, the confidence value is increased; otherwise, the confidence value is decreased. When the confidence value is greater than or equal to the second threshold, it is identified as a strafing memory access mode.

4. The apparatus according to claim 3, characterized in that, The memory access pattern recognition unit includes: The third identification unit for identifying pointer array type memory access patterns is configured to: perform a matching detection between the current memory access address in the memory access trace and a preset number of historical memory access read / write values ​​under the step-type memory access pattern; if a successful match is detected, the confidence value is increased; if a failed match is detected and the confidence value is less than a third threshold, the confidence value is decreased. When the confidence value is greater than or equal to the third threshold, it is identified as a pointer array type memory access mode; The fourth identification unit, used to identify ordinary pointer-type memory access patterns, is configured to: perform a matching detection between the current memory access address in the memory access trace and a preset number of historical memory access read / write values; if a successful match is detected, increase the confidence value; if a failed match is detected and the confidence value is less than a fourth threshold, decrease the confidence value; when the confidence value is greater than a certain threshold... At the fourth threshold, it is identified as a normal pointer-type memory access mode; The fifth identification unit for identifying structure pointer-type memory access patterns is configured to: calculate the absolute difference between the current memory access address and a preset number of historical memory access read / write values ​​in the memory access trace as a first difference, and compare the first difference with a preset difference threshold. If the first difference is greater than or equal to the preset difference threshold, the confidence value is increased; otherwise, the confidence value is decreased. When the confidence value is greater than or equal to the fifth threshold, it is identified as a structure pointer type memory access mode; The sixth identification unit, used to identify pointer-chasing memory access patterns, is configured to: calculate the difference between the memory access address and the memory read / write value for each instance of the same instruction in the memory access trace as a second difference; compare the second difference calculated in the current instance with that calculated in the previous instance; if the second difference remains the same, increase the confidence value; if the second difference remains different, increase the confidence value. If the confidence value is less than the sixth threshold, the confidence value is reduced; if the confidence value is greater than or equal to the sixth threshold, it is identified as a pointer-chasing memory access mode.

5. The apparatus according to claim 4, characterized in that, The memory access pattern recognition unit includes: The seventh identification unit, used to identify indirect memory access patterns, is configured as follows: The difference between the current memory access address and the historical memory access address of the same instruction in the memory access trace is calculated as the third difference; The step difference of historical memory access read and write values ​​under a preset number of step-type memory access modes is used as the fourth difference; If the ratio between the third difference and the fourth difference conforms to a preset ratio factor, then the confidence value is increased. If the preset scaling factor is not met and the confidence value is less than the seventh threshold, then the confidence value is reduced. When the confidence value is greater than or equal to the seventh threshold, it is identified as an indirect memory access mode; The eighth identification unit for identifying heap access patterns is configured to: calculate whether the proportional difference between memory addresses with the same instruction interval of a given step in the memory access trace satisfies the characteristics of a heap; if it satisfies, increase the confidence value; if it does not satisfy, decrease the confidence value; when the confidence value is greater than or equal to the eighth threshold, it is identified as a heap access pattern.

6. The apparatus according to claim 1, characterized in that, Also includes: The input / output interface unit is connected to multiple data storage units and multiple confidence counters, supports user-defined protocols, and is used to receive externally input memory access trace data and output the finally identified memory access mode and the confidence value of each memory access mode to the external storage medium or computer.

7. A hardware-based memory access pattern recognition method, characterized in that, Include: Receive memory access trace data from the application and store it in various data storage units; The control unit triggers each memory access pattern recognition unit and each confidence counter, and calls the memory access trace to determine the confidence value recorded by each confidence counter according to a preset pattern recognition strategy, thereby identifying each type of memory access pattern; wherein: The preset pattern recognition strategy includes: A second identification strategy is used to identify step-type memory access patterns. This strategy is configured to: calculate the difference between memory addresses accessed within the same instruction interval of a given step size in the memory access trace; verify whether the difference is continuous and consistent; if the difference is continuous and consistent, increase the confidence value; otherwise, decrease the confidence value; and identify the pattern when the confidence value is greater than or equal to a second threshold. It is a step-by-step memory access mode; The third identification strategy is used to identify pointer array-type memory access patterns. This strategy is configured to: perform a matching test between the current memory access address in the memory access trace and a preset number of historical memory access read / write values ​​under the strafing memory access pattern; if a successful match is detected, the confidence value is increased; if a match fails and the confidence value is less than a third threshold, the confidence value is decreased. The confidence value; when the confidence value is greater than or equal to the third threshold, it is identified as a pointer array type memory access mode; A seventh identification strategy is used to identify indirect memory access patterns. This seventh identification strategy is configured as follows: calculating the difference between the current memory access address and the historical memory access address of the same instruction in the memory access trace as a third difference; calculating the step difference of historical memory access read / write values ​​under a preset number of step-type memory access patterns as a fourth difference; and if the ratio of the third difference to the fourth difference is... If the preset scaling factor is met, the confidence value is increased; if the preset scaling factor is not met and the confidence value is less than the seventh threshold, the confidence value is decreased; when the confidence value is greater than or equal to the seventh threshold, it is identified as an indirect memory access mode. The eighth identification strategy, used to identify heap access patterns, is configured as follows: calculate whether the proportional difference between memory addresses with the same instruction interval of a given step in the memory access trace satisfies the characteristics of a heap; if it satisfies, increase the confidence value; if it does not satisfy, decrease the confidence value; when the confidence value is greater than or equal to the eighth threshold, it is identified as a heap access pattern.

8. The method according to claim 7, characterized in that, Prioritize triggering the identification of strafing memory access patterns, followed by triggering the identification of pointer array memory access patterns and indirect memory access patterns.

9. The method according to claim 8, characterized in that, The preset pattern recognition strategy includes: A first identification strategy is used to identify static memory access patterns. The first identification strategy is configured to: compare the consistency between the current memory access address in the memory access trace and the historical memory access address of the same instruction; if they are consistent, increase the confidence value; otherwise, decrease the confidence value; when the confidence value is greater than or equal to a first threshold, it is identified as a static memory access pattern. The fourth identification strategy is used to identify ordinary pointer-type memory access patterns. The fourth identification strategy is configured as follows: matching the current memory access address in the memory access trace with a preset number of historical memory access read and write values; if a successful match is detected, the confidence value is increased; if a failed match is detected and the confidence value is less than the fourth threshold, the confidence value is decreased. When the confidence value is greater than or equal to the fourth threshold, it is identified as a normal pointer-type memory access mode; The fifth identification strategy is used to identify structure pointer-type memory access patterns. This fifth identification strategy is configured as follows: Calculate the absolute difference between the current memory access address and a preset number of historical memory access read / write values ​​in the memory access trace as a first difference value, and compare this first difference value with a preset difference threshold. If the first difference value is greater than or equal to the preset difference threshold, increase the confidence value; otherwise, decrease the confidence value. Confidence level; When the confidence value is greater than or equal to the fifth threshold, it is identified as a structure pointer type memory access mode; The sixth identification strategy is used to identify pointer-chasing memory access patterns. The sixth identification strategy is configured as follows: calculate the difference between the memory access address and the memory access read / write value of the same instruction in the memory access trace as the second difference, compare whether the second difference calculated in the current time is the same as that calculated in the previous time, and if the second difference is consistent, increase the confidence value. If the second If the difference is inconsistent and the confidence value is less than the sixth threshold, the confidence value is reduced; if the confidence value is greater than or equal to the sixth threshold, it is identified as a pointer-chasing memory access mode.

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