Method and device for calibrating chip clock based on serial port communication

Abstract

The invention belongs to the technical field of clock calibration, and discloses a method and device for calibrating a chip clock based on serial port communication, and the method comprises the steps: obtaining a preset calibration frame on a bus and a unit count value of the preset calibration frame; calculating the current clock frequency of the chip according to the unit count value; calculating an error between the current clock frequency and the target clock frequency; if the error is greater than a preset normal threshold value, inputting the current clock frequency into a clock trimming function curve to obtain a first trimming value; inputting the target clock frequency into the clock trimming function curve to obtain a second trimming value; calculating a trimming difference value between the first trimming value and the second trimming value; and compensating a trim register of the chip according to the trimming difference value. According to the invention, the clock frequency of the chip can be calibrated under the condition that a hardware circuit is not modified and an external clock source is not utilized.

Description

Technical Field

[0001] This application relates to the technical field of clock calibration, and particularly to a method and device for calibrating a chip clock based on serial communication. Background Art

[0002] In various embedded systems and low-power devices, the RCH clock is often used to generate the system clock or as a timing reference in the low-power mode, which not only saves the space of the hardware circuit but also saves a part of the hardware cost. However, the frequency of the RCH clock is easily affected by temperature and humidity changes, manufacturing processes, and component aging, resulting in a decrease in clock accuracy. Such deviation may affect the performance and stability of the system. Especially in applications that require high-precision timing, it may cause abnormal operation of peripherals such as UART, TIMER, and LPTIMER, leading to business logic errors. Therefore, it is very necessary to calibrate the RCH clock to improve its frequency stability and accuracy.

[0003] Most of the existing methods for calibrating the internal RCH clock of a chip are based on an existing accurate external high-speed clock, that is, using a reference clock. For example, a chip with a relatively high clock main frequency is mostly used to provide the clock source for the chip to be calibrated (the purpose is to minimize the clock error of capture and sampling) to capture the internal RCH clock output by the chip to be calibrated. Since some products do not consider the situation of internal RCH clock offset during application, there is no redundant interface at the hardware level to calibrate the clock. Moreover, even if there are extra interface pins, additional external clock devices are required, which undoubtedly increases the cost. Summary of the Invention

[0004] This application provides a method and device for calibrating a chip clock based on serial communication, which can calibrate the clock frequency of the chip itself without modifying the hardware circuit and without using an external clock source.

[0005] In a first aspect, an embodiment of this application provides a method for calibrating a chip clock based on serial communication, including:

[0006] Obtaining a preset calibration frame on the bus and the unit count value of the preset calibration frame;

[0007] Calculating the current clock frequency of the chip according to the unit count value;

[0008] Calculating the error between the current clock frequency and the target clock frequency;

[0009] If the error is greater than a preset normal threshold, inputting the current clock frequency into the clock trimming function curve to obtain a first trimming value; inputting the target clock frequency into the clock trimming function curve to obtain a second trimming value;

[0010] Calculate the trimming difference between the first trimming value and the second trimming value;

[0011] Compensate the trim register of the chip according to the trimming difference.

[0012] Furthermore, the obtaining of the preset calibration frame and the unit count value of the preset calibration frame on the bus includes:

[0013] Obtain the data frame on the bus based on double-edge triggered capture;

[0014] Determine whether the data frame is equal to the preset calibration frame;

[0015] If so, calculate the unit count value of one bit according to the received count value of one byte.

[0016] Furthermore, the calculating of the current clock frequency of the chip according to the unit count value includes:

[0017] Obtain the preset baud rate; multiply the preset baud rate by the unit count value to obtain the current clock frequency.

[0018] Furthermore, the method further includes:

[0019] Obtain the normal counting range according to the preset baud rate, the maximum clock frequency and the minimum clock frequency of the chip;

[0020] After obtaining the unit count value, determine whether the unit count value is within the normal counting range;

[0021] If so, calculate the current clock frequency of the chip according to the unit count value.

[0022] Furthermore, the method further includes:

[0023] Obtain the reference data of the clock frequency and the register trimming value;

[0024] Fit the clock trimming function curve according to the reference data.

[0025] Furthermore, the method further includes:

[0026] After compensating the trim register, return to the step of obtaining the preset calibration frame on the bus;

[0027] If the error between the calculated current clock frequency and the target clock frequency is greater than the preset normal threshold, calculate the trimming difference again to compensate the trim register until the error is less than or equal to the preset normal threshold.

[0028] Furthermore, the preset calibration frame is 0x7F and the preset baud rate is 2400 bit / s.

[0029] In a second aspect, an embodiment of the present application provides a device for calibrating a chip clock based on serial communication, including:

[0030] A capture module, configured to obtain a preset calibration frame on the bus and the unit count value of the preset calibration frame;

[0031] A frequency calculation module, configured to calculate the current clock frequency of the chip according to the unit count value;

[0032] An error calculation module, configured to calculate the error between the current clock frequency and the target clock frequency;

[0033] A trimming module, configured to input the current clock frequency into a clock trimming function curve to obtain a first trimming value when the error is greater than a preset normal threshold; input the target clock frequency into the clock trimming function curve to obtain a second trimming value;

[0034] A difference calculation module, configured to calculate the trimming difference between the first trimming value and the second trimming value;

[0035] A compensation module, configured to compensate the trim register of the chip according to the trimming difference.

[0036] Further, the device further includes:

[0037] A count value judgment module, configured to obtain a normal counting range according to a preset baud rate, the maximum clock frequency and the minimum clock frequency of the chip; judge whether the unit count value is within the normal counting range, and if so, execute the frequency calculation module.

[0038] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of a method for calibrating a chip clock based on serial communication as described in any of the above embodiments are implemented.

[0039] In summary, compared with the prior art, the beneficial effects brought by the technical solution provided by the embodiment of the present application at least include:

[0040] A method for calibrating a chip clock based on serial communication provided by the embodiment of the present application enables the chip to use the serial communication of the host to capture a preset calibration frame on the host bus for self-clock calibration without modifying the hardware circuit and without using an external clock source. When performing calibration, since the change between the trimming value and the clock frequency is not linear, that is, changing a trimming value does not fixedly increase or decrease a fixed clock frequency, therefore, the present application adopts an idea of difference, that is, the difference in clock frequency corresponding to the difference between two trimming values is fixed, so as to compensate the trim register. Description of the Drawings

[0041] Figure 1Flowchart of a method for calibrating a chip clock based on serial port communication provided for an exemplary embodiment of the present application.

[0042] Figure 2 Schematic diagram of the frame format with a preset calibration frame of 0xA9 provided for an exemplary embodiment of the present application.

[0043] Figure 3 Curve graph of trimming value and clock frequency and linear function curve graph provided for an exemplary embodiment of the present application.

[0044] Figure 4 Polynomial curve graph of trimming value and clock frequency provided for an exemplary embodiment of the present application.

[0045] Figure 5 Piecewise polynomial curve graph of trimming value and clock frequency provided for an exemplary embodiment of the present application.

[0046] Figure 6 Structural diagram of a device for calibrating a chip clock based on serial port communication provided for an exemplary embodiment of the present application. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0048] Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0049] Please refer to Figure 1 , the embodiments of the present application provide a method for calibrating a chip clock based on serial port communication, including:

[0050] Step S11, obtaining a preset calibration frame on the bus and the unit count value of the preset calibration frame.

[0051] Specifically, the above-mentioned obtaining of the preset calibration frame on the bus and the unit count value of the preset calibration frame includes:

[0052] Step S111, capturing the data frame on the bus based on double-edge triggering;

[0053] Step S112, determining whether the data frame is equal to the preset calibration frame.

[0054] In practical applications, the chip is usually mounted on the bus, and there is usually more than one baud rate on the bus. Therefore, when calibrating the clock, the captured data frame is directly judged.

[0055] The commonly used baud rates in a general bus are 2400 bit / s, 9600 bit / s, and 19200 bit / s. These three baud rates transmit different data on the bus. To ensure that the chip can recognize the preset calibration frame, it is required that the preset calibration frame on the bus can only be sent at the preset baud rate.

[0056] Please refer to Figure 2 , assuming that the data of the preset calibration frame is 0xA9, the capture times can be set according to this data first. Assuming that the chip sets the capture condition as double-edge trigger capture, the data of the preset calibration frame will trigger 8 capture interrupts in this way. Arrange the time interval data of each captured frame in order, for example: start bit = bit 0 = (bit 1 + bit 2) / 2 = bit 3 = bit 4 = bit 5 = bit 6, so as to recognize 0xA9.

[0057] It can be understood that those skilled in the art can select the corresponding recognition algorithm according to the format of the preset calibration frame, so that the chip can recognize the preset calibration frame transmitted at the preset baud rate on the bus. Therefore, no more details will be elaborated here.

[0058] Step S113, if so, calculate the unit count value of one bit according to the received count value of one byte.

[0059] Specifically, by capturing the serial port data at 2400 baud rate, obtain the cnt count value (received count value) corresponding to one byte of the serial port captured by the current clock abnormal chip. After processing, obtain the cnt value of one bit (unit count value). The time Time corresponding to one bit can be calculated as follows:

[0060]

[0061] Step S12, calculate the current clock frequency of the chip according to the unit count value; specifically, obtain the preset baud rate; multiply the preset baud rate by the unit count value to obtain the current clock frequency.

[0062] Because:

[0063]

[0064] So it can be obtained that:

[0065] System clock = cnt × Uart Baud

[0066] Because Uart Baud is known to be 2400, and the unit count value cnt can be determined after the capture by the timer. After obtaining these two parameters, the current clock frequency System clock of the chip can be obtained.

[0067] Step S13: Calculate the error between the current clock frequency and the target clock frequency.

[0068] Step S14: If the error is greater than the preset normal threshold, input the current clock frequency into the clock trimming function curve to obtain a first trimming value; input the target clock frequency into the clock trimming function curve to obtain a second trimming value.

[0069] Specifically, reference data of the clock frequency and the register trimming value can be obtained; the clock trimming function curve is obtained by fitting according to the reference data. Since the data type of the frequency is floating-point and the code size occupied by one frequency is 4 bytes, the table below occupies 2KB in the code. Also, since the trim value corresponding to the current frequency needs to be quickly found in the code, some special processing is done on this table, so the actual size of this table in the code is much larger than 2KB. Therefore, this application uses a function to equivalently replace these pure data to achieve the purpose of reducing the code space.

[0070]

[0071] Please refer to Figure 3 , it can be clearly seen that the relationship between the clock frequency and the trimming value is not linear. Using a linear function for fitting has a poor fitting effect. Therefore, this application can use a polynomial for fitting to obtain a curve as shown in Figure 4 . It can be seen that the number of terms of the polynomial reaches 4, and the value of R 2 (goodness of fit) is close to 1. At this time, the relationship between the trim value and the frequency can be fitted more accurately. In this way, using multiple functions to fit the reference data can ensure the reduction of the code space.

[0072] Please refer to Figure 5 . One segment of the polynomial is obtained by segmentation: y = -1.13x^2 + 89.155x - 1587.1. It can be seen that R 2 is 1, indicating that the polynomial has a good fitting effect. By analogy, the remaining polynomials can be obtained.

[0073] Step S15: Calculate the trimming difference between the first trimming value and the second trimming value.

[0074] Step S16: Compensate the trim register of the chip according to the trimming difference.

[0075] Furthermore, after compensating the trim register, return to the step of obtaining the preset calibration frame on the bus, that is, step S11. If the calculated error between the current clock frequency and the target clock frequency is greater than the preset normal threshold, calculate the trimming difference again to compensate the trim register until the error is less than or equal to the preset normal threshold.

[0076] This application adopts the idea of difference. Assume that the current clock frequency of a chip with inaccurate RCH clock is 150 MHz, while the target clock frequency is 168 MHz. Determine what the trim value of the abnormal chip is at the clock frequency of 150 MHz according to the fitting function, find this trim value as the first trimming value, and then determine what the trim value of the abnormal chip is at the clock frequency of 168 MHz according to the fitting function, find this trim value as the second trimming value; take the difference between the first trimming value and the second trimming value, and the obtained difference is used as the trimming value for compensating the trim register of the abnormal chip. Repeat this process to correct the clock frequency of the abnormal chip back to the target clock frequency.

[0077] A method for calibrating the chip clock based on serial communication provided in the above embodiment enables the chip to use the serial communication of the host to capture the preset calibration frame on the host bus for calibrating its own clock without modifying the hardware circuit and without using an external clock source. When calibrating, since the relationship between the trimming value and the clock frequency is non-linear, this application adopts the idea of difference, that is, the difference in the clock frequency corresponding to the difference between two trimming values is fixed, so as to compensate the trim register.

[0078] In some embodiments, the method further includes:

[0079] Step S011, obtain the normal counting range according to the preset baud rate, the maximum clock frequency and the minimum clock frequency of the chip.

[0080] Step S012, after obtaining the unit count value, determine whether the unit count value is within the normal counting range.

[0081] Step S013, if so, calculate the current clock frequency of the chip according to the unit count value.

[0082] Specifically, the internal RCH clock deviation of the chip cannot ensure that all chips with abnormal frequencies can be corrected back to the normal frequency. If the frequency deviation is too large, there may already be some problems with the chip itself. Therefore, this application limits the calibration range of the clock frequency of the abnormal chip, and calibration will no longer be started if it exceeds this range.

[0083] According to the relationship between the trimming value and the clock frequency, it is possible to know the maximum and minimum clock frequencies that can be obtained by changing the trim value. Then, based on the maximum and minimum clock frequencies, the following formula can be used:

[0084]

[0085] When the UartReg (UART baud rate register) remains unchanged, changing the chip clock between the maximum and minimum values can obtain the maximum and minimum values of the corresponding UART baud rate, and vice versa. This application aims to determine whether the maximum and minimum values of this baud rate will be misidentified as other baud rates. Therefore, this application first obtains the maximum and minimum values of the unit count value based on the maximum and minimum values of the clock frequency and the preset baud rate, and then makes a judgment on the captured unit count value to determine whether it falls within the unit count value corresponding to the maximum and minimum clock frequencies. If so, the current clock frequency is calculated for further judgment.

[0086] Please refer to Figure 6 , another embodiment of this application provides a device for calibrating a chip clock based on serial communication, including:

[0087] A capture module 101, configured to obtain a preset calibration frame on the bus and the unit count value of the preset calibration frame.

[0088] A frequency calculation module 102, configured to calculate the current clock frequency of the chip according to the unit count value.

[0089] An error calculation module 103, configured to calculate the error between the current clock frequency and the target clock frequency.

[0090] An adjustment module 104, configured to input the current clock frequency into a clock adjustment function curve to obtain a first adjustment value when the error is greater than a preset normal threshold; input the target clock frequency into the clock adjustment function curve to obtain a second adjustment value.

[0091] A difference calculation module 105, configured to calculate the adjustment difference between the first adjustment value and the second adjustment value.

[0092] A compensation module 106, configured to compensate the trim register of the chip according to the adjustment difference.

[0093] In some embodiments, the device further includes:

[0094] A count value judgment module, configured to obtain a normal counting range according to the preset baud rate, the maximum clock frequency and the minimum clock frequency of the chip; judge whether the unit count value is within the normal counting range, and if so, execute the frequency calculation module.

[0095] The specific limitations provided in this embodiment for a device for calibrating a chip clock based on serial communication can be referred to the embodiment of the method for calibrating a chip clock based on serial communication in the above text, and will not be elaborated here. Each module in the above device for calibrating a chip clock based on serial communication can be implemented in whole or in part by software, hardware, and their combination.

[0096] An embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of a method for calibrating a chip clock based on serial communication as described in any of the above embodiments are implemented. Among them, the computer-readable storage medium refers to a carrier for storing data, which may include, but is not limited to, floppy disks, optical discs, hard disks, flash memories, USB flash drives, and / or memory sticks, etc. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. For the working process, working details, and technical effects of the computer-readable storage medium provided in this embodiment, reference may be made to the embodiments of the method for calibrating a chip clock based on serial communication in the foregoing text, and details are not repeated herein.

[0097] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0098] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for calibrating the chip clock based on serial port communication, characterized in that, Including: Obtain a preset calibration frame on the bus and the unit count value of the preset calibration frame; Calculate the current clock frequency of the chip according to the unit count value; Calculate the error between the current clock frequency and the target clock frequency; If the error is greater than a preset normal threshold, input the current clock frequency into the clock trimming function curve to obtain a first trimming value; Input the target clock frequency into the clock trimming function curve to obtain a second trimming value; Calculate the trimming difference between the first trimming value and the second trimming value; Compensate the trim register of the chip according to the trimming difference.

2. The method for calibrating a chip clock based on serial port communication according to claim 1, wherein The obtaining of the preset calibration frame on the bus and the unit count value of the preset calibration frame includes: Capture the data frame on the bus based on double-edge triggering; Determine whether the data frame is equal to the preset calibration frame; If so, calculate the unit count value of one bit according to the received count value of one byte.

3. The method for calibrating a chip clock based on serial port communication according to claim 2, wherein The calculating of the current clock frequency of the chip according to the unit count value includes: Obtain a preset baud rate; multiply the preset baud rate by the unit count value to obtain the current clock frequency.

4. The method for calibrating a chip clock based on serial port communication according to claim 3, wherein It further includes: Obtain the normal counting range according to the preset baud rate, the maximum clock frequency and the minimum clock frequency of the chip; After obtaining the unit count value, determine whether the unit count value is within the normal counting range; If so, calculate the current clock frequency of the chip according to the unit count value.

5. The method for calibrating the chip clock based on serial port communication according to claim 1, wherein It further includes: Obtain the reference data of the clock frequency and the register trimming value; Fit the clock trimming function curve according to the reference data.

6. The method for calibrating the chip clock based on serial port communication according to claim 1, wherein, It further includes: After compensating the trim register, return to the step of obtaining the preset calibration frame on the bus; If the error between the calculated current clock frequency and the target clock frequency is greater than the preset normal threshold, calculate the trimming difference again to compensate the trim register until the error is less than or equal to the preset normal threshold.

7. The method for calibrating a chip clock based on serial port communication according to claim 3, wherein The preset calibration frame is 0x7F, and the preset baud rate is 2400 bit / s.

8. A device for calibrating a chip clock based on serial port communication, characterized in that, Including: A capture module for obtaining a preset calibration frame on the bus and the unit count value of the preset calibration frame; A frequency calculation module for calculating the current clock frequency of the chip according to the unit count value; An error calculation module for calculating the error between the current clock frequency and the target clock frequency; A trimming module for inputting the current clock frequency into the clock trimming function curve to obtain a first trimming value when the error is greater than a preset normal threshold; Input the target clock frequency into the clock trimming function curve to obtain a second trimming value; A difference calculation module for calculating the trimming difference between the first trimming value and the second trimming value; A compensation module for compensating the trim register of the chip according to the trimming difference.

9. The device for calibrating the chip clock based on serial port communication according to claim 8, characterized in that, It further includes: A count value judgment module for obtaining the normal counting range according to the preset baud rate, the maximum clock frequency and the minimum clock frequency of the chip; Determine whether the unit count value is within the normal counting range, and if so, execute the frequency calculation module.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it realizes the steps of the method for calibrating the chip clock based on serial port communication as described in any one of claims 1 to 6.

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