DDR5 multi-particle independent port PDN impedance simulation optimization method and device

Abstract

The invention relates to the field of electronic circuit design, and particularly provides a DDR5 multi-particle independent port PDN impedance simulation optimization method and device, for a DDR5 power supply network needing to be simulated, an independent port is established for the power supply network of each Sink end, simulation is carried out, an independent PDN impedance curve is generated, and the PDN impedance curve is optimized. And finally, comparing the impedance curve with a specified target impedance curve, and performing independent optimization to ensure that the PDN impedance of each particle is within a target range, so that the power supply integrity and the signal integrity are improved. Compared with the prior art, the power supply integrity and the signal integrity can be improved through independent port simulation optimization, and the high performance and the stability of the system are ensured.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuit design, and specifically provides a method and device for optimizing the PDN impedance simulation of multiple independent ports of DDR5 chips. Background Art

[0002] DDR5 memory modules play an important role in high-performance computing and processor back-end applications. With the increase in data transmission rate, power integrity (PI) and signal integrity (SI) issues become more prominent.

[0003] Although traditional PDN design methods perform well in DDR4 and lower versions, at the high frequencies and high data rates of DDR5, there are some obvious drawbacks, such as insufficient simulation accuracy, inability to handle high-frequency effects, low optimization efficiency, etc.; especially in the case of multiple chips, the optimization of the PDN impedance simulation of independent ports is particularly important. Summary of the Invention

[0004] The present invention aims at the above-mentioned deficiencies of the prior art and provides a practical method for optimizing the PDN impedance simulation of multiple independent ports of DDR5 chips.

[0005] A further technical task of the present invention is to provide a device for optimizing the PDN impedance simulation of multiple independent ports of DDR5 chips, which is reasonable in design, safe and applicable.

[0006] The technical solution adopted by the present invention to solve its technical problems is as follows:

[0007] For the power network of DDR5 to be simulated, an independent port is established for the power network at each Sink end, and simulation is performed to generate an independent PDN impedance curve. Finally, it is compared with the specified target impedance curve respectively and optimized individually to ensure that the PDN impedance of each chip is within the target range, thereby improving power integrity and signal integrity.

[0008] Further, first, open the ADS software, create and save a project. Then, import the PCB file to be simulated. After importing the design, enter the stack-up design interface, adjust the parameters according to the actual PCB design, configure the material properties, input the dielectric constant and loss at different frequencies, and finally, start SIPro / PIPro, and select PI-AC analysis for the simulation type to extract the AC impedance characteristics of the PDN.

[0009] Further, the specific steps are as follows:

[0010] S1. Establishment of an independent port simulation model;

[0011] S2. Simulation settings;

[0012] S3. Simulation result analysis;

[0013] S4. Optimization strategy.

[0014] Further, in step S1, in the PI-AC analysis interface, select the power network and reference ground network to be simulated, clarify the power supply end VRM of this network, and use the software to automatically set the ports for the VRM. Clearly set the allowable fluctuation ranges of voltage and current, assign S-parameter models to the passive interconnect devices on the power network channel, and define independent power and ground ports for multiple power-consuming ends Sink, that is, this power network of DDR5 particles. That is, each Sink end will be automatically set as a PDN impedance observation port. When viewing the results, there will be as many impedance curves as there are Sink ends.

[0015] Further, in step S2, set the simulation frequency range from low frequency 1KHz to high frequency 1GHz, and set the global simulation parameters in the simulation tool.

[0016] Further, in step S3, view the PDN impedance curve graph, switch the result to a logarithmic coordinate system to clearly observe the impedance characteristics in the high-frequency band, add a target impedance line to the impedance curve graph, and judge whether the PDN impedance meets the design requirements.

[0017] Further, in step S4, the DDR5 particles are simulated using independent ports. Compare the impedance curve of a certain Sink end with the target impedance line. If it does not meet the design requirements, optimize it precisely alone, and the other Sink ends do not need to be adjusted anymore;

[0018] If the curve shows that the impedance in the high-frequency band is too high, increase the number of high-frequency decoupling capacitors for this Sink end and optimize their layout;

[0019] If the impedance in the low-frequency band is too high, adjust the parameters of the voltage module to optimize its output ability.

[0020] The DDR5 multi-particle independent-port PDN impedance simulation and optimization device includes: at least one memory and at least one processor;

[0021] The at least one memory is used to store machine-readable programs;

[0022] The at least one processor is used to call the machine-readable program to execute the DDR5 multi-particle independent-port PDN impedance simulation and optimization method.

[0023] Compared with the prior art, the DDR5 multi-particle independent-port PDN impedance simulation and optimization method and device of the present invention have the following prominent beneficial effects:

[0024] The present invention is particularly applicable to the scenario where DDR5 is used as a processor back-end application, aiming to improve power integrity and signal integrity through independent port emulation optimization, and ensure the high performance and stability of the system. Brief Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0026] Attached Figure 1 is a flowchart of a method for optimizing the PDN impedance of independent ports of multiple DDR5 chips;

[0027] Attached Figure 2 is a flowchart of PDN impedance simulation in a method for optimizing the PDN impedance of independent ports of multiple DDR5 chips;

[0028] Attached Figure 3 is a PCB model stack-up structure diagram in a method for optimizing the PDN impedance of independent ports of multiple DDR5 chips;

[0029] Attached Figure 4 is an optimized PDN impedance curve graph in a method for optimizing the PDN impedance of independent ports of multiple DDR5 chips. Detailed Embodiments

[0030] In order to enable those skilled in the art of the present technology to better understand the solutions of the present invention, the following will further elaborate on the present invention in conjunction with specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0031] The following gives a best embodiment:

[0032] As Figures 1-4 shown, in the method for optimizing the PDN impedance of independent ports of multiple DDR5 chips in this embodiment, for the selected power network of DDR5 that needs to be simulated, an independent port is established for this power network at each Sink end (DDR5 chip), and simulation is performed to generate an independent PDN impedance curve. Finally, it is respectively compared with the specified target impedance curve and individually optimized to ensure that the PDN impedance of each chip is within the target range, thereby improving the power integrity and signal integrity of the entire system.

[0033] Open the ADS software, create a project and save it. Then import the PCB file to be simulated. After importing the design, enter the stack-up design interface, adjust the parameters according to the actual PCB design, configure the material properties, and input the dielectric constant and loss at different frequencies. Then start SIPro / PIPro, and select the PI-AC analysis for the simulation type to extract the AC impedance characteristics of the PDN.

[0034] The specific steps are as follows:

[0035] S1. Establishment of the independent port simulation model;

[0036] In the PI-AC analysis interface, select the power network and reference ground network to be simulated, clarify the power supply end (VRM) of this network, and use the software to automatically set the ports for the VRM. Clearly set parameters such as the allowable fluctuation ranges of voltage and current, and set the reference impedance to 0.1 Ω; assign the S-parameter model to the passive interconnect devices on this power network channel;

[0037] Define independent power and ground ports for multiple power-consuming ends (Sinks), that is, for the power network of multiple DDR5 chips. Each Sink end will be automatically set as the PDN impedance observation port. When viewing the results, there will be as many impedance curves as there are Sink ends.

[0038] In this way, each DDR5 chip can be precisely optimized subsequently, improving the simulation accuracy and optimization efficiency.

[0039] S2. Simulation settings;

[0040] Set the simulation frequency range from 1 KHz at low frequency to 1 GHz at high frequency, and set the global simulation parameters in the simulation tool, such as multi-threaded simulation, network division accuracy, etc.

[0041] S3. Analysis of simulation results;

[0042] View the PDN impedance curve graph, switch the results to the logarithmic coordinate system to more clearly observe the impedance characteristics in the high-frequency band. Add the target impedance line (such as 0.066 Ω) to the impedance curve graph to judge whether the PDN impedance meets the design requirements.

[0043] S4. Optimization strategy;

[0044] Use independent port simulation for DDR5 chips. If the impedance curve of a certain Sink end (DDR5 chip) is compared with the target impedance line and does not meet the design requirements, it can be precisely optimized individually. Other Sink ends do not need to be adjusted anymore, improving the optimization efficiency.

[0045] If the curve shows that the impedance in the high - frequency band is too high, increase the number of high - frequency decoupling capacitors (such as 0.1 μF and 1 μF high - frequency ceramic capacitors) at the Sink end and optimize their layout (place the high - frequency decoupling capacitors close to the power pins to reduce parasitic inductance, ensure that each power pin is independently connected to the decoupling capacitor, and avoid star connection); if the impedance in the low - frequency band is too high, adjust the parameters of the voltage module (add low - frequency capacitors such as 10 μF and 47 μF) and optimize its output capacity.

[0046] It should be noted that ADS software is a leading electronic design automation software, suitable for radio frequency, microwave, and signal integrity applications. The target impedance of the PDN for DDR5 is usually around 0.066 Ω. In actual design, it is necessary to ensure that the PDN impedance is lower than the target value by optimizing decoupling capacitors, PCB design, and parasitic inductance in the high - frequency band. These measures help improve power integrity and system stability. The following are the key information and design points regarding the DDR5 PDN impedance:

[0047] Target impedance (ZT - PDN);

[0048] The target impedance is an important parameter in PDN design, used to ensure that the noise voltage on the power rail does not exceed the acceptable ripple voltage of the IC power supply. The calculation formula for the target impedance is:

[0049]

[0050] Where: VCC is the power supply voltage; Ripple% is the ripple percentage of the power supply voltage; Imax is the maximum transient current.

[0051] Typical value;

[0052] VCC = 1.1 V (typical operating voltage of DDR5); Ripple% = 3% (common ripple percentage); Imax = 1 A (assuming the maximum transient current is 1 A);

[0053] According to the above formula, the target impedance is: ZT - PDN=(1.1×0.03) / (0.5×1)=0.066 Ω. Therefore, the target impedance of the PDN for DDR5 is usually around 0.066 Ω.

[0054] In actual design, the PDN impedance needs to be lower than the target impedance throughout the target frequency range. The target frequency range usually ranges from DC to 1 GHz. To achieve this goal, the following measures need to be taken: Select appropriate decoupling capacitors (use decoupling capacitors with different capacitance values, such as 0.1 μF, 1 μF, etc., in parallel to cover a wide frequency range);

[0055] Optimize the PCB design (ensure that the impedance of the power supply and ground wires is as low as possible, usually less than 5 mΩ); use a multi-layer PCB (reduce the propagation of power supply noise by adding power supply layers and ground layers); in the high-frequency band, above 100 MHz for example, the PDN impedance is mainly determined by decoupling capacitors and PCB plane capacitors. The impedance optimization in the high-frequency band mainly uses high-frequency ceramic capacitors, such as 0.1 μF, to reduce the impedance in the high-frequency band, and by optimizing the layout and wiring of the capacitors, the parasitic inductance is reduced.

[0056] Taking the power supply voltage of 1.1V for DDR5 as an example to illustrate (the simulation process framework is as shown in the appendix Figure 1 and the simulation process steps are as shown in the appendix Figure 2 ):

[0057] 1. Import the PCB model: Import the PCB model of the DDR5 memory module, and set the stack-up information of the PCB, including the thickness and material parameters of each layer, as shown in the appendix Figure 3 .

[0058] 2. Define independent ports: In the simulation tool, define independent power supply and ground ports for each DDR5 chip, and set the reference impedance to 0.1 Ω.

[0059] 3. Set the simulation parameters: Set the simulation frequency range from low frequency 1 kHz to high frequency 1 GHz, and set the global simulation parameters.

[0060] 4. Run the simulation: Start the simulation, and the simulation tool will calculate the impedance of the PDN at different frequencies and generate an impedance curve graph.

[0061] 5. Analyze the results: View the impedance curve graph, as shown in the appendix Figure 4 . Compare with the target impedance line to judge whether the PDN impedance meets the design requirements. If the impedance in some frequency bands exceeds the target value, optimize the design according to the simulation results.

[0062] In the present invention, by defining independent power supply and ground ports for each DDR5 chip, the PDN impedance characteristics of each chip are accurately analyzed, and the mutual influence between chips is reduced. Through independent port simulation and optimized design, the PDN impedance is significantly reduced, and the influence of power supply noise and transient current is reduced.

[0063] Through independent port simulation and optimized design, the power integrity and signal integrity of the DDR5 system are significantly improved, providing strong support for the design and optimization of the DDR5 memory module.

[0064] The above specific embodiments are only specific cases of the present invention. The patent protection scope of the present invention includes but is not limited to the above specific embodiments. Any technical solutions that conform to the above specific embodiments of the present invention and any appropriate changes or substitutions made by any person of ordinary skill in the relevant technical field shall fall within the patent protection scope of the present invention.

[0065] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. The method for simulating and optimizing the PDN impedance of multiple independent ports of DDR5 memory chips is characterized in that, For the power network of DDR5 selected for simulation, independent ports are established for the power network at each Sink end, and simulations are performed to generate independent PDN impedance curves. Finally, they are compared with the specified target impedance curves separately and optimized individually to ensure that the PDN impedance of each die is within the target range, thereby improving power integrity and signal integrity.

2. The DDR5 multi-die independent port PDN impedance simulation optimization method according to claim 1, wherein First, open the ADS software, create and save a project. Then, import the PCB file to be simulated. After importing the design, enter the stack-up design interface, adjust the parameters according to the actual PCB design, configure the material properties, input the dielectric constant and loss at different frequencies. Finally, start SIPro / PIPro, and select PI-AC analysis for the simulation type to extract the AC impedance characteristics of the PDN.

3. The DDR5 multi-die independent port PDN impedance simulation optimization method according to claim 2, wherein The specific steps are as follows: S1. Establishment of the independent port simulation model; S2. Simulation settings; S3. Analysis of simulation results; S4. Optimization strategy.

4. The DDR5 multi-die independent port PDN impedance simulation optimization method according to claim 3, wherein In step S1, in the PI-AC analysis interface, select the power network and reference ground network to be simulated, clarify the power supply end VRM of this network, and use the software to automatically set ports for the VRM. Clearly set the allowable fluctuation ranges of voltage and current, assign S-parameter models to the passive interconnection devices on the power network channel, and define independent power and ground ports for multiple power-consuming Sink ends, that is, this power network of DDR5 dies. That is, each Sink end will be automatically set as a PDN impedance observation port. When viewing the results, several impedance curves will be generated for several Sink ends.

5. The DDR5 multi-die independent port PDN impedance simulation optimization method according to claim 4, wherein, In step S2, set the simulation frequency range from 1KHz at low frequency to 1GHz at high frequency, and set the global simulation parameters in the simulation tool.

6. The DDR5 multi-die independent port PDN impedance simulation optimization method according to claim 5, characterized in that In step S3, view the PDN impedance curve graph, switch the result to a logarithmic coordinate system to clearly observe the impedance characteristics in the high-frequency band, add the target impedance line to the impedance curve graph, and judge whether the PDN impedance meets the design requirements.

7. The DDR5 multi-die independent port PDN impedance simulation optimization method according to claim 6, wherein In step S4, for DDR5 dies, use independent port simulation. Compare the impedance curve of a certain Sink end with the target impedance line. If it does not meet the design requirements, optimize it precisely individually, and do not need to adjust other Sink ends; If the curve shows that the impedance in the high-frequency band is too high, increase the number of high-frequency decoupling capacitors for this Sink end and optimize their layout; If the impedance in the low-frequency band is too high, adjust the parameters of the voltage module and optimize its output capacity.

8. The PDN impedance simulation and optimization device for multiple independent ports of DDR5 memory chips is characterized in that, Including: At least one memory and at least one processor; The at least one memory is used to store machine-readable programs; The at least one processor is used to call the machine-readable program and execute the method according to any one of claims 1 to 7.

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