Semiconductor structure preparation method and semiconductor structure

Abstract

The invention discloses a semiconductor structure preparation method and a semiconductor structure, and the method comprises the steps: carrying out the first reaction between first neutral particles and a dielectric layer, and carrying out the first etching of a first depth on the surface of the dielectric layer exposed from the side surface of a mask pattern, so as to form a first etching structure; performing a second reaction on second neutral particles and the dielectric layer, performing second etching of a second depth on the bottom of the first etching structure to form a second etching structure, and generating and adsorbing a solid barrier layer at least on the bottom of the second etching structure through the second reaction; desorbing the barrier layer for removal; the process of performing the second etching and desorbing the barrier layer is one to multiple times until the surface of the substrate is exposed from the bottom of the second etching structure. According to the invention, the etching process window can be improved, charge accumulation and lattice damage are effectively avoided, the performance of the device is improved, and the application value is extremely high.

Description

Technical Field

[0001] This application relates to the field of semiconductor processing technologies, and particularly to a method for fabricating a semiconductor structure and a semiconductor structure. Background Art

[0002] When fabricating semiconductor devices of integrated circuits (ICs), it is usually necessary to form a dielectric film layer on a substrate. The dielectric film layer plays multiple roles in integrated circuits, such as insulation, isolation, protection, and process assistance. Commonly used dielectric film layers include silicon oxide, which is a cornerstone material in traditional silicon-based semiconductor processes. Among them, the performance of the silicon oxide etching process has a very important impact on the manufacturing of integrated circuits and the device performance. The traditional silicon oxide etching process mainly uses the method of reactive ion etching (RIE), and in a capacitively coupled plasma (CCP) or inductively coupled plasma (ICP) reaction chamber, the rapid removal of the silicon oxide film layer is achieved by the synergistic effect of the bombardment of high-energy particles and chemical reactions. However, in the CCP or ICP reaction chamber, the bombardment of high-energy ions will simultaneously cause problems such as poor selectivity between silicon oxide and the underlying substrate material (such as silicon) or the upper mask material (such as photoresist), lattice damage to silicon oxide or the underlying silicon, and charge accumulation causing dielectric layer traps or interface states. These will greatly affect the process window of silicon oxide etching and the performance of IC devices. Therefore, it is necessary to study a process method that can significantly improve the above problems. Summary of the Invention

[0003] The purpose of this application is to overcome the above problems existing in the prior art, and provide a method for fabricating a semiconductor structure and a semiconductor structure, so as to significantly improve the selectivity to the upper and lower layer materials of the dielectric layer while achieving the rapid removal of the dielectric layer, and effectively avoid problems such as charge accumulation and lattice damage.

[0004] To achieve the above purpose, the technical solution of this application is as follows: According to the first aspect of this application, an embodiment of this application provides a method for fabricating a semiconductor structure, including: Providing a substrate, on one side of which there are successively a dielectric layer and a mask pattern; Using first neutral particles to perform a first reaction with the dielectric layer to perform a first etching of the surface of the dielectric layer exposed from the side of the mask pattern to a first depth to form a first etching structure; the first neutral particles are obtained by exciting a first reaction gas to form a first plasma and filtering out the charged particles in the first plasma; Switch to using second neutral particles to perform a second reaction with the dielectric layer to perform a second etch of a second depth on the bottom of the first etch structure to form a second etch structure, and generate and adsorb a solid barrier layer at least on the bottom of the second etch structure through the second reaction; the second neutral particles are obtained by exciting a second reaction gas to form a second plasma and filtering out charged particles in the second plasma; Desorb the barrier layer to remove it; Wherein, the process of performing the second etch and desorbing the barrier layer is one to multiple times until the surface of the substrate is exposed from the bottom of the second etch structure.

[0005] In some embodiments, the first depth is less than the thickness of the dielectric layer, and the second depth is less than the first depth.

[0006] In some embodiments, the substrate material includes silicon.

[0007] In some embodiments, the dielectric layer material includes silicon oxide.

[0008] In some embodiments, after the surface of the substrate is exposed from the bottom of the second etch structure, it further includes: switching to using third neutral particles to perform a third reaction with the mask pattern to remove the mask pattern; the third neutral particles are obtained by exciting a third reaction gas to form a third plasma and filtering out charged particles in the third plasma.

[0009] In some embodiments, the first reaction gas includes a first fluorine-based gas, and the second reaction gas includes a second fluorine-based gas and a hydrogen-based gas.

[0010] In some embodiments, the first fluorine-based gas includes NF3, SF6, CHF3, CH2F2, CF4, C4F8 or C2F6.

[0011] In some embodiments, the second fluorine-based gas includes NF3, SF6, CHF3, CH2F2, CF4, C4F8 or C2F6, and the hydrogen-based gas includes NH3.

[0012] In some embodiments, the first fluorine-based gas is NF3, and the first neutral particles include F radicals and NF2 radicals.

[0013] In some embodiments, the second fluorine-based gas is NF3, the second neutral particles include at least one of NH4F neutral molecules and NH4F.HF neutral molecules, and the barrier layer includes (NH4)2SiF6.

[0014] In some embodiments, the first etching is performed using a first temperature, the second etching is performed using a second temperature, and the barrier layer is decomposed using a third temperature, with the second temperature, the first temperature, and the third temperature increasing in sequence.

[0015] In some embodiments, the first temperature is 70°C to 110°C.

[0016] In some embodiments, the second temperature is 10°C to 40°C.

[0017] In some embodiments, the third temperature is 150°C to 275°C.

[0018] When performing the first etching or the second etching, the pressure is 100 mTorr to 10 Torr, the frequencies of the radio frequency sources include 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, 100 MHz, or 2.45 GHz, and the source power is 20 W to 3000 W.

[0019] In some embodiments, the first temperature, the second temperature, and the third temperature are achieved by the following method: The substrate is placed on the top surface of a heating base, and a gas cooling channel is provided on the top of the heating base. The gas cooling channel is used to introduce a cooling gas to adjust the heat transfer capacity of the heating base so that the substrate reaches different required temperatures; Among them, by heating the heating base to a target temperature and respectively introducing a first flow rate, a second flow rate, or a third flow rate of the cooling gas into the gas cooling channel, the substrate is forced to be convectively cooled to the required first temperature, second temperature, or third temperature; the third flow rate, the first flow rate, and the second flow rate increase in sequence, and the target temperature is higher than the third temperature.

[0020] In some embodiments, the distance between the bottom of the first etching structure and the substrate surface is 3 Å to 50 nm; In some embodiments, the mask pattern material includes photoresist.

[0021] In some embodiments, the third reaction gas includes an oxygen-based gas, and the third neutral particle includes an O radical.

[0022] According to the second aspect of the present application, an embodiment of the present application further provides a semiconductor structure, which is obtained by using the semiconductor structure preparation method provided in any one of the embodiments of the first aspect above.

[0023] Embodiments of the present application may / at least have the following advantages: (1) By using relatively mild neutral particles to react with the dielectric layer material, the removal of the dielectric layer film is achieved. It has a very high selectivity ratio for both the mask pattern material and the substrate material, and can effectively avoid problems such as charge accumulation and lattice damage caused by high-energy ion bombardment in traditional reactive ion etching.

[0024] (2) By adopting a two-step etching method (the first etching and the second etching), the step-by-step removal of the dielectric layer is performed. When performing the first etching, the high-concentration first neutral particles generated by the first plasma formed by the first reaction gas at a relatively high temperature (the first temperature) react quickly with the dielectric layer to achieve the rapid removal of most of the dielectric layer material without damaging the mask pattern; when approaching the bottom substrate quickly, the second etching is switched to. The second neutral particles generated by the second plasma formed by the second reaction gas at a relatively low temperature (the second temperature) react with the dielectric layer to generate a solid barrier layer, and the barrier layer is decomposed at a certain temperature (the third temperature) to achieve the gentle removal of the remaining dielectric layer material, thus avoiding damage to the substrate.

[0025] Therefore, the embodiments of the present application can greatly improve the etching process window and enhance the performance of IC devices when preparing a semiconductor structure with an etching structure (the second etching structure).

[0026] Other advantages of the present application will be elaborated in the following specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a flowchart of a method for preparing a semiconductor structure according to a preferred embodiment of the present application.

[0028] Figure 2 It is a schematic structural diagram after forming a dielectric layer and a mask pattern on a substrate according to a preferred embodiment of the present application.

[0029] Figure 3 It is a schematic principle diagram of using the first neutral particles to perform the first reaction with the dielectric layer according to a preferred embodiment of the present application.

[0030] Figure 4 It is a schematic structural diagram after forming the first etching structure in the dielectric layer according to a preferred embodiment of the present application.

[0031] Figure 5 It is a schematic principle diagram of using the second neutral particles to perform the second reaction with the dielectric layer according to a preferred embodiment of the present application.

[0032] Figure 6 It is a schematic principle diagram of decomposing the barrier layer according to a preferred embodiment of the present application.

[0033] Figure 7 Schematic diagram of the structure after forming a second etching structure in a dielectric layer provided by a preferred embodiment of the present application.

[0034] Figure 8 Schematic diagram of the structure after removing a mask pattern provided by a preferred embodiment of the present application.

[0035] In the figure, 10 is a substrate; 11 is a dielectric layer; 12 is an opening; 13 is a mask pattern; 141 is a first trench; 15 is a barrier layer; 161 is a second trench. Detailed implementation manners

[0036] In view of the problems existing in the existing silicon oxide dielectric layer etching process, such as poor selectivity between silicon oxide and the underlying substrate material (such as silicon) or the upper mask material (such as photoresist) due to high-energy ion bombardment, lattice damage of silicon oxide or the underlying silicon, and charge accumulation causing dielectric layer traps or interface states, etc., the embodiments of the present application provide a semiconductor structure preparation method, including: Providing a substrate, on one side of which there are successively a dielectric layer and a mask pattern; Using first neutral particles to react with the dielectric layer for a first reaction to perform a first etching with a first depth on the surface of the dielectric layer exposed from the side of the mask pattern to form a first etching structure; the first neutral particles are obtained by exciting a first reaction gas to form a first plasma and filtering out the charged particles in the first plasma; Switching to using second neutral particles to react with the dielectric layer for a second reaction to perform a second etching with a second depth on the bottom of the first etching structure to form a second etching structure, and generating and adsorbing a solid barrier layer at least on the bottom of the second etching structure through the second reaction; the second neutral particles are obtained by exciting a second reaction gas to form a second plasma and filtering out the charged particles in the second plasma; Desorbing the barrier layer to remove it; Wherein, the process of performing the second etching and desorbing the barrier layer is one to multiple times until the surface of the substrate is exposed from the bottom of the second etching structure.

[0037] The embodiments of the present application realize the removal of the dielectric layer film by using relatively mild neutral particles to react with the dielectric layer material, which not only has a very high selectivity ratio for both the mask pattern material and the substrate material, but also can effectively avoid problems such as charge accumulation and lattice damage caused by high-energy ion bombardment in traditional reactive ion etching. Therefore, when preparing a semiconductor structure with an etching structure (second etching structure), the process window of etching can be greatly improved, and the performance of IC devices can be enhanced.

[0038] Embodiments of the present application also provide a semiconductor structure obtained by using the semiconductor structure preparation method provided by the embodiments of the present application.

[0039] The following will describe in detail the specific embodiments of the present application with reference to the accompanying drawings.

[0040] Reference Figure 1 Embodiments of the present application provide a method for preparing a semiconductor structure, including the following steps: Step S11: Provide a substrate.

[0041] Reference Figure 2 In some embodiments, the material of the substrate 10 includes silicon. For example, a silicon wafer can be used as the substrate 10 (i.e., a silicon substrate) to further form a required semiconductor structure on the substrate 10. However, it can be understood that the method for preparing a semiconductor structure provided by the embodiments of the present application can also be applied to other substrates 10 other than silicon materials. The following takes the substrate 10 made of silicon material as an example to illustrate the method for preparing a semiconductor structure provided by the embodiments of the present application.

[0042] Step S12: Sequentially form a dielectric layer and a mask pattern on the surface of the substrate.

[0043] Reference Figure 2 In some embodiments, a dielectric layer 11 is deposited on one side (the upper surface) of the substrate 10 by using a dielectric deposition process.

[0044] In some embodiments, the material of the dielectric layer 11 includes silicon oxide (SiO2). For example, a silicon oxide layer with a conventional thickness is deposited on the upper surface of the substrate 10 by using the CVD process as the dielectric layer 11. However, it can be understood that the material of the dielectric layer 11 is not limited to silicon oxide. The following takes the dielectric layer 11 made of silicon oxide material as an example to continue to illustrate the method for preparing a semiconductor structure provided by the embodiments of the present application.

[0045] In some embodiments, a mask layer is first formed on the upper surface of the dielectric layer 11; then, by patterning the mask layer, a mask pattern 13 is formed on the upper surface of the dielectric layer 11.

[0046] In some embodiments, the material of the mask layer includes photoresist. That is, the material of the mask pattern 13 includes photoresist. However, it can be understood that the material of the mask layer is not limited to photoresist. The following takes the mask layer made of photoresist material as an example to continue to illustrate the method for preparing a semiconductor structure provided by the embodiments of the present application.

[0047] In some embodiments, a spin coating process is adopted. First, a photoresist layer serving as a mask layer is spin-coated and dried on the upper surface of the dielectric layer 11. Then, a photolithography process is used to pattern the photoresist layer serving as the mask layer, and a plurality of juxtaposed photoresist patterns are formed on the upper surface of the dielectric layer 11. Each photoresist pattern serves as a mask pattern 13.

[0048] It should be noted that Figure 2 only a case where 3 photoresist patterns (mask patterns 13) are formed on the upper surface of the dielectric layer 11 is schematically shown. However, it can be understood that 1 or more photoresist patterns can be formed on the upper surface of the dielectric layer 11, such as 1 photoresist pattern, 2 photoresist patterns, 3 photoresist patterns, 10 photoresist patterns, etc., and it is not limited thereto.

[0049] After a plurality of mask patterns 13 are formed on the upper surface of the dielectric layer 11, an opening 12 will be formed between any two adjacent mask patterns 13, and the upper surface of the dielectric layer 11 located at the bottom surface of the opening 12 will be exposed. The above-mentioned opening 12 serves as a window for subsequent etching of the dielectric layer 11.

[0050] Step S13: Use first neutral particles to etch the surface of the dielectric layer exposed from the side of the self-mask pattern, and form a first etching structure in the dielectric layer.

[0051] Refer to Figure 3 and Figure 4 . In some embodiments, a plasma dry etching process is adopted, and with the mask pattern 13 as a mask, the surface of the dielectric layer 11 exposed from the side of the self-mask pattern 13 below (i.e., the opening 12) is etched and patterned to remove a certain thickness of silicon oxide material from the dielectric layer 11, so as to form a first etching structure in the dielectric layer 11.

[0052] In some embodiments, the first etching structure includes trenches, through holes, etc. Hereinafter, taking the first etching structure as a trench (first trench 141) as an example, the embodiments of the present application will be further described in detail.

[0053] In some embodiments, a first reaction gas is used to perform a first etching of the dielectric layer 11 to a first depth A, and a first trench 141 (first etching structure) having a first depth A is formed in the dielectric layer 11.

[0054] In some embodiments, when using a plasma dry etching process to etch the dielectric layer 11, first neutral particles are used to react with the dielectric layer 11 for a first reaction, and the surface of the dielectric layer 11 exposed from the bottom surface of the opening 12 is etched to a first depth A for a first etching, so as to form a first trench 141.

[0055] Among them, the first reaction gas is ionized to excite the first reaction gas to form a first plasma; and, by filtering the first plasma, charged particles contained in the first plasma are removed to obtain first neutral particles.

[0056] The plasma formed by ionizing the reaction gas usually contains positive ions, negative ions, electrons, free radicals, and neutral molecules. Among them, the charged particles (positive ions, negative ions, electrons) are high-energy particles, which will strongly bombard the dielectric layer 11 (silicon oxide), easily causing problems such as poor selectivity to the substrate 10 material (such as silicon) under the dielectric layer 11 or the mask pattern 13 material (such as photoresist) on the upper layer, damage to the silicon oxide or the silicon lattice of the bottom layer, and charge accumulation causing dielectric layer traps or interface states. These will greatly affect the process window of silicon oxide etching and the performance of IC devices. Therefore, in the embodiments of the present application, by filtering the first plasma formed by exciting the first reaction gas, removing the charged particles therein, and only retaining the relatively mild free radicals and neutral molecules (first neutral particles), the energy during the bombardment of the first plasma is reduced. Thus, when etching the dielectric layer 11, not only can it have an extremely high selectivity ratio to the mask pattern 13 material, but also it can effectively avoid problems such as dielectric layer lattice damage caused by high-energy ion bombardment and dielectric layer traps or interface states caused by charge accumulation. At the same time, rapid removal of the dielectric layer 11 material can be achieved.

[0057] In some embodiments, the first reaction gas includes a first fluorine-based gas.

[0058] In some embodiments, the first fluorine-based gas includes NF3, SF6, CHF3, CH2F2, CF4, C4F8, or C2F6.

[0059] In some embodiments, the first fluorine-based gas is NF3, SF6, CHF3, CH2F2, CF4, C4F8, or C2F6.

[0060] In this embodiment, the first fluorine-based gas is NF3. By ionizing NF3, NF3 is excited to form a plasma (first plasma). By filtering the first plasma formed by NF3, charged particles contained therein are removed to obtain F free radicals and NF2 free radicals, that is, neutral particles (first neutral particles), as Figure 3 shown ( Figure 3 only the F free radicals as the main etching particles are shown). Using the F free radicals and NF2 free radicals to react with the dielectric layer 11 of the silicon oxide material (first reaction), the surface of the dielectric layer 11 exposed from the side of the self-mask pattern 13 is etched to a certain depth (first depth A) (first etching), and its expression is: NF3 → NF2· + F· NF2· + F· + SiO2 → NO + NO2 + SiF4 Thereby, a first trench 141 with a first depth A is etched and formed on the surface of the dielectric layer 11 exposed at the bottom of the opening 12, as Figure 4 shown.

[0061] In some embodiments, the first depth A is less than the thickness C of the dielectric layer 11.

[0062] In some embodiments, the first depth A is less than the thickness C of the dielectric layer 11 and greater than half of the thickness C of the dielectric layer 11. That is, by using the F radicals to react rapidly with the silicon oxide material of the dielectric layer 11 and removing most of the thickness of the dielectric layer 11, the end point of the first etching stops when the bottom of the first trench 141 is about to contact the surface of the underlying substrate 10, thereby realizing the rapid etching of most of the thickness of the dielectric layer 11. This first etching process has an extremely high selectivity to the photoresist material of the mask pattern 13.

[0063] In some embodiments, the first distance B between the bottom of the first trench 141 (the first etching structure) and the surface of the substrate 10 is 3 Å to 50 nm. For example, the first distance B can be 3 Å, 5 Å, 10 Å, 20 Å, 50 Å, 100 Å, 500 Å, 1 nm, 10 nm, 30 nm or 50 nm, or any value between any two of the foregoing distance values. Thus, during the first etching, the dielectric layer 11 can be prevented from being etched through, so as to avoid the direct bombardment of the high-concentration F radicals on the substrate 10, thereby effectively protecting the substrate 10 and avoiding lattice damage to the silicon of the substrate 10.

[0064] In some embodiments, inductively coupled plasma (ICP) can be used to excite the first reaction gas to form a first plasma. Alternatively, capacitively coupled plasma (CCP) can also be used to excite the first reaction gas to form a first plasma. Hereinafter, taking the etching using inductively coupled plasma (ICP) as an example, the embodiments of the present application will be further described.

[0065] In some embodiments, an inert gas can be used as a dilution and dissociation gas to dilute and dissociate the first reaction gas. For example, the dilution and dissociation gas that can be used includes at least one of Ar and He.

[0066] In some embodiments, the bias voltage is turned off when performing the first etching.

[0067] In some embodiments, when performing the first etching, the silicon oxide material of the dielectric layer 11 is etched in a direction biased towards isotropic by the obtained F radicals.

[0068] In some embodiments, when performing the first etching, a first temperature that is relatively high (compared with the second temperature) is used to etch the dielectric layer 11.

[0069] In some embodiments, the first temperature is 70°C to 110°C. For example, the first temperature can be 70°C, 75°C, 80°C, 85°C, 90°C, 95°C, 100°C, 105°C, or 110°C, or any value between any two of the foregoing temperature values. At this temperature, for example, a high concentration of F radicals is generated after NF3 is excited. After filtration, the high-concentration F radicals can react quickly with the silicon oxide material of the dielectric layer 11 to achieve rapid etching of the dielectric layer 11. This process has an extremely high selectivity (≥100) for the mask pattern 13 of the photoresist material.

[0070] In some embodiments, when performing the first etching, the pressure is 100 mTorr to 10 Torr. For example, the pressure can be 100 mTorr, 200 mTorr, 500 mTorr, 800 mTorr, 1 Torr, 3 Torr, 5 Torr, 7 Torr, 9 Torr, or 10 Torr, or any value between any two of the foregoing pressure values.

[0071] In some embodiments, when performing the first etching, the frequencies of the radio frequency sources used to excite and form the first plasma include 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, 100 MHz, or 2.45 GHz, but are not limited thereto.

[0072] In some embodiments, when performing the first etching, the source power is 20 W to 3000 W. For example, the source power can be 20 W, 50 W, 80 W, 100 W, 400 W, 900 W, 1000 W, 1300 W, 1500 W, 2000 W, 2500 W, or 3000 W, or any value between any two of the foregoing power values.

[0073] Step S14: Use a second neutral particle to etch the bottom of the first etching structure, further form a second etching structure in the dielectric layer, and generate and adsorb a solid barrier layer at least on the bottom of the second etching structure.

[0074] Reference Figure 5. In some embodiments, a plasma dry etching process is employed, and continuing to use the mask pattern 13 as a mask, the dielectric layer 11 exposed on the inner wall of the first trench 141 below is etched and patterned to further form a second etching structure located in the dielectric layer 11 on the basis of the first trench 141. The purpose is to etch the bottom of the first trench 141 to remove the dielectric layer 11 with a remaining thickness (i.e., the first distance B) at least on the bottom of the first trench 141, so that the surface of the substrate 10 is exposed on the bottom of the finally formed second etching structure.

[0075] In some embodiments, the second etching structure includes trenches, through holes, etc. Here, taking the second etching structure as a trench (the second trench 161) as an example, the embodiments of the present application will be further described in detail.

[0076] In some embodiments, a second reaction gas is used to perform a second etching with a second depth D on the bottom of the first trench 141, that is, to continue to perform a second etching with a second depth D on the dielectric layer 11 located on the bottom of the first trench 141 to further form a second trench 161 (the second etching structure) located in the dielectric layer 11 on the basis of the first trench 141. The bottom of the second trench 161 is advanced downward by a second depth D relative to the bottom of the first trench 141. That is, the total depth of the second trench 161 at this time is the sum of the first depth A and the second depth D, as Figure 5 shown. The second depth D is less than the first depth A.

[0077] In some embodiments, when using a plasma dry etching process to perform a second etching on the dielectric layer 11 exposed on the inner wall of the first trench 141, a second reaction is performed between the second neutral particles and the dielectric layer 11 to perform a second etching with a second depth D on the bottom of the first trench 141 to further form a second trench 161 on the basis of the first trench 141.

[0078] Among them, when performing a second etching on the dielectric layer 11 exposed on the inner wall of the first trench 141, it is necessary to first stop the supply of the first reaction gas and switch to the supply of the second reaction gas. And, by ionizing the second reaction gas, the second reaction gas is excited to form a second plasma; after filtering the second plasma to remove the charged particles contained in the second plasma, second neutral particles are obtained.

[0079] It should be noted that when using the second neutral particles to perform a second reaction with the dielectric layer 11, a solid barrier layer 15 is generated and adsorbed at least on the bottom of the second trench 161 through the second reaction, as Figure 5As shown, by using the solid-state barrier layer 15 adsorbed on the bottom of the second trench 161, protection of the surface of the substrate 10 can be formed and the continuation of the second reaction can be blocked. In this way, slow removal of the silicon oxide material at the bottom of the second trench 161 can be achieved, which not only has a high selectivity for the silicon material of the substrate 10, but also can effectively avoid problems such as charge accumulation and lattice damage.

[0080] In some embodiments, the second reaction gas includes a second fluorine-based gas and a hydrogen-based gas.

[0081] In some embodiments, the second fluorine-based gas includes NF3, SF6, CHF3, CH2F2, CF4, C4F8, or C2F6.

[0082] In some embodiments, the second fluorine-based gas is NF3, SF6, CHF3, CH2F2, CF4, C4F8, or C2F6.

[0083] In some embodiments, the hydrogen-based gas includes NH3.

[0084] In this embodiment, the second reaction gas is NF3 and NH3. By mixing and ionizing NF3 and NH3, the NF3 and NH3 are excited to form a plasma (the second plasma). After filtering the formed second plasma and removing the charged particles contained therein, neutral molecules of NH4F and NH4F·HF, that is, neutral particles (the second neutral particles), are obtained. Using at least one of NH4F and NH4F·HF to react with the dielectric layer 11 of the silicon oxide material (the second reaction), the bottom of the first trench 141 can be etched to a second depth D for the second etching, and a second trench 161 can be further formed on the basis of the first trench 141. It can be seen that the depth of the second trench 161 is A + D. At the same time, a solid-state barrier layer 15 will be generated and adsorbed on the bottom (including the sidewalls of the second trench 161) of the second trench 161. Its expression is: NF3 + NH3 → NH4F + NH4F·HF NH4F / NH4F·HF + SiO2 → (NH4)2SiF6 + H2O Thereby, a second trench 161 with a depth of A + D is etched and formed in the dielectric layer 11, and (NH4)2SiF6, which is a solid-state reaction product, is adsorbed on the inner wall of the second trench 161 as the barrier layer 15, as Figure 5 shown.

[0085] It should be noted that since it is usually difficult for NH3 and NF3 in the second reaction gas to react completely, after the formed second plasma is filtered, F radicals may also be filtered through ( Figure 5Only NH4F and NH4F.HF, which are the main etching particles, are shown, and they participate in the etching of the remaining dielectric layer 11. This is equivalent to diluting the F radicals by adding NH3, thereby greatly reducing the bombardment energy during etching.

[0086] It should also be noted that once the reaction product (NH4)2SiF6 is generated and adsorbed on the inner wall of the second trench 161, it plays a role in preventing the second reaction from continuing. Therefore, when the first distance B is relatively large, through one second etching process, it may not be possible to completely remove the remaining thickness of the dielectric layer 11 at the bottom of the first trench 141 at once, resulting in a certain second distance E (B - D = E) between the bottom of the formed second trench 161 and the surface of the substrate 10, as Figure 5 shown. In this case, it is necessary to first remove the barrier layer 15 and repeat the second etching one or more times (one or more cycles), and before each next second etching, first remove the barrier layer 15 formed in the previous time to perform the next second etching. Thus, the remaining dielectric layer 11 can be completely etched and slowly removed. Of course, if the first distance B is relatively small (for example, a thickness of several angstroms), it may be possible to completely remove the remaining thickness of the dielectric layer 11 at the bottom of the first trench 141 at once through one second etching process. This process has a high selectivity for the photoresist of the mask pattern and the silicon of the substrate 10, and the F radicals in the filtered second plasma also cause almost no damage to the silicon of the substrate 10.

[0087] In some embodiments, an inert gas can be used as the dilution and dissociation gas to dilute and dissociate the second reaction gas. For example, the dilution and dissociation gas that can be used includes at least one of Ar and He.

[0088] In some embodiments, when performing the second etching, the bias voltage is turned off.

[0089] In some embodiments, the remaining silicon oxide material of the dielectric layer 11 is etched in a direction biased towards isotropic etching by the obtained NH4F and NH4F.HF.

[0090] In some embodiments, when performing the second etching, a second temperature that is relatively low (compared with the first temperature) is used to continue the etching of the remaining thickness of the dielectric layer 11.

[0091] In some embodiments, the second temperature is from 10°C to 40°C. For example, the second temperature can be 10°C, 15°C, 20°C, 25°C, 30°C, 35°C, or 40°C, or any value between any two of the foregoing temperature values. At this temperature, the (NH4)2SiF6 generated by the reaction is in a solid state and adsorbs on the inner wall of the second trench 161 to form the barrier layer 15, thereby preventing the second reaction from continuing and, when the dielectric layer 11 below the bottom of the second trench 161 is completely removed by the reaction, adsorbing on the surface of the substrate 10 exposed from the bottom of the second trench 161, thus effectively protecting the surface of the substrate 10.

[0092] In some embodiments, the second temperature is room temperature (normal temperature).

[0093] In some embodiments, when performing the second etching, the pressure is from 100 mTorr to 10 Torr. For example, the pressure can be 100 mTorr, 150 mTorr, 200 mTorr, 400 mTorr, 500 mTorr, 700 mTorr, 1 Torr, 5 Torr, 8 Torr, or 10 Torr, or any value between any two of the foregoing pressure values.

[0094] In some embodiments, when performing the second etching, the frequencies of the radio frequency sources for exciting the formation of the first plasma include 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, 100 MHz, or 2.45 GHz, but are not limited thereto.

[0095] In some embodiments, when performing the second etching, the source power is from 20 W to 3000 W. For example, the source power can be 20 W, 40 W, 80 W, 100 W, 400 W, 700 W, 900 W, 1100 W, 1500 W, 2000 W, 2200 W, 2600 W, or 3000 W, or any value between any two of the foregoing power values.

[0096] Step S15: Desorb and remove the barrier layer.

[0097] Reference Figure 6 . In some embodiments, by using a third temperature that is relatively the highest (relative to the first temperature and the second temperature), the (NH4)2SiF6 adsorbed on the inner wall of the second trench 161 as the barrier layer 15 sublimes and decomposes during the process of the temperature rising from the second temperature to the third temperature, forming gaseous SiF4, NH3, and HF that volatilize, thereby removing the barrier layer 15 by desorption and exposing the inner wall surface of the second trench 161 including the bottom. The expression is: (NH4)2SiF6 → SiF4 + NH3 + HF In some embodiments, the third temperature is 150°C to 275°C. For example, the third temperature can be 150°C, 155°C, 170°C, 185°C, 200°C, 220°C, 240°C, 260°C, or 275°C, or any value between any two of the foregoing temperature values. It can be seen that the second temperature, the first temperature, and the third temperature increase in sequence.

[0098] Step S16: When the surface of the substrate is exposed from the bottom of the second etching structure, execute Step S17; otherwise, return to execute Step S14.

[0099] After performing the second etching once, it can be determined by detection whether the surface of the substrate 10 is exposed from the bottom of the second trench 161. If the surface of the substrate 10 is exposed from the bottom of the second trench 161, the subsequent Step S17 can be executed. Otherwise, if the surface of the substrate 10 has not been exposed from the bottom of the second trench 161, it is necessary to return to execute Step S14, that is, repeatedly execute Step S14 and Step S15 until the surface of the substrate 10 is exposed from the bottom of the second trench 161. Among them, the process of performing the second etching and desorbing the barrier layer 15 may require one to multiple cycles to expose the surface of the substrate 10 from the bottom of the second trench 161, so as to achieve complete etching of the dielectric layer 11, as Figure 7 shown.

[0100] When the surface of the substrate 10 is exposed from the bottom of the second trench 161, the depth of the second trench 161 is A + nD, where n is the number of cycles of the process of performing the second etching and desorbing the barrier layer 15, and n ≥ 1. It should be noted that in this example, expressing the depth of the second trench 161 at this time as (A + nD) is only for the convenience of explanation. In fact, when repeatedly performing the second etching, the etching depth each time will be different, that is, the values of D in each cycle will not be absolutely equal.

[0101] Step S17: React the third neutral particles with the mask pattern to remove the mask pattern.

[0102] Reference Figure 8 . In some embodiments, after the surface of the substrate 10 is exposed from the bottom of the second trench 161, the third reaction gas can be switched to, and the third reaction gas is ionized to excite the third reaction gas to form a third plasma. Then, by filtering the third plasma, the charged particles contained in the third plasma are filtered out to obtain the third neutral particles. Next, the third neutral particles are used to perform a third reaction with the photoresist material of the mask pattern 13 to remove the mask pattern 13.

[0103] In some embodiments, the third reactive gas includes an oxygen-based gas. For example, a mixed gas of O2 and N2 can be used as the third reactive gas. After excitation, the formed third plasma is filtered to obtain O radicals, that is, the third neutral particles, which react with the photoresist material of the mask pattern 13 to remove the mask pattern 13.

[0104] In some embodiments, the third reaction is carried out at a fourth temperature to remove the mask pattern 13.

[0105] In some embodiments, the fourth temperature is 100°C to 300°C. For example, the fourth temperature can be 100°C, 120°C, 150°C, 180°C, 200°C, 230°C, 250°C, 280°C, or 300°C, or any value between any two of the foregoing temperature values.

[0106] In some embodiments, when the third reaction is carried out, the pressure is 100 mTorr to 1000 mTorr. For example, the pressure can be 100 mTorr, 200 mTorr, 300 mTorr, 400 mTorr, 500 mTorr, 600 mTorr, 700 mTorr, 800 mTorr, 900 mTorr, or 1000 mTorr, or any value between any two of the foregoing pressure values.

[0107] In some embodiments, when the third reaction is carried out, the source power is 100 W to 3000 W. For example, the source power can be 100 W, 200 W, 500 W, 1000 W, 1500 W, 2000 W, 2500 W, or 3000 W, or any value between any two of the foregoing power values.

[0108] In some embodiments, when the third reaction is carried out, the bias power is zero.

[0109] After removing the mask pattern 13, a semiconductor structure with a patterned dielectric layer having a second trench 161 on the substrate 10 is obtained, as Figure 8 shown.

[0110] In some embodiments, the method for preparing a semiconductor structure provided in the embodiments of the present application can be implemented using a plasma processing device internally provided with a device for filtering charged particles. The plasma processing device is used to execute the method for preparing a semiconductor structure corresponding to the above embodiments to prepare and form a semiconductor structure corresponding to the above embodiments. The plasma processing device can be, for example, an inductively coupled plasma (ICP) etching device or a capacitively coupled plasma (CCP) etching device, etc.

[0111] In some embodiments, a plasma processing apparatus is provided with a chamber, and a device for filtering charged particles is disposed in the chamber. The device includes a double-layer filter screen, and the filter holes on the two filter screens are staggered. There is a gap between the two filter screens. A reaction gas (first reaction gas / second reaction gas) is excited to form a plasma by inductively coupled plasma (ICP) or capacitively coupled plasma (CCP). The ions and electrons are filtered out by the double-layer filter screen, and finally only free radicals / neutral molecules can pass through and react with the dielectric layer 11 on the substrate 10 to achieve etching and removal of the dielectric layer 11. Due to the filtering effect of the filter screen, the semiconductor structure preparation method provided by the embodiments of the present application uses free radicals or neutral molecules to react with silicon oxide throughout the process to remove the dielectric layer 11 film layer, and has a very high selectivity ratio for the photoresist of the mask pattern 13 and the silicon of the substrate 10, and can effectively avoid problems such as charge accumulation and lattice damage caused by traditional reactive ion etching (RIE).

[0112] In some embodiments, a plasma processing apparatus with a device for filtering charged particles inside can be realized by using a repair device for the surface of a silicon carbide trench disclosed in Chinese Patent Application No. CN117524866A. Alternatively, the device for filtering charged particles can be realized by using a filtering component provided in a repair device for the surface of a silicon carbide trench disclosed in Chinese Patent Application No. CN117524866A.

[0113] In some embodiments, the above-mentioned first temperature, second temperature, third temperature, and fourth temperature can be achieved by the following method: A heating base for setting the substrate 10 is provided in the chamber of the plasma processing apparatus, and a heater is provided inside the heating base. By controlling the start of the heater, the heating base can be heated to the required target temperature. In this way, by using the heat conduction effect of the heating base, the substrate 10 disposed on the top surface of the heating base can be heated. Further, a cooling gas channel is provided inside the heating base, and the cooling gas channel is located between the heater and the top surface of the heating base, that is, the cooling gas channel is located at the top of the heating base above the heater, and when the substrate 10 is disposed on the top surface of the heating base, the cooling gas channel is located below the substrate 10. When a cooling gas (such as argon, etc.) is introduced into the cooling gas channel, it can play a role in cooling the back surface of the substrate 10 by forced convection to inhibit the heat transfer of the heating base.

[0114] Furthermore, by setting the substrate 10 on the top surface of the heating base and adjusting the flow rate of the cooling gas introduced into the cooling gas channel, the heat transfer ability of the heating base can be adjusted so that the substrate 10 reaches different required temperatures.

[0115] Among them, by controlling the start of the heater, the heating base is heated to a target temperature, and a cooling gas with a first flow rate is introduced into the gas cooling channel, so that the substrate 10 is forced convection cooled correspondingly to a required first temperature, and the first etching is performed at the first temperature.

[0116] By controlling the heating temperature of the heater to be maintained at the target temperature, and introducing a cooling gas with a second flow rate greater than the first flow rate into the gas cooling channel, the substrate 10 is forced convection cooled further correspondingly to a second temperature lower than the first temperature, and the second etching is performed at the second temperature.

[0117] By controlling the heating temperature of the heater to be maintained at the target temperature, and introducing a cooling gas with a third flow rate less than the first flow rate into the gas cooling channel, the temperature of the substrate 10 rises to a third temperature higher than the first temperature under the action of weakened forced convection cooling, so that the barrier layer 15 sublimes to desorb and remove at the third temperature. Among them, the third flow rate, the first flow rate, and the second flow rate increase in sequence, and the target temperature is higher than the third temperature.

[0118] Finally, by controlling the heating temperature of the heater to be maintained at the target temperature, and by adjusting the fourth flow rate of the cooling gas introduced into the gas cooling channel, the substrate 10 undergoes a third reaction at the fourth temperature to remove the mask pattern 13. The target temperature is not lower than the higher one of the fourth temperature and the third temperature.

[0119] In some embodiments, the gas cooling channels are distributed in a manner parallel to the top surface of the heating base. For example, the gas cooling channels can adopt a planar spiral structure or a central radiation structure, etc., and are distributed in the heating base above the heater.

[0120] Therefore, the embodiments of the present application can achieve the first reaction to the third reaction in the same plasma processing equipment, and complete the semiconductor structure preparation method provided by the embodiments of the present application.

[0121] The embodiments of the present application also provide a semiconductor structure, which is obtained by using the semiconductor structure preparation method provided by the above embodiments.

[0122] Reference Figure 8 . In some embodiments, the semiconductor structure includes a substrate 10, a dielectric layer 11 is provided on the upper surface of the substrate 10, a second etching structure (second trench 161) is provided on the upper surface of the dielectric layer 11, and the bottom of the second etching structure is located on the upper surface of the substrate 10, so that the upper surface of the substrate 10 is exposed from the bottom of the second etching structure. The second etching structure is obtained by the semiconductor structure preparation method provided by the above embodiments. Thus, a semiconductor structure with a patterned dielectric layer 11 having a second etching structure is formed on the upper surface of the substrate 10.

[0123] In some embodiments, the patterned dielectric layer 11 with the second etching structure can be used to provide functions such as insulation, isolation, protection, and process assistance on the substrate 10.

[0124] In summary, in the embodiments of the present application, by using relatively mild neutral particles to react with the material of the dielectric layer 11, the removal of the dielectric layer 11 film is achieved. It not only has an extremely high selectivity ratio for both the mask pattern 13 material and the substrate 10 material, but also can effectively avoid problems such as charge accumulation and lattice damage caused by high-energy ion bombardment in traditional reactive ion etching. Therefore, when preparing a semiconductor structure with an etching structure (the second etching structure), the etching process window can be greatly improved, and the performance of IC devices can be enhanced, which has extremely high application value in the construction of integrated circuit devices, especially in the construction of advanced process devices.

[0125] The above are only the preferred embodiments of the present application, and the embodiments are not intended to limit the protection scope of the present application. Therefore, all equivalent changes made by using the content of the specification and drawings of the present application should be included in the protection scope of the present application by the same token.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Including: Providing a substrate, on one side of which there are successively a dielectric layer and a mask pattern; Using first neutral particles to perform a first reaction with the dielectric layer, etching the surface of the dielectric layer exposed from the side of the mask pattern to a first depth to form a first etching structure; the first neutral particles are obtained by exciting a first reaction gas to form a first plasma and filtering out charged particles in the first plasma; Switching to using second neutral particles to perform a second reaction with the dielectric layer, etching the bottom of the first etching structure to a second depth to form a second etching structure, and generating and adsorbing a solid barrier layer at least on the bottom of the second etching structure through the second reaction; the second neutral particles are obtained by exciting a second reaction gas to form a second plasma and filtering out charged particles in the second plasma; Desorbing the barrier layer to remove it; Wherein, the process of performing the second etching and desorbing the barrier layer is one to multiple times until the surface of the substrate is exposed from the bottom of the second etching structure.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein, The first depth is less than the thickness of the dielectric layer, and the second depth is less than the first depth; and / or, the substrate material includes silicon; and / or, the dielectric layer material includes silicon oxide; And / or, after the surface of the substrate is exposed from the bottom of the second etching structure, it further includes: switching to using third neutral particles to perform a third reaction with the mask pattern to remove the mask pattern; The third neutral particles are obtained by exciting a third reaction gas to form a third plasma and filtering out charged particles in the third plasma.

3. The method for preparing a semiconductor structure according to claim 1, wherein The first reaction gas includes a first fluorine-based gas, and the second reaction gas includes a second fluorine-based gas and a hydrogen-based gas.

4. The method for preparing a semiconductor structure according to claim 3, wherein, The first fluorine-based gas includes NF3, SF6, CHF3, CH2F2, CF4, C4F8 or C2F6, the second fluorine-based gas includes NF3, SF6, CHF3, CH2F2, CF4, C4F8 or C2F6, and the hydrogen-based gas includes NH3.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein, The first fluorine-based gas is NF3, and the first neutral particles include F radicals and NF2 radicals; and / or, the second fluorine-based gas is NF3, the second neutral particles include at least one of NH4F neutral molecules and NH4F.HF neutral molecules, and the barrier layer includes (NH4)2SiF6.

6. The method for preparing a semiconductor structure according to claim 1, wherein, Using a first temperature to perform the first etching, using a second temperature to perform the second etching, and using a third temperature to decompose the barrier layer, and the second temperature, the first temperature and the third temperature increase in sequence.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein, The first temperature is 70°C to 110°C; and / or, the second temperature is 10°C to 40°C; and / or, the third temperature is 150°C to 275°C; and / or, when performing the first etching or the second etching, the pressure is 100 mTorr to 10 Torr, the frequencies of the radio frequency sources include 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, 100 MHz or 2.45 GHz, and the source power is 20 W to 3000 W.

8. The method for preparing a semiconductor structure according to claim 6, wherein, The first temperature, the second temperature and the third temperature are achieved by the following method: Placing the substrate on the top surface of a heating pedestal, wherein a gas cooling channel is provided on the top of the heating pedestal, and the gas cooling channel is used to introduce a cooling gas to adjust the heat transfer capacity of the heating pedestal so that the substrate reaches different required temperatures; Wherein, by heating the heating pedestal to a target temperature and introducing a first flow rate, a second flow rate or a third flow rate of the cooling gas into the gas cooling channel respectively, the substrate is forced to be convectively cooled to the required first temperature, second temperature or third temperature; the third flow rate, the first flow rate and the second flow rate increase in sequence, and the target temperature is higher than the third temperature.

9. The method for fabricating a semiconductor structure according to claim 2, wherein The distance between the bottom of the first etching structure and the substrate surface is 3 Å to 50 nm; and / or, the mask pattern material includes photoresist; and / or, the third reaction gas includes an oxygen-based gas, and the third neutral particle includes an O radical.

10. A semiconductor structure, characterized in that, Obtained by using the semiconductor structure preparation method according to any one of claims 1-9.

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