Preparation method and structure of three-dimensional integrated chip based on SOI CMOS technology

Abstract

The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a preparation method and structure of a three-dimensional integrated chip based on an SOI CMOS process. According to the invention, a plurality of wafers with different functions are prepared by using an SOI CMOS process, and then the plurality of wafers are stacked layer by layer to form a three-dimensional integrated chip through processes such as temporary bonding, substrate removal, wafer alignment, permanent bonding, temporary bonding solution, metal interconnection and the like. The manufacturing method is compatible with a silicon-based process, and the process development difficulty is reduced; on the premise that the performance of the device is not influenced, the substrate can be completely removed, and the interconnection distance between chips is shortened; by adopting a temporary bonding mode, high-precision alignment can be realized through visible light; a layer-by-layer stacking mode that the front faces of the chips are upward is adopted, operation such as mirroring and overturning is not needed in circuit design, and the circuit design difficulty is greatly reduced; and chips of different manufacture procedures can be separately manufactured, so that the chip preparation cost is greatly reduced, and the like.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a preparation method and structure of a three-dimensional integrated chip based on SOI CMOS process. Background Art

[0002] In recent years, the reduction of technology nodes and physical dimensions in advanced silicon-based integrated circuit manufacturing has approached the limit. Therefore, it has become increasingly difficult to improve the integration degree of integrated circuit systems solely by reducing the feature size of MOSFET devices. To meet the pursuit of the comprehensive performance of performance × power consumption × area (PPA) for future integrated circuits, the three-dimensional integration technology in the vertical dimension has been developed to seek breakthroughs. By expanding the integrated circuit system into the three-dimensional space and vertically stacking multiple chips or wafers, higher integration can be achieved within a limited space, the signal transmission path can be shortened, signal delay and power consumption can be reduced, and different chips can be efficiently integrated, laying a foundation for the realization of high-performance and multifunctional integrated systems.

[0003] Compared with wire bonding (WB), the chip integration technology based on through-silicon vias (TSV) achieves shorter interconnections, improves packaging efficiency, reduces device size and weight, eliminates a large number of parasitic capacitances and inductances, reduces system power consumption, and improves speed, as Figure 1 shown. However, the 3D chip stacking packaging design based on TSV technology also faces many challenges: more serious self-heating effects lead to reliability problems such as chip warping, interface cracks, solder ball fractures, device performance degradation, and atomic diffusion; due to the special geometry of TSV links, more complex circuit designs are required to ensure signal integrity.

[0004] In summary, the extremely high thermal management and circuit design difficulties severely restrict the development of 3D packaging technology. The existing three-dimensional integration technologies adopt two methods: wafer-to-wafer bonding or sequential manufacturing. The method of wafer-to-wafer bonding faces difficulties in alignment accuracy and circuit design, while the sequential manufacturing method is incompatible with the existing silicon-based processes. Summary of the Invention

[0005] In view of the pursuit of the comprehensive performance of performance × power consumption × area (PPA) for future integrated circuits, the disadvantages or improvement requirements of existing three-dimensional packaging technologies, and comprehensively considering the maturity of the temporary bonding process, back thinning process, and permanent bonding process, combined with the characteristics of SOI CMOS devices, the present invention innovatively proposes a three-dimensional integrated chip structure and its manufacturing method based on SOI CMOS process. By preparing multiple wafers with different functions through SOI CMOS process, and then through processes such as temporary bonding, substrate removal, wafer alignment, permanent bonding, and de-temporary bonding, multiple wafers are stacked layer by layer to form a three-dimensional integrated chip. The schematic diagram of the chip structure is as Figure 2The three-dimensional integrated chip manufacturing method is compatible with silicon-based processes and can achieve high-precision alignment only through visible light, with advantages such as simple circuit design, small interlayer spacing, and transistor-level interconnectability. Through such a method, not only can wafers with different functions be vertically stacked, greatly reducing the chip area, but also sub-micron-level interlayer spacing can be achieved, shortening the interconnect distance between chips, significantly enhancing the device bandwidth, and reducing chip latency.

[0006] To solve the above technical problems, the present invention provides a preparation method for a three-dimensional integrated chip based on SOI CMOS process, including the following steps: Step S1: Provide a plurality of SOI wafers; Step S2: Process the plurality of SOI wafers through the SOI CMOS process to form a plurality of SOI circuit wafers with different functions; the tops of the SOI circuit wafers are all covered with a passivation layer and polished using the CMP process; Step S3: Use one of the SOI circuit wafers as the first-layer SOI circuit of the three-dimensional integrated chip; Step S4: Spin-coat a temporary bonding adhesive on another SOI circuit wafer and the supporting glass substrate; Step S5: Align the adhesive surfaces of another SOI circuit wafer and the glass substrate, apply pressure, and simultaneously irradiate with ultraviolet light to temporarily bond the two; Step S6: Perform back-thinning processing on the SOI circuit wafer bonded to the glass substrate, and remove the silicon substrate part of the SOI circuit wafer through rough grinding, polishing, chemical etching, and CMP processes to obtain an ultra-thin SOI circuit on the glass substrate; Step S7: Perform plasma surface modification on the ultra-thin SOI circuit and the first-layer SOI circuit; Step S8: Fix the first-layer SOI circuit on the bonding platform, insert the ultra-thin SOI circuit between the first-layer SOI circuit and the lens, grab two alignment marks through the lens, align and approach the ultra-thin SOI circuit and the first-layer SOI circuit, and then clamp the two SOI circuits using a gripper; Step S9: Remove the gasket in the gripper, completely fit the two SOI circuits, and permanently bond the two SOI circuits through pressure application and annealing processes; Step S10: Irradiate the glass substrate with a laser to release the temporary bond of the glass substrate to form two stacked wafers; Step S11: Use through-hole etching, metal filling, and metal wiring processes to metallically interconnect the circuits in the two stacked wafers to form a three-dimensional stacked integrated circuit; Step S12: Repeat the above steps S4 to S11 to continuously stack upward to form a multi-layer stacked three-dimensional integrated circuit.

[0007] Preferably, in the step S1, the SOI wafer includes a silicon film layer, a buried oxide layer, and a silicon substrate.

[0008] Preferably, in the step S2, the SOI CMOS process includes lithography, etching, implantation, oxidation, deposition, annealing, and CMP processes.

[0009] Preferably, in the step S5, the bonding strength of the temporary bonding is greater than 1.7 J / m 2 , to ensure that no peeling occurs in the bonding area during the subsequent rough polishing and CMP processes.

[0010] Preferably, in the step S6, the thickness of the ultra-thin SOI circuit after removing the silicon substrate is less than 10 μm.

[0011] Preferably, in the step S9, the annealing temperature is less than 500 °C and is closest to room temperature to ensure that the annealing temperature does not affect the device performance.

[0012] The present invention also provides a three-dimensional integrated chip structure based on the SOI CMOS process, which is prepared by using the preparation method of a three-dimensional integrated chip based on the SOI CMOS process as described above, and includes multiple layers of SOI circuits; adjacent two layers of SOI circuits are connected through lead-out interconnect tungsten vias and lead-out interconnect metals to form a three-dimensional integrated chip; and it is ensured that the lead-out interconnect tungsten vias can only pass through the buried oxide layer, STI region, and dielectric layer from bottom to top to ensure the electrical signal lead-out of the source and drain electrodes in different layers of SOI circuits, or the electrical signal lead-out of the source and drain electrodes and the gate electrode.

[0013] Preferably, each layer of the SOI circuit includes: a silicon substrate layer, a buried oxide layer, an STI isolation region, a silicon active layer, a dielectric layer, an N-type / P-type source and drain implantation layer, a gate oxide dielectric layer, a polysilicon layer, a self-owned interconnect tungsten via, and a self-owned interconnect metal; in each layer of the SOI circuit, a buried oxide layer is provided on the silicon substrate layer, a silicon active layer and an N-type / P-type source and drain implantation layer are sequentially provided on the buried oxide layer, and the silicon active layers of different devices are isolated by the STI isolation region distributed on the outside, a gate oxide dielectric layer and a polysilicon layer are sequentially provided above the silicon active layer, the dielectric layer is provided on the N-type / P-type source and drain implantation layer, the polysilicon layer, and the STI isolation region to protect each layer of the SOI circuit and provide an interlayer isolation function, and the self-owned interconnect metal exposed on the surface of the dielectric layer is connected to the corresponding N-type / P-type source and drain implantation layer, or to the corresponding N-type / P-type source and drain implantation layer and the polysilicon layer through the self-owned interconnect tungsten via.

[0014] Preferably, in each layer of the SOI circuit, the lower end of the lead-interconnect tungsten through-hole is connected to the lead-interconnect metal and / or the self-interconnect metal.

[0015] Preferably, each layer of transistor devices and circuits is formed by the SOI CMOS process with the silicon substrate layer, buried oxide layer, STI isolation region, silicon active layer, N-type / P-type source-drain injection layer, gate oxide dielectric layer, polysilicon layer, dielectric layer, self-interconnect tungsten through-hole, and self-interconnect metal; the circuit is a circuit formed by interconnecting a single device and / or multiple devices.

[0016] Compared with the prior art, the present invention has the following beneficial effects: Compared with the existing three-dimensional integration technology that uses two methods of wafer-to-wafer bonding or sequential manufacturing, the present invention is based on the SOI CMOS process. Through processing techniques such as temporary bonding, substrate removal, wafer alignment, permanent bonding, and de-temporary bonding, multiple wafers are stacked layer by layer to form a three-dimensional integrated chip. That is, it is compatible with the existing silicon-based process, simplifies the process steps, reduces the difficulty of circuit design, and improves the chip performance. That is, the three-dimensional integrated chip and its manufacturing method have the following advantages: The present invention stacks multiple wafers layer by layer to form a three-dimensional integrated chip, greatly reducing the chip area; the present invention uses the SOI CMOS process, which can completely remove the substrate without affecting the device performance, shorten the inter-chip interconnect distance, greatly improve the bandwidth of the device, and reduce the chip delay; the present invention uses the SOI CMOS process with fewer process steps and is compatible with the standard silicon-based process; the present invention uses a process of first manufacturing wafers separately, then bonding, and finally performing through-hole interconnection, avoiding defects such as solder ball fracture common in conventional three-dimensional packaging and making it easier to ensure signal integrity; the present invention uses a temporary bonding method, which can achieve high-precision alignment through visible light and can achieve transistor-level alignment and interconnection; the present invention uses a method of stacking the chips face up layer by layer, and the circuit design does not require operations such as mirroring and flipping, greatly reducing the difficulty of circuit design; the present invention can manufacture chips with different processes separately and then integrate them using the method in the present invention to form a three-dimensional integrated system-on-chip, greatly reducing the chip preparation cost. Description of the Drawings

[0017] Figure 1 Schematic diagram of a three-dimensional integrated chip formed by the prior art using three-dimensional packaging technology.

[0018] Figure 2 Schematic diagram of a three-dimensional integrated chip structure based on the SOI CMOS process provided by the present invention.

[0019] Figure 3 Structural diagram of two wafers 1 and 2 processed and manufactured by the present invention.

[0020] Figure 4 The preparation flowchart of temporary bonding of the wafer 2 and substrate removal provided by the present invention.

[0021] Figure 5 The preparation flowchart of wafer surface modification and permanent bonding provided by the present invention.

[0022] Figure 6 The preparation flowchart of de-temporary bonding of the wafer and metal interconnection provided by the present invention. Specific embodiments

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0024] As Figure 2 shown, the embodiment of the present invention specifically provides a three-dimensional integrated chip structure based on the SOI CMOS process, including: each layer of transistor devices and corresponding circuits formed by a silicon substrate layer 201, a buried oxide layer 202, STI isolation regions 203, a silicon active layer 204, an N-type / P-type source / drain injection layer 205, a dielectric layer 206, self-interconnect tungsten vias 207, self-interconnect metal 208, a polysilicon layer 209, and a gate oxide dielectric layer 210. The circuits of two or more layers are connected through lead-out interconnect tungsten vias 211 and lead-out interconnect metal 212 to form a three-dimensional integrated chip. And it is ensured that the lead-out interconnect tungsten vias can only pass through the buried oxide layer 202, STI isolation regions 203, and dielectric layer 206 from bottom to top, so as to ensure the electrical signal extraction of the source / drain in different layers of the SOI circuit, or the electrical signal extraction of the source / drain and the gate (the structure for the electrical signal extraction of the gate is not shown in Figure 2 , and its structure and process are the same as those for the electrical signal extraction of the source / drain, so it will not be described in detail here).

[0025] As Figures 3 to 6 shown, a method for preparing a three-dimensional integrated chip structure based on the SOI CMOS process disclosed in the embodiment of the present invention at least includes: Step S1, providing two or more SOI wafers, where the SOI wafers include a silicon film layer, a buried oxide layer, and a silicon substrate.

[0026] Step S2, using process technologies such as photolithography, etching, implantation, oxidation, deposition, annealing, and chemical mechanical polishing (CMP) to process the multiple SOI wafers to form multiple SOI circuit wafers with different functions; the tops of the SOI circuits are all covered with a passivation layer and polished using the CMP process.

[0027] Optionally, all of the process technologies are conventional silicon-based semiconductor processing technologies existing in the art; Step S3: Take one of the SOI wafers as the first layer of the three-dimensional integrated chip, and reprocess the other SOI wafers.

[0028] Step S4: Spin coat the temporary bonding adhesive 311 onto the other SOI wafers and the supporting glass substrate 312.

[0029] Step S5: Align the adhesive surfaces of the other SOI wafers and the supporting glass substrate, apply pressure, and irradiate with ultraviolet light simultaneously to temporarily bond the two together.

[0030] Optionally, the bonding strength of the temporary bonding is greater than 1.7 J / m 2 , which can ensure that the bonded area does not fall off during subsequent processes such as rough polishing and CMP.

[0031] Step S6: Perform back thinning processing on the SOI circuit bonded to the glass substrate, and remove the Si substrate part of the SOI circuit through four processes: rough grinding, polishing, chemical etching, and CMP to obtain an ultra-thin SOI circuit on the glass wafer.

[0032] Optionally, the thickness of the ultra-thin SOI circuit after removing the Si substrate is less than 10 microns.

[0033] Step S7: Perform plasma surface modification on the ultra-thin SOI circuit and the first-layer SOI circuit wafer 1. Step S8: Fix the first-layer SOI circuit on the bonding platform and use the lens to capture the alignment marks; insert the ultra-thin SOI circuit on the glass wafer between the first-layer SOI circuit and the lens, and capture the alignment marks through the lens; through the two alignment marks, align and approach the ultra-thin SOI circuit on the glass substrate and the first-layer SOI circuit, and then use the gripper to clamp the two SOI circuits.

[0034] Step S9: Remove the gasket in the gripper, completely fit the two SOI circuits, and permanently bond the two circuits through pressure and annealing processes.

[0035] Optionally, to ensure that the annealing temperature does not affect the device performance, the annealing temperature is less than 500 °C and as close to room temperature as possible.

[0036] Step S10: Use laser to irradiate the supporting glass substrate to release the temporary bonding between the glass substrate and the SOI circuit, forming two stacked wafers.

[0037] Step S11: Use through-hole etching, metal filling, and metal wiring processes to interconnect the circuits in the two wafers to form a three-dimensional stacked integrated circuit.

[0038] In step S12, by repeating steps S4 - S11, continuous upward stacking can be achieved to form a multi - layer stacked three - dimensional integrated circuit.

[0039] In summary, by adopting the present invention, chips with different manufacturing processes can be three - dimensionally integrated to form a system - on - chip. The monolithic three - dimensional integration technology based on the SOI CMOS process technology proposed in the present invention, due to the presence of the buried oxide layer, can completely remove the substrate during back - thinning, thereby shortening the inter - wafer interconnect length and eliminating the alloy solder balls used in TSV bonding. Compared with the TSV technology, it further improves the integration degree, and at the same time avoids defects such as interface cracks and solder ball fractures, making it easier to ensure signal integrity. It is a very promising 3D integration solution.

[0040] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.

Claims

1. A method for fabricating a three-dimensional integrated chip based on SOI CMOS process, characterized in that, Including the following steps: Step S1: Provide a plurality of SOI wafers; Step S2: Process the plurality of SOI wafers through the SOI CMOS process to form a plurality of SOI circuit wafers with different functions; the tops of the SOI circuit wafers are all covered with a passivation layer and polished using the CMP process; Step S3: Use one of the SOI circuit wafers as the first layer of SOI circuit of the three-dimensional integrated chip; Step S4: Spin-coat a temporary bonding adhesive on another SOI circuit wafer and the supporting glass substrate; Step S5: Align the adhesive surface of another SOI circuit wafer with the adhesive surface of the glass substrate and apply pressure, and at the same time irradiate with ultraviolet light to temporarily bond the two; Step S6: Perform back thinning on the SOI circuit wafer bonded to the glass substrate, and remove the silicon substrate part of the SOI circuit wafer through rough grinding, polishing, chemical etching and CMP processes to obtain an ultra-thin SOI circuit on the glass substrate; Step S7: Perform plasma surface modification on the ultra-thin SOI circuit and the first layer of SOI circuit; Step S8: Fix the first layer of SOI circuit on the bonding platform, insert the ultra-thin SOI circuit between the first layer of SOI circuit and the lens, grab two alignment marks through the lens, align and approach the ultra-thin SOI circuit and the first layer of SOI circuit, and then use a gripper to clamp the two SOI circuits; Step S9: Remove the gasket in the gripper, completely fit the two SOI circuits, and permanently bond the two SOI circuits through a pressure application and annealing process; Step S10: Use laser to irradiate the glass substrate to release the temporary bonding of the glass substrate to form two stacked wafers; Step S11: Use through-hole etching, metal filling and metal wiring processes to metallically interconnect the circuits in the two stacked wafers to form a three-dimensional stacked integrated circuit; Step S12: Repeat the above steps S4 to S11 to continuously stack upward to form a multi-layer stacked three-dimensional integrated circuit.

2. The preparation method of a three-dimensional integrated chip based on SOI CMOS process according to claim 1, characterized in that, In the step S1, the SOI wafer includes a silicon film layer, a buried oxide layer and a silicon substrate.

3. The manufacturing method of a three-dimensional integrated chip based on SOI CMOS process as claimed in claim 1, wherein, In the step S2, the SOI CMOS process includes using photolithography, etching, implantation, oxidation, deposition, annealing and CMP processes.

4. The manufacturing method of a three-dimensional integrated chip based on SOI CMOS process as claimed in claim 1, characterized in that, In the step S5, the bonding strength of the temporary bonding is greater than 1.7 J / m 2 , so as to ensure that no peeling phenomenon occurs in the bonding area during the subsequent rough polishing and CMP processes.

5. The manufacturing method of a three-dimensional integrated chip based on the SOI CMOS process according to claim 1, characterized in that In the step S6, the thickness of the ultra-thin SOI circuit after removing the silicon substrate is less than 10 μm.

6. The preparation method of a three-dimensional integrated chip based on SOI CMOS process according to claim 1, characterized in that, In the step S9, the annealing temperature of the annealing process is less than 500 °C and is closest to room temperature to ensure that the annealing temperature does not affect the device performance.

7. A three-dimensional integrated chip structure based on SOI CMOS process, which is prepared by using the preparation method of a three-dimensional integrated chip based on SOI CMOS process according to any one of claims 1 to 6, characterized in that, Including multiple layers of SOI circuits; connecting adjacent two layers of SOI circuits through lead-out interconnect tungsten vias and lead-out interconnect metals to form a three-dimensional integrated chip; and ensuring that the lead-out interconnect tungsten vias can only pass through the buried oxide layer, STI region and dielectric layer from bottom to top to ensure the electrical signal lead-out of the source and drain electrodes in different layers of SOI circuits, or the electrical signal lead-out of the source and drain electrodes and the gate electrode.

8. A three-dimensional integrated chip structure based on the SOI CMOS process according to claim 7, characterized in that, Each layer of the SOI circuit includes: a silicon substrate layer, a buried oxide layer, STI isolation regions, a silicon active layer, a dielectric layer, an N-type / P-type source / drain injection layer, a gate oxide dielectric layer, a polysilicon layer, self-interconnect tungsten vias, and self-interconnect metal; in each layer of the SOI circuit, the buried oxide layer is disposed on the silicon substrate layer, the silicon active layer and the N-type / P-type source / drain injection layer are sequentially disposed on the buried oxide layer, and the silicon active layers of different devices are isolated by the STI isolation regions distributed on the outside. The gate oxide dielectric layer and the polysilicon layer are sequentially disposed above the silicon active layer. The dielectric layer is disposed on the N-type / P-type source / drain injection layer, the polysilicon layer, and the STI isolation regions to protect each layer of the SOI circuit and provide an interlayer isolation function. The self-interconnect tungsten vias connect the self-interconnect metal exposed on the surface of the dielectric layer to the corresponding N-type / P-type source / drain injection layer, or to the corresponding N-type / P-type source / drain injection layer and the polysilicon layer.

9. A three-dimensional integrated chip structure based on SOI CMOS process as claimed in claim 8, wherein, In each layer of the SOI circuit, the lower end of the lead-out interconnect tungsten via is connected to the lead-out interconnect metal and / or the self-interconnect metal.

10. A three-dimensional integrated chip structure based on SOI CMOS process according to claim 8, characterized in that, The silicon substrate layer, the buried oxide layer, the STI isolation regions, the silicon active layer, the N-type / P-type source / drain injection layer, the gate oxide dielectric layer, the polysilicon layer, the dielectric layer, the self-interconnect tungsten vias, and the self-interconnect metal are formed into each layer of transistor devices and circuits through the SOI CMOS process; the circuit is a circuit formed by interconnecting a single device and / or multiple devices.

Images