Method for preparing strained SGOI substrate structure through ion implantation process

Abstract

The invention discloses a method for preparing a strain SGOI substrate structure through an ion implantation process, and belongs to the technical field of semiconductors, and the method comprises the steps: preparing a first wafer and a second wafer which are wafer substrate bare chips; generating a germanium-silicon layer on the surface of the first wafer; performing thermal oxidation treatment on the surface of the second wafer; carrying out surface modification treatment on the surface of the first wafer through an ion implantation process; performing a hydrogen ion implantation process on the first wafer to enable the first wafer to form a weakening layer in the germanium-silicon layer; combining the first wafer with the second wafer through low-temperature bonding; stripping along the weakening layer to form a top germanium-silicon film on the second wafer; recrystallizing the top germanium-silicon thin film through thermal annealing treatment; and etching the top germanium-silicon thin film to the required thickness through wet etching treatment. The contact interface between the germanium-silicon and the oxide is improved, the thickness of the germanium-silicon thin film on the top layer is controllable, the required ultrathin thickness can be achieved, the uniformity of the thin film is good, and the surface defects are few.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor design and manufacturing, and particularly relates to a preparation method of a strained SGOI substrate structure by an ion implantation process. Background Art

[0002] Directly bonding germanium-silicon with a silicon wafer having a silicon dioxide insulating layer to form a strained SGOI structure (Strained SiGe on Insulator), which is a silicon-based germanium-silicon material with high hole mobility and has excellent application development. The disadvantages of the prior art are that in the strained SGOI technology, if a germanium-silicon material layer is directly formed on the insulating oxide layer, due to the relatively poor contact interface between the germanium-silicon material and the insulating oxide, especially the high interface state density, it will cause serious scattering and leakage, thereby affecting the device performance. In the matching with the substrate, a large number of defects will be generated, such as surface roughness (RMS), defect density, and dislocation density (TD), etc. Especially, dislocations will further reduce the degree of strain, thereby reducing the mobility of carriers. In addition, Ge in SiGe is prone to diffusion during the heat treatment process, reducing the degree of strain. When Ge diffuses to the oxide layer interface, the surface defect concentration will greatly increase, thereby reducing the performance and reliability of the MOS transistor. Summary of the Invention

[0003] Based on the technical problems existing in the prior art, the present invention provides a preparation method of a strained SGOI substrate structure by an ion implantation process, which solves the problems in the existing preparation methods such as the relatively poor contact interface between the germanium-silicon material and the insulating oxide, the large dislocation density, the ultra-thin thickness of the top germanium-silicon thin film being difficult to prepare and control, the uneven film thickness at the crystal edge, and the large number of defects, etc., so as to achieve beneficial technical effects such as improving the performance and reliability of semiconductor devices.

[0004] According to the technical solution of the present invention, the present invention provides a preparation method of a strained SGOI substrate structure by an ion implantation process, including the following steps:

[0005] Step S1, prepare a first wafer and a second wafer, and both the first wafer and the second wafer are bare wafers of the wafer substrate;

[0006] Step S2, generate a germanium-silicon layer on the surface of the first wafer;

[0007] Step S3, perform a thermal oxidation treatment on the surface of the second wafer to form an oxide layer on the surface of the second wafer;

[0008] Step S4, perform a surface modification treatment on the surface of the first wafer by an ion implantation process to form a surface modification layer;

[0009] Step S5: Perform a hydrogen ion implantation process on the first wafer to form a weakened layer within the germanium-silicon layer of the first wafer;

[0010] Step S6: After surface cleaning the first wafer and the second wafer, bond the surface of the surface modification layer of the first wafer to the surface of the oxide layer of the second wafer through low-temperature bonding;

[0011] Step S7: Peel off the first wafer and a part of the germanium-silicon layer along the weakened layer, and the remaining part forms a top germanium-silicon thin film on the second wafer;

[0012] Step S8: Perform recrystallization on the top germanium-silicon thin film through thermal annealing treatment;

[0013] Step S9: Etch the top germanium-silicon thin film to the required thickness through wet etching treatment.

[0014] In some embodiments, in step S4, the ions used in the ion implantation process are one or a combination of two or more of carbon ions, nitrogen ions, hydrogen ions, helium ions, and argon ions.

[0015] In some embodiments, in step S4, the ion implantation process is low-temperature ion implantation, and the temperature of the ion implantation process is ≤ 0 °C.

[0016] In some embodiments, in step S5, the implantation energy of the hydrogen ion implantation process is 50 keV to 200 keV, and / or the implantation dose is 1 × 10^16 atoms / cm² to 1 × 10^18 atoms / cm².

[0017] In some embodiments, in step S5, the temperature of the hydrogen ion implantation process is ≤ 60 °C.

[0018] In some embodiments, in step S6, the temperature of the low-temperature bonding is ≤ 200 °C.

[0019] In some embodiments, in step S8, the thermal annealing treatment is high-temperature thermal annealing treatment, and the temperature of the thermal annealing treatment is ≥ 500 °C.

[0020] In some embodiments, in step S8, the temperature of the thermal annealing treatment is ≤ 700 °C.

[0021] In some embodiments, after step S9, the top germanium-silicon thin film reaches the required ultra-thin thickness, and the ultra-thin thickness is ≤ 20 nm.

[0022] Compared with the prior art, the beneficial technical effects of the present invention are as follows:

[0023] The preparation method of the strain SGOI substrate structure of the present invention realizes a semiconductor structure with an ultrathin germanium-silicon film on the top layer, a flat surface, and few defects through an innovative process flow. Among them, surface modification treatment is carried out by ion implantation to optimize the surface condition of germanium-silicon. The low-temperature bonding process is adopted to further improve the contact interface between germanium-silicon and the oxide, ensuring a flat interface. At the same time, the low-temperature process avoids the problem that germanium in germanium-silicon diffuses significantly and affects device performance. The hydrogen ion implantation process is used to form a flat and easily peelable weakening layer. Wet etching is used to thin the top germanium-silicon film. The wet etching rate is slow in germanium-silicon materials, so the thickness is controllable and can reach the required ultrathin thickness, and the film uniformity is good. At the same time, the surface is relatively flat, the surface defects are few, and good single crystal properties are maintained. Brief Description of the Drawings

[0024] Figure 1 is the flowchart of the method provided by the present invention.

[0025] Description of the reference numerals in the drawings:

[0026] A, the first wafer; B, the second wafer; 1, germanium-silicon layer; 2, surface modification layer; 3, weakening layer; 4, oxide layer; 5, top germanium-silicon film. Detailed Embodiments

[0027] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.

[0028] In addition, it should be noted that for the sake of convenience of description, only the parts related to the relevant invention are shown in the drawings. Without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. Without conflict, the order of the steps in the present invention can be adjusted, and the step numbers do not limit that the present invention must be strictly carried out in the order of the numbers.

[0029] It should be noted that the concepts such as "first" and "second" mentioned in the present invention are only used to distinguish different devices, modules, or units, and are not used to limit the order of the functions performed by these devices, modules, or units or their interdependent relationships.

[0030] It should be noted that the modifications of "one" and "multiple" mentioned in the present invention are illustrative rather than restrictive. Those skilled in the art should understand that unless clearly specified otherwise in the context, it should be understood as "one or more".

[0031] The present invention provides a preparation method of a strained SGOI substrate structure by an ion implantation process. Without changing the sandwich structure of the SGOI substrate structure, the preparation method is redesigned. A typical preparation method of the present invention includes: preparing two wafer substrate bare chips A and B; depositing a germanium-silicon thin film (SiGe Deposition) on the surface of wafer A and performing a thermal oxidation treatment on the surface of wafer B; performing a low-temperature ion implantation process on the surface of wafer A and carrying out a surface modification treatment; performing a hydrogen ion implantation process on wafer A; first cleaning the surfaces of wafer A and wafer B and then performing a low-temperature bonding; stripping wafer A to form a top germanium-silicon thin film, and then annealing the top germanium-silicon thin film at a high temperature to perform re-crystallization; using a wet etching (WET Etch) process to etch the top germanium-silicon to an ultra-thin film thickness. The main purpose of the present invention is to solve problems in the existing preparation methods such as a relatively poor contact interface between the germanium-silicon material and the insulating oxide, a relatively large dislocation density, difficulty in preparing and controlling the required ultra-thin thickness of the top germanium-silicon thin film, uneven film thickness and many defects at the wafer edge, etc., so as to achieve beneficial technical effects such as improving the performance and reliability of semiconductor devices.

[0032] Please refer to Figure 1 , a preparation method of a strained SGOI substrate structure by an ion implantation process of the present invention, includes the following steps.

[0033] Step S1: Prepare a first wafer A and a second wafer B, both the first wafer A and the second wafer B are wafer substrate bare chips.

[0034] Step S2: Generate a germanium-silicon layer 1 (SiGe) on the surface of the first wafer A; specifically, deposit a germanium-silicon thin film (SiGe Deposition) on the surface of the first wafer A to generate a high-quality and low-defect germanium-silicon layer 1.

[0035] Step S3: Perform a thermal oxidation treatment on the surface of the second wafer B to form an oxide layer 4 on the surface of the second wafer B. The oxide layer 4 is specifically a high-quality and low-defect silicon dioxide insulating oxide layer.

[0036] Step S4: Perform a surface modification treatment on the surface of the first wafer A by an ion implantation process to form a surface modification layer 2. Specifically, in this step S4, it is a low-energy and low-dose ion implantation, and the ions used in the ion implantation process are one or a combination of two or more of carbon ions, nitrogen ions, hydrogen ions, helium ions, and argon ions. And preferably, the ion implantation process is a low-temperature ion implantation, and the temperature of the ion implantation process is, for example, ≤ 0 °C.

[0037] Step S5: Perform a hydrogen ion implantation process on the first wafer A to form a weakened layer 3 within the germanium-silicon layer 1 of the first wafer A. Preferably, the implantation energy of the hydrogen ion implantation process is 50 keV to 200 keV, and / or the implantation dose is 1×10^16 atoms / cm² to 1×10^18 atoms / cm². The temperature of the hydrogen ion implantation process is preferably ≤60°C. Hydrogen ions are relatively small. When they are implanted into the germanium-silicon layer 1 to a certain depth, a structure similar to bubbles is formed, which is the weakened layer of the structure. Since this layer is a weak link, it can be peeled off along the precise position of this layer in subsequent steps to initially obtain the top layer structure of SGOI. Among them, hydrogen ion implantation is preferably at a high dose. Compared with low-dose implantation, high-dose implantation can make the weakened layer 3 smoother, that is, make the surface generated after peeling smoother. The depth of hydrogen ion implantation, that is, the depth position of the weakened layer 3, is directly related to the implantation energy, and the required parameters are obtained through design calculations. Using room temperature or preferably low-temperature ion implantation process can avoid the diffusion of implanted ions, control the carbon ions to be uniformly implanted into a certain position in the substrate, with precise position and narrow distribution range, that is, form an implanted layer with precise position and smoothness, namely the weakened layer 3. At the same time, in the case of lower temperature implantation, a lower dose implantation can be selected to further avoid lattice damage and reduce defects.

[0038] Step S6: After surface cleaning the first wafer A and the second wafer B, bond the surface of the surface modification layer 2 of the first wafer A to the surface of the oxide layer 4 of the second wafer B through low-temperature bonding. In the embodiment, when bonding, the first wafer A is flipped and inverted on the upper surface of the second wafer B. Preferably, the temperature of the low-temperature bonding is, for example, ≤200°C.

[0039] Step S7: Peel off the first wafer A and part of the germanium-silicon layer 1 along the weakened layer 3, and the remaining part forms the top germanium-silicon thin film 5 on the second wafer B.

[0040] Step S8: Recrystallize the top germanium-silicon thin film 5 through thermal annealing treatment. Among them, preferably, the thermal annealing treatment is high-temperature thermal annealing treatment, and the temperature of the thermal annealing treatment is, for example, ≥500°C. More preferably, the temperature of the thermal annealing treatment is ≤700°C, and further, for example, 500°C to 700°C. In this way, it can be avoided that germanium in the germanium-silicon reduces the strain degree due to the diffusion during the heat treatment process and affects the device performance.

[0041] Step S9, the top germanium-silicon thin film 5 is etched to a required thickness through wet etching treatment. Thus, a strained SGOI substrate structure is obtained. The strained SGOI substrate structure is a substrate (formed by the second wafer B), an oxide layer 4, a surface modification layer 2 (serving as an interface layer in the structure), and a top germanium-silicon thin film 5 stacked in sequence. Preferably, after step S9, the top germanium-silicon thin film 5 reaches a required ultra-thin thickness, and the ultra-thin thickness is ≤20 nm. In the prior art, when thinning the top structure, chemical mechanical polishing is generally used, which has the problems of difficult layer thickness control, large thickness drops (e.g., exceeding 10%) at the crystal edges, and surface scratches. For the relatively thick top germanium-silicon thin film currently, the influence of defects on performance is not very significant. However, for the ultra-thin top germanium-silicon thin film at the nanoscale required in advanced processes, the above defects will significantly affect performance. The present invention adopts a wet etching process, which can make the film uniformity consistent, achieve a thickness drop below 2%, and have no surface defects.

[0042] In summary, the strain SGOI substrate structure of the present invention is prepared by an ion implantation process. Through an innovative process flow, a semiconductor structure with an ultrathin germanium-silicon film on the top layer, a flat surface, and few defects is achieved. Among them, surface modification treatment is carried out by ion implantation to optimize the surface condition of germanium-silicon. The low-temperature bonding process is adopted to further improve the contact interface between germanium-silicon and the oxide, ensuring a flat interface. At the same time, the low-temperature process avoids the obvious diffusion of germanium in germanium-silicon, which affects the device performance. The hydrogen ion implantation process is used to form a flat and easily peelable weakening layer. Wet etching is used to thin the top germanium-silicon film. The wet etching rate is slower in germanium-silicon materials, so the thickness is controllable and can reach the required ultrathin thickness, and the film uniformity is better. At the same time, the surface is relatively flat, the surface defects are few, and good single-crystallinity is maintained. In addition, for the transistor prepared by the strain SGOI technology, the germanium-silicon film defines the source-drain junction depth and depletion region, which can improve short-channel effects such as DIBL (Drain Induced Barrier Lowering), further improve the subthreshold characteristics of the device, and reduce the static power consumption of the circuit. Introducing strain into the channel of the MOS device can increase the carrier mobility. In addition, the strain SGOI transistor does not require channel doping, which can avoid effects such as RDF (Random Dopants Fluctuation) and the reduction of carrier mobility, and maintain a stable threshold voltage (threshold voltage, Vth). Different from the 3D transistor structure adopted by the FinFET process, the strain SGOI is a planar process technology, which can effectively reduce the process difficulty. Compared with the traditional Bulk Silicon technology, the strain SGOI can provide better transistor electrostatic characteristics, and the buried oxide layer can reduce the parasitic capacitance between the source and the drain. In addition, this technology can effectively limit the electron flow between the source and the drain, significantly reducing the leakage current performance of the device. In addition to through the gate, the strain SGOI can also control the transistor behavior through the bottom substrate of the device to achieve the back bias control function.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A preparation method of a strained SGOI substrate structure by an ion implantation process, characterized in that, It includes the following steps: Step S1, prepare a first wafer (A) and a second wafer (B), both the first wafer (A) and the second wafer (B) are bare die of wafer substrates; Step S2, form a layer of germanium-silicon layer (1) on the surface of the first wafer (A); Step S3, perform thermal oxidation treatment on the surface of the second wafer (B) to form an oxide layer (4) on the surface of the second wafer (B); Step S4, perform surface modification treatment on the surface of the first wafer (A) by ion implantation process to form a surface modification layer (2); Step S5, perform hydrogen ion implantation process on the first wafer (A) to form a weakened layer (3) in the germanium-silicon layer (1) of the first wafer (A); Step S6, after surface cleaning of the first wafer (A) and the second wafer (B), bond the surface of the surface modification layer (2) of the first wafer (A) to the surface of the oxide layer (4) of the second wafer (B) by low-temperature bonding; Step S7, peel off the first wafer (A) and part of the germanium-silicon layer (1) along the weakened layer (3), and the remaining part forms a top germanium-silicon thin film (5) on the second wafer (B); Step S8, perform recrystallization on the top germanium-silicon thin film (5) by thermal annealing treatment; Step S9, etch the top germanium-silicon thin film (5) to the required thickness by wet etching treatment.

2. The preparation method of the strained SGOI substrate structure according to claim 1 by ion implantation process, characterized in that, In step S4, the ions used in the ion implantation process are one or a combination of two or more of carbon ions, nitrogen ions, hydrogen ions, helium ions, and argon ions.

3. The manufacturing method of the strain SGOI substrate structure according to claim 1 by ion implantation process, characterized in that, In step S4, the ion implantation process is low-temperature ion implantation, and the temperature of the ion implantation process ≤ 0 °C.

4. The manufacturing method of the strained SGOI substrate structure according to claim 1 by ion implantation process, characterized in that, In step S5, the implantation energy of the hydrogen ion implantation process is 50 keV to 200 keV, and / or the implantation dose is 1×1016 atoms / cm2 to 1×1018 atoms / cm2.

5. The method for preparing the strained SGOI substrate structure according to claim 1 by an ion implantation process, characterized in that, In step S5, the temperature of the hydrogen ion implantation process ≤ 60 °C.

6. The preparation method of the strained SGOI substrate structure according to claim 1 by an ion implantation process, characterized in that, In step S6, the temperature of the low-temperature bonding ≤ 200 °C.

7. The manufacturing method of the strain SGOI substrate structure according to claim 1 by ion implantation process, characterized in that, In step S8, the thermal annealing treatment is high-temperature thermal annealing treatment, and the temperature of the thermal annealing treatment ≥ 500 °C.

8. The preparation method of the strained SGOI substrate structure according to claim 1 by an ion implantation process, characterized in that, In step S8, the temperature of the thermal annealing treatment ≤ 700 °C.

9. The preparation method of the strained SGOI substrate structure according to claim 1 by an ion implantation process, characterized in that, After step S9, the top germanium-silicon thin film (5) reaches the required ultra-thin thickness, and the ultra-thin thickness ≤ 20 nm.

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