Semiconductor structure and method for manufacturing the same

Abstract

The present application relates to a semiconductor structure and a method for manufacturing the same, comprising: providing a first wafer, the first wafer including a central region and an edge region, the edge region being located around the central region; a metal interconnect layer being formed on the surface of the first wafer, and a portion of the metal interconnect layer located within the edge region having a void; forming a dielectric layer on the metal interconnect layer, the dielectric layer at least filling the void; forming a barrier layer on the dielectric layer, the barrier layer extending to cover the surface and sidewalls of the metal interconnect layer; performing a planarization process to expose the surface of the metal interconnect layer; and performing a hybrid bonding process on the first wafer. The present application reduces or avoids the risk of metal diffusion in the metal interconnect layer, while also reducing or avoiding the risk of edge chipping or cracking of the first wafer, thereby helping to improve the wafer yield.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] As the development of very large-scale integrated circuits (VLSIs) approaches their physical limits, three-dimensional integrated circuits (3D ICs), with their advantages in both physical size and cost, are an effective way to extend Moore's Law and address advanced packaging challenges. Hybrid bonding technology, among other things, can simultaneously interconnect thousands of chips by bonding two wafers, significantly improving chip performance while reducing production costs.

[0003] The challenge of hybrid bonding technology lies in achieving internal metal interconnects and maintaining high yield after interconnection. Poor edge bonding creates a significant risk of edge cracking during subsequent manufacturing processes, severely impacting product yield. Therefore, a method is needed to ensure high yield after hybrid bonding while reducing or eliminating the risk of edge cracking during subsequent manufacturing processes. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a manufacturing method thereof, which can reduce or avoid the risk of wafer edge cracking in subsequent processes while ensuring a high wafer yield.

[0005] In a first aspect, the present application provides a method for manufacturing a semiconductor structure, comprising:

[0006] Providing a first wafer, the first wafer comprising a central region and an edge region, the edge region being located around the central region, a metal interconnection layer being formed on a surface of the first wafer, and a portion of the metal interconnection layer located within the edge region having a cavity;

[0007] forming a dielectric layer on the metal interconnection layer, wherein the dielectric layer at least fills the void;

[0008] forming a barrier layer on the dielectric layer, wherein the barrier layer extends to cover the surface and sidewalls of the metal interconnection layer;

[0009] performing a planarization process to expose the surface of the metal interconnection layer;

[0010] A hybrid bonding process is performed on the first wafer.

[0011] In one embodiment, the steps before forming the dielectric layer on the metal interconnect layer further include:

[0012] removing a portion of the metal interconnection layer in the edge region away from the central region;

[0013] forming a bonding layer on the metal interconnection layer;

[0014] A portion of the bonding layer in the edge region away from the central region is removed.

[0015] In one embodiment, along the radial direction of the first wafer, the width of the removed portion of the metal interconnection layer is greater than the width of the removed portion of the bonding layer.

[0016] In one embodiment, the metal interconnection layer includes an interlayer dielectric structure formed on the first wafer and trenches and through holes formed in the interlayer dielectric structure, wherein metal material is electroplated in the trenches and the through holes.

[0017] In one embodiment, the process of forming the interlayer dielectric structure includes:

[0018] forming a first dielectric layer on the first wafer;

[0019] performing a planarization process on the first dielectric layer to remove at most a portion of the first dielectric layer;

[0020] forming a dielectric barrier layer on the first dielectric layer;

[0021] A second dielectric layer is formed on the dielectric barrier layer to form the interlayer dielectric structure including the first dielectric layer, the dielectric barrier layer and the second dielectric layer.

[0022] In one embodiment, during the planarization process of the first dielectric layer, the thickness of the first dielectric layer is reduced by 5 kÅ to 20 kÅ, and the remaining thickness of the first dielectric layer after the planarization process is greater than zero and less than or equal to 3 kÅ.

[0023] In one embodiment, the hybrid bonding process includes:

[0024] Providing a second wafer, wherein a metal wiring layer is formed on a front surface of the second wafer;

[0025] bonding the front surface of the first wafer and the front surface of the second wafer so that a projection of the metal interconnection layer in a direction perpendicular to the surface of the second wafer overlaps with a projection of the metal wiring layer in a direction perpendicular to the surface of the second wafer, thereby connecting the metal wiring layer and the metal interconnection layer;

[0026] performing an annealing process;

[0027] The first wafer and the second wafer are respectively one of a logic wafer and a pixel wafer, and the first wafer and the second wafer are of different types.

[0028] In one embodiment, after completing the hybrid bonding process, the method for manufacturing the semiconductor structure further includes:

[0029] Perform defect detection on the semiconductor structure obtained after hybrid bonding.

[0030] In one embodiment, the thickness of the dielectric layer ranges from 1 kÅ to 5 kÅ, and the thickness of the barrier layer ranges from 0.5 kÅ to 2 kÅ.

[0031] In a second aspect, the present application also provides a semiconductor structure, which is prepared using the above-mentioned semiconductor structure manufacturing method.

[0032] The unexpected effects of the present application are: by forming a dielectric layer that fills the voids, the risk of crystal edge cracking in subsequent processes is reduced or avoided; by forming a barrier layer covering the surface and sidewalls of the metal interconnection layer, the risk of metal diffusion in the metal interconnection layer is reduced or avoided, and at the same time, the risk of edge collapse or crystal edge cracking of the first wafer is reduced or avoided, thereby helping to improve the yield of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A flowchart of a method for manufacturing a semiconductor structure provided in one embodiment of the present application.

[0035] Figure 2 This is a structural schematic diagram corresponding to the step of providing a first wafer in the method for manufacturing a semiconductor structure provided in one embodiment of the present application.

[0036] Figure 3 This is a structural schematic diagram corresponding to the step of forming a dielectric layer on a metal interconnection layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present application.

[0037] Figure 4 This is a structural schematic diagram corresponding to the step of forming a barrier layer on a dielectric layer in a method for manufacturing a semiconductor structure provided in one embodiment of the present application.

[0038] Figure 5 A schematic structural diagram corresponding to the step of performing a planarization process to expose the surface of a metal interconnection layer in a method for manufacturing a semiconductor structure provided in one embodiment of the present application.

[0039] Figure 6A structural schematic diagram corresponding to the steps of performing a hybrid bonding process in a method for manufacturing a semiconductor structure provided in one embodiment of the present application.

[0040] Explanation of the reference numerals: 100 - first wafer; 110 - metal interconnect layer; 111 - bonding layer; 112 - interlayer dielectric structure; 112a - first dielectric layer; 112b - dielectric barrier layer; 112c - second dielectric layer; 113 - groove; 114 - through hole; 120 - dielectric layer; 130 - barrier layer; 200 - second wafer; 210 - metal wiring layer; X1 - middle area; X2 - edge area; A - void. DETAILED DESCRIPTION

[0041] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0043] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0044] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0045] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] Figure 1 This is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application. Figure 1 , the present application provides a method for manufacturing a semiconductor structure, including steps S01 to S05.

[0047] Step S01, providing a first wafer, the first wafer including a central region and an edge region, the edge region being located around the central region, a metal interconnection layer being formed on the surface of the first wafer, and a portion of the metal interconnection layer located in the edge region having a cavity.

[0048] See Figure 2 In one embodiment, the void A is usually formed during the preparation process of the metal interconnection layer 110 (for example, during the edge cleaning process of the metal interconnection layer 110), and the presence of the void A in the metal interconnection layer 110 will greatly increase the risk of edge cracking in subsequent processes, thereby affecting the yield of the first wafer 100.

[0049] Step S02 , forming a dielectric layer on the metal interconnect layer, wherein the dielectric layer at least fills the voids.

[0050] See Figure 3In one embodiment, by filling the void A with the dielectric layer 120, the quality of the first wafer 100 and each film layer on its surface (including the metal interconnection layer 110 and the dielectric layer 120) can be effectively improved, thereby reducing or avoiding the risk of defects or crystal edge cracking in subsequent planarization and bonding processes.

[0051] In one embodiment, the material of the dielectric layer 120 is an insulating dielectric material. For example, the material of the dielectric layer 120 includes silicon oxide or other oxide materials.

[0052] Step S03 : forming a barrier layer on the dielectric layer, wherein the barrier layer extends to cover the surface and sidewalls of the metal interconnection layer.

[0053] See Figure 4 In one embodiment, the barrier layer 130 comprises nitride-doped silicon carbide (NDC). It should be noted that the barrier layer 130 can reduce or prevent metal diffusion from occurring on the surface of the metal interconnect layer and at the crystal edge (i.e., the portion of the edge region X2 away from the central region X1).

[0054] Step S04 : performing a planarization process to expose the surface of the metal interconnection layer.

[0055] See Figure 5 In one embodiment, portions of dielectric layer 120 and barrier layer 130 located on the surface of metal interconnect layer 110 are removed during the planarization process, thereby exposing the surface of metal interconnect layer 110 for subsequent hybrid bonding. Optionally, a chemical mechanical polishing (CMP) process is used for planarization.

[0056] It should be noted that the planarization process in step S04 removes the dielectric layer 120 and barrier layer 130 located on the upper surface of the metal interconnect layer 110, leaving the remaining dielectric layer 120 and barrier layer 130 flush with the surface of the metal interconnect layer 110. At this point, the remaining dielectric layer 120 and barrier layer 130 are both located at the edge of the first wafer 100 (i.e., the portion of the edge region X2 away from the central region X1). This protects the side edges of the metal interconnect layer 110 (i.e., the portion of the metal interconnect layer 110 near the edge of the first wafer 100) during the subsequent bonding process, thereby improving product yield.

[0057] At the same time, it needs to be further explained that, after the planarization treatment is performed to expose the surface of the metal interconnection layer, the hybrid bonding process performed in the next step will connect the exposed surface of the metal interconnection layer with the metal wiring layer on another wafer. Therefore, the risk of metal diffusion and contamination on the exposed surface of the metal interconnection layer at this time is very small and can be ignored.

[0058] Step S05: performing a hybrid bonding (HB) process on the first wafer.

[0059] The manufacturing method of the above-mentioned semiconductor structure reduces or avoids the risk of crystal edge cracking in subsequent processes by forming a dielectric layer that fills the voids; reduces or avoids the risk of metal diffusion in the metal interconnection layer by forming a barrier layer covering the surface and sidewalls of the metal interconnection layer, and at the same time reduces or avoids the risk of edge collapse or crystal edge cracking of the first wafer, thereby helping to improve the yield of the wafer.

[0060] Continue reading Figure 2 In one embodiment, the metal interconnect layer 110 includes an interlayer dielectric structure 112 and a trench 113 and a through-hole 114 formed in the interlayer dielectric structure 112. The trench 113 and the through-hole 114 are electroplated with a metal material to ensure the normal function of the metal interconnect layer 110. Optionally, the material of the metal interconnect layer 110 includes copper (Cu).

[0061] See Figure 2 In one embodiment, the formation process of the interlayer dielectric structure 112 includes: forming a first dielectric layer 112a on the first wafer 100; performing a planarization process on the first dielectric layer 112a to remove at most a portion of the first dielectric layer 112a to improve the thickness uniformity and surface flatness of the first dielectric layer 112a; forming a dielectric barrier layer 112b on the first dielectric layer 112a; and forming a second dielectric layer 112c on the dielectric barrier layer 112b to form the interlayer dielectric structure 112 including the first dielectric layer 112a, the dielectric barrier layer 112b, and the second dielectric layer 112c.

[0062] In one embodiment, during the planarization process of the first dielectric layer, the thickness of the first dielectric layer reduced is logarithmically related to the total thickness of the first dielectric layer. Optionally, the relationship between the total thickness D of the first dielectric layer and the thickness d of the first dielectric layer reduced is: Optionally, the total thickness of the first dielectric layer before planarization is in the range of 20 kÅ to 30 kÅ, the thickness of the first dielectric layer after thinning is in the range of 5 kÅ to 20 kÅ, and the remaining thickness of the first dielectric layer after planarization is greater than zero and less than or equal to 3 kÅ. Optionally, the thickness of the dielectric barrier layer is 1 kÅ, and the thickness of the second dielectric layer is 2.1 kÅ.

[0063] It should be noted that, during the above-mentioned planarization process of the first dielectric layer, by controlling the thickness of the portion of the first dielectric layer removed during the planarization process, the impact of excessive thickness removed during the planarization process on subsequent photolithography and etching processes can be reduced or avoided. The problem of metal residue that may occur in subsequent process steps can also be reduced or avoided, thereby reducing the probability of abnormal crystal edge bonding.

[0064] In one embodiment, the material of the first dielectric layer is tetraethyl orthosilicate (TEOS), the material of the dielectric barrier layer is carbon-doped silicon nitride, and the material of the second dielectric layer is silicon oxide. In other embodiments of the present application, the specific structure of the interlayer dielectric structure and the material selection of the different film layers can be adjusted according to actual needs, as long as the interlayer dielectric structure meets the insulation performance and other process requirements of the semiconductor structure. This application does not impose any restrictions on this.

[0065] It should be noted that in the process of forming the above-mentioned interlayer dielectric structure, after forming the first dielectric layer, the first dielectric layer needs to be etched to form trenches and through-holes in the first dielectric layer, and the trenches and through-holes are then filled with metal material through a metal electroplating process. Similarly, after forming the second dielectric layer, the second dielectric layer and the dielectric barrier layer also need to be etched to form trenches and through-holes in the second dielectric layer and the dielectric barrier layer, and the trenches and through-holes are then filled with metal material through a metal electroplating process, thereby forming the interlayer dielectric structure and the metal interconnect layer.

[0066] Continue reading Figure 2 In one embodiment, before forming the dielectric layer 120 on the metal interconnect layer 110, the semiconductor structure manufacturing method further includes: removing a portion of the metal interconnect layer 110 in the edge region X2 away from the central region X1; forming a bonding layer 111 on the metal interconnect layer 110; and removing a portion of the bonding layer 111 in the edge region X2 away from the central region X1. This removes the portion of the metal interconnect layer 110 in the edge region X2 away from the central region X1 to ensure smooth subsequent processes and reduce or avoid the formation of bubbles and defects in subsequent bonding processes. In a radial direction of the first wafer 100, the width D1 of the removed portion of the metal interconnect layer 110 is greater than the width D2 of the removed portion of the bonding layer 111. For example, the width D1 of the removed portion of the metal interconnect layer 110 is, for example, 3.2 mm, and the width D2 of the removed portion of the bonding layer 111 is, for example, 2.4 mm.

[0067] In one embodiment, electroplating edge cleaning (ECP EBR) can be used to remove a portion of the metal interconnect layer 110 in the edge region X2 away from the central region X1. It should be noted that if voids A are generated in the removed portion of the metal interconnect layer 110 during the edge cleaning process, the voids A will be filled with a dielectric layer in subsequent process steps, thereby reducing or even preventing the adverse effects of the voids A on subsequent process steps.

[0068] Continue reading Figure 2 In one embodiment, after forming the first dielectric layer 112a filled with a metal material, the method for manufacturing the semiconductor structure further includes: performing metal electroplating and edge cleaning on the first dielectric layer 112a to remove a portion of the first dielectric layer 112a in the edge region X2 that is away from the central region X1. Accordingly, after forming the second dielectric layer 112c filled with a metal material, the method for manufacturing the semiconductor structure further includes: performing metal electroplating and edge cleaning on the second dielectric layer 112c to remove a portion of the second dielectric layer 112c in the edge region X2 that is away from the central region X1, so that the sidewalls of the second dielectric layer 112c are flush with the sidewalls of the first dielectric layer 112a.

[0069] In one embodiment, after forming the interlayer dielectric structure and the metal interconnect layer, the method for manufacturing the semiconductor structure further includes: performing a trimming process on the first wafer to remove defects or structural anomalies at the edge of the first wafer.

[0070] See Figure 3 In one embodiment, the thickness of dielectric layer 120 ranges from 1 kÅ to 5 kÅ to ensure that voids A in metal interconnect layer 110 are completely filled. Optionally, dielectric layer 120 is formed using a high-density plasma chemical vapor deposition (HDPCVD) process. In other embodiments of the present application, the thickness of dielectric layer 120 and the selection of the preparation process can be adjusted based on the size of voids A in the semiconductor structure during actual manufacturing and other process requirements. It is sufficient to ensure that dielectric layer 120 completely fills voids A, and this application does not impose any restrictions on this.

[0071] See Figure 4 In one embodiment, the thickness of barrier layer 130 ranges from 0.5 kÅ to 2 kÅ to ensure that barrier layer 130 effectively prevents metal diffusion. Furthermore, barrier layer 130 formed on the sidewalls of dielectric layer 120 can also enhance the strength of the portion of metal interconnect layer 110 away from central region X1, reducing or preventing the risk of edge cracking during subsequent fabrication processes.

[0072] In one embodiment, after performing a planarization process to expose the surface of the metal interconnection layer and before performing a hybrid bonding process on the first wafer, the method for manufacturing a semiconductor structure further includes: performing a planarization process on the metal interconnection layer to further improve the surface flatness of the metal interconnection layer so as to perform a subsequent hybrid bonding process and improve the bonding effect.

[0073] See Figure 6 In one embodiment, a hybrid bonding process includes: providing a second wafer 200, wherein a metal wiring layer 210 is formed on the front surface of the second wafer 200; bonding the front surface of the first wafer 100 and the front surface of the second wafer 200 so that the projection of the metal interconnection layer 110 along a direction perpendicular to the surface of the second wafer 200 (i.e., the Y direction) coincides with the projection of the metal wiring layer 210 along a direction perpendicular to the surface of the second wafer 200, thereby connecting the metal wiring layer 210 and the metal interconnection layer 110; and performing an annealing process to enhance the hybrid bonding effect.

[0074] The first wafer 100 and the second wafer 200 are respectively one of a logic wafer and a pixel wafer, and the first wafer 100 and the second wafer 200 are of different types. That is, the first wafer 100 is a logic wafer and the second wafer 200 is a pixel wafer, or the first wafer 100 is a pixel wafer and the second wafer 200 is a logic wafer.

[0075] In one embodiment, after hybrid bonding, the semiconductor structure manufacturing method further includes: performing defect detection on the semiconductor structure obtained after hybrid bonding to improve product yield. Optionally, the defect detection includes inspecting the semiconductor structure after hybrid bonding for the presence of bond bubbles.

[0076] Accordingly, continue to refer to Figure 6 The present application also provides a semiconductor structure manufactured using the semiconductor structure manufacturing method described above. The semiconductor structure manufactured using the semiconductor structure manufacturing method provided in the present application maintains product yield while achieving interconnection between the metal interconnect layer of the first wafer and the metal wiring layer of the second wafer, and reduces or avoids problems such as poor edge bonding during the manufacturing process and edge cracking in subsequent manufacturing processes.

[0077] The unexpected effects of the present application are: by forming a dielectric layer that fills the voids, the risk of crystal edge cracking in subsequent processes is reduced or avoided; by forming a barrier layer covering the surface and sidewalls of the metal interconnection layer, the risk of metal diffusion in the metal interconnection layer is reduced or avoided, and at the same time, the risk of edge collapse or crystal edge cracking of the first wafer is reduced or avoided, thereby helping to improve the yield of the wafer.

[0078] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0079] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a first wafer, the first wafer comprising a central region and an edge region, the edge region being located around the central region, a metal interconnection layer being formed on a surface of the first wafer, and a portion of the metal interconnection layer located within the edge region having a cavity; forming a dielectric layer on the metal interconnection layer, wherein the dielectric layer at least fills the void; forming a barrier layer on the dielectric layer, wherein the barrier layer extends to cover the surface and sidewalls of the metal interconnection layer; performing a planarization process to expose the surface of the metal interconnection layer; performing a hybrid bonding process on the first wafer; The metal interconnect layer includes an interlayer dielectric structure formed on the first wafer and trenches and through holes formed in the interlayer dielectric structure, wherein metal material is electroplated in the trenches and the through holes; The formation process of the interlayer dielectric structure includes: forming a first dielectric layer on the first wafer; The first dielectric layer is planarized to remove at most a portion of the first dielectric layer, and the thickness of the first dielectric layer reduced is in a logarithmic relationship with the total thickness of the first dielectric layer. The relationship between the total thickness D of the first dielectric layer and the thickness d of the first dielectric layer reduced is D=log 10 d; forming a dielectric barrier layer on the first dielectric layer; A second dielectric layer is formed on the dielectric barrier layer to form the interlayer dielectric structure including the first dielectric layer, the dielectric barrier layer and the second dielectric layer.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The steps before forming the dielectric layer on the metal interconnect layer also include: removing a portion of the metal interconnection layer in the edge region away from the central region; forming a bonding layer on the metal interconnection layer; A portion of the bonding layer in the edge region away from the central region is removed.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: In a radial direction of the first wafer, the width of the removed portion of the metal interconnection layer is greater than the width of the removed portion of the bonding layer.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: During the planarization process of the first dielectric layer, the first dielectric layer is thinned to a thickness ranging from 5 kÅ to 20 kÅ, and the remaining thickness of the first dielectric layer after the planarization process is greater than zero and less than or equal to 3 kÅ.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The hybrid bonding process includes: Providing a second wafer, wherein a metal wiring layer is formed on a front surface of the second wafer; bonding the front surface of the first wafer and the front surface of the second wafer so that a projection of the metal interconnection layer in a direction perpendicular to the surface of the second wafer overlaps with a projection of the metal wiring layer in a direction perpendicular to the surface of the second wafer, thereby connecting the metal wiring layer and the metal interconnection layer; performing an annealing process; The first wafer and the second wafer are respectively one of a logic wafer and a pixel wafer, and the first wafer and the second wafer are of different types.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: After completing the hybrid bonding process, the method for manufacturing the semiconductor structure further includes: Perform defect detection on the semiconductor structure obtained after hybrid bonding.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: The thickness of the dielectric layer ranges from 1 kÅ to 5 kÅ, and the thickness of the barrier layer ranges from 0.5 kÅ to 2 kÅ.

8. A semiconductor structure, characterized in that The semiconductor structure is manufactured using the method for manufacturing the semiconductor structure according to any one of claims 1 to 7.

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