Control method and device of two-phase interleaving power factor correction circuit, equipment, storage medium and product

Abstract

The invention discloses a control method and device of a two-phase interleaving power factor correction circuit, equipment, a storage medium and a product, and relates to the field of control of a multi-phase interleaving PFC circuit, and the method is applied to at least two-phase interleaving power factor correction circuits. The method comprises the steps of obtaining an output voltage, an input voltage and a feedforward adjustment coefficient of the two-phase interleaving power factor correction circuit and a sampling current and a power distribution proportion of each channel; determining an adjustment coefficient of each channel in the two-phase interlaced power factor correction circuit according to the power distribution proportion; and according to the output voltage, the input voltage, the sampling current, the adjustment coefficient and the feedforward adjustment coefficient, determining the PWM duty ratio of each channel in the two-phase interleaving power factor correction circuit, so that the output power of each channel in the two-phase interleaving power factor correction circuit is consistent. Therefore, the technical problem that the two-phase load of a traditional two-phase PFC circuit is affected by hardware, and the two-phase load power is difficult to be distributed in a balanced mode or distributed according to needs is solved.

Description

Technical Field

[0001] This application relates to the technical field of control of multi-phase interleaved PFC circuits, and particularly to a control method, device, equipment, storage medium and product for a two-phase interleaved power factor correction circuit. Background Art

[0002] The multi-phase interleaved power factor correction (PFC) circuit is a technology used to improve the power factor of power electronic devices, reduce harmonic distortion, and enhance system efficiency. By operating multiple single-phase PFC circuits in parallel in a phase-interleaved manner, the multi-phase interleaved PFC circuit can effectively reduce the input current ripple, lower electromagnetic interference (EMI), and improve the overall performance and reliability of the system. The phase interleaving technique staggers the output current phases of multiple single-phase PFC circuits by a certain angle (usually 360° / n, where n is the number of phases), so that when the phase currents are superimposed, some of the ripples cancel each other out, thereby reducing the ripple amplitude of the total input current, decreasing the size of the filter inductance and capacitance, and increasing the power density.

[0003] The advantages of the multi-phase interleaved PFC circuit include: reducing the input current ripple. The reduction of the ripple current reduces the requirements for the filter inductance and capacitance, and decreases the component volume and cost. Improving the electromagnetic compatibility (EMC) performance of the system. Improving the power factor. Through a smoother input current waveform, the power factor of the system is improved, approaching 1. Enhancing the system efficiency. Each phase shares the load, reducing the current stress of each phase and the switching losses. Improving the overall efficiency of the system. Enhancing the system reliability. The multi-phase redundant design improves the fault tolerance of the system. Reducing the impact of a single component failure on the system. Increasing the power density. Reducing the size of the filter components, making the system more compact.

[0004] However, due to hardware limitations, it is difficult to evenly distribute or allocate the load power of the two phases in a traditional two-phase PFC circuit as needed. Summary of the Invention

[0005] The main objective of this application is to provide a control method, device, equipment, storage medium and product for a two-phase interleaved power factor correction circuit, aiming to solve the technical problem that due to hardware limitations, it is difficult to evenly distribute or allocate the load power of the two phases in a traditional two-phase PFC circuit as needed.

[0006] To achieve the above objective, this application proposes a control method for a two-phase interleaved power factor correction circuit, and the control method for the two-phase interleaved power factor correction circuit is applied to the two-phase interleaved power factor correction circuit; The control method for the two-phase interleaved power factor correction circuit includes: Obtain the output voltage, input voltage, and feedforward regulation coefficient of the two-phase interleaved power factor correction circuit, as well as the sampled current and power distribution ratio of each channel. Determine the regulation coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power distribution ratio. Determine the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampled current, regulation coefficient, and feedforward regulation coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent.

[0007] Optionally, the step of determining the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampled current, regulation coefficient, and feedforward regulation coefficient specifically includes: Obtain the voltage reference value of each channel in the two-phase interleaved power factor correction circuit. Determine the current reference value and the output PWM duty cycle compensation amount of each channel in the two-phase interleaved power factor correction circuit according to the regulation coefficient, input voltage, and output voltage. Determine the sampled current difference of each channel in the two-phase interleaved power factor correction circuit and the output of the current error compensation module in the two-phase interleaved power factor correction circuit according to the current reference value and the sampled current. Determine the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the sampled current difference, the output of the current error compensation module, the feedforward regulation coefficient, and the output PWM duty cycle compensation amount.

[0008] Optionally, the step of determining the current reference value and the output PWM duty cycle compensation amount of each channel in the two-phase interleaved power factor correction circuit according to the regulation coefficient, input voltage, and output voltage specifically includes: Determine the output voltage difference and the output of the voltage error compensation module in the two-phase interleaved power factor correction circuit according to the output voltage and the voltage reference value. Determine the average value of the input voltage according to the input voltage. Determine the current reference value according to the output voltage difference, the input voltage, the average value of the input voltage, and the regulation coefficient. Determine the PWM duty cycle compensation amounts of the two modes of the voltage feedforward compensation module in the two-phase interleaved power factor correction circuit according to the input voltage, the output voltage, the output of the voltage error compensation module, and the feedforward regulation coefficient. Select the minimum value of the PWM duty cycle compensation amounts as the output PWM duty cycle compensation amount.

[0009] Optionally, before the step of obtaining the output voltage, input voltage, and feedforward regulation coefficient of the two-phase interleaved power factor correction circuit, as well as the sampled current and power distribution ratio of each channel, the method further includes: Obtaining a correction regulation coefficient and the inductor current of each channel in the two-phase interleaved power factor correction circuit; Determining the corrected sampled current of each channel in the two-phase interleaved power factor correction circuit according to the inductor current and the correction regulation coefficient.

[0010] Optionally, after the step of determining the regulation coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power distribution ratio, the method further includes: Obtaining the actual feedback current of each channel in the two-phase interleaved power factor correction circuit; Adjusting the output power of each channel of the two-phase interleaved power factor correction circuit according to the feedback current through the regulation coefficient, so that the actual output power of each channel meets the preset load requirements.

[0011] In addition, to achieve the above object, the present application also proposes a control device for a two-phase interleaved power factor correction circuit, the device includes: An acquisition module, configured to acquire the output voltage, input voltage, and feedforward regulation coefficient of the two-phase interleaved power factor correction circuit, as well as the sampled current and power distribution ratio of each channel; An adjustment module, configured to determine the regulation coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power distribution ratio; A power module, configured to determine the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampled current, regulation coefficient, and feedforward regulation coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent.

[0012] In addition, to achieve the above object, the present application also proposes a control device for a two-phase interleaved power factor correction circuit, the device includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program is configured to implement the steps of the control method for the two-phase interleaved power factor correction circuit.

[0013] In addition, to achieve the above object, the present application also proposes a storage medium, the storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium, and when the computer program is executed by a processor, it implements the steps of the control method for the two-phase interleaved power factor correction circuit.

[0014] In addition, to achieve the above object, the present application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the control method for the two-phase interleaved power factor correction circuit.

[0015] One or more technical solutions proposed by the present application have at least the following effects: The present application discloses a control method, device, equipment, storage medium and product for a two-phase interleaved power factor correction circuit. The method is applied to at least a two-phase interleaved power factor correction circuit. The method includes: obtaining the output voltage, input voltage and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit, as well as the sampled current and power distribution ratio of each channel; determining the adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power distribution ratio; determining the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampled current, adjustment coefficient and feedforward adjustment coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent. Thus, it solves the technical problem that the two-phase loads of the traditional two-phase PFC circuit are affected by hardware, and it is difficult to achieve balanced distribution or on-demand distribution of the two-phase load power, ensuring the flexibility and consistency of the output of the two-phase interleaved power factor correction circuit. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 is the two-phase interleaved power factor correction circuit of the present application; Figure 2 is the topological structure diagram of the control method for the two-phase interleaved power factor correction circuit of the present application; Figure 3 is the schematic flowchart of the first embodiment of the control method for the two-phase interleaved power factor correction circuit proposed in the embodiment of the present application; Figure 4 is the schematic flowchart of the second embodiment of the control method for the two-phase interleaved power factor correction circuit proposed in the embodiment of the present application; Figure 5 is the block diagram of the current feedforward compensation module of the present application; Figure 6 is the block diagram of the current sampling correction module of the present application; Figure 7Schematic flowchart of the third embodiment of the control method for a two-phase interleaved power factor correction circuit proposed in an embodiment of the present application; Figure 8 Schematic block diagram of the control device for a two-phase interleaved power factor correction circuit in an embodiment of the present application; Figure 9 Schematic diagram of the device structure of the hardware operating environment involved in the control method for a two-phase interleaved power factor correction circuit in an embodiment of the present application.

[0018] Explanation of the reference numerals in the drawings:

[0019] The realization of the purpose, functional features and advantages of the present application will be further described in conjunction with the embodiments with reference to the accompanying drawings. Detailed implementation manners

[0020] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0021] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0022] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present application are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0023] In addition, the descriptions involving "first", "second", etc. in the present application are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present application.

[0024] The main solution of the embodiment of the present application is: introduce a regulation coefficient K Mx and a feedforward regulation coefficient in the voltage feedforward link of the two-phase interleaved PFC circuit. By adjusting the voltage feedforward gain K Mx and the feedforward regulation coefficient of the corresponding channel according to the actual circuit parameters, the load power can be more evenly distributed. If the load powers of the two-phase inductors need to be unevenly distributed during actual use, the two-way K Mx and the feedforward regulation coefficient can also be flexibly adjusted.

[0025] In the embodiment, for the convenience of description, the controller of the two-phase interleaved PFC circuit is used as the execution subject for elaboration below.

[0026] The present application provides a solution. The present application discloses a control method, device, equipment, storage medium and product for a two-phase interleaved power factor correction circuit. The method is applied to at least a two-phase interleaved power factor correction circuit. The method includes: obtaining the output voltage, input voltage and feedforward regulation coefficient of the two-phase interleaved power factor correction circuit, as well as the sampled current and power distribution ratio of each channel; determining the regulation coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power distribution ratio; determining the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampled current, regulation coefficient and feedforward regulation coefficient, so that the output powers of each channel in the two-phase interleaved power factor correction circuit are consistent. Thus, the technical problem that the two-phase loads of the traditional two-phase PFC circuit are affected by hardware and it is difficult to evenly distribute or distribute on demand the load powers of the two phases is solved, ensuring the flexibility and consistency of the output of the two-phase interleaved power factor correction circuit.

[0027] It should be noted that as Figure 1 shown, Figure 1 is the two-phase interleaved power factor correction circuit of the present application. The two-phase interleaved power factor correction circuit includes: two-phase parallel inductors (L1 and L2) coupled between the rectifier bridge and the output terminal; two switches respectively coupled to the two inductors; a voltage dividing circuit composed of resistor R13 and resistor R14, which divides the input voltage UAC and sends it into the input voltage sampling channel; a voltage dividing circuit composed of resistor R15 and resistor R16, which divides the output voltage UDC and sends it into the output voltage sampling channel; the voltage division of resistor R1 is sent into operational amplifier 3 through resistors R2 and R3, and after amplification, it is sent into the sampling channel of inductor current IAC1; the voltage division of resistor R7 is sent into operational amplifier 5 through resistors R8 and R9, and after amplification, it is sent into the sampling channel of inductor current IAC2. After the controller collects these feedback signals, it calculates the PWM duty cycle for controlling the two switches and sends out two PWM waves.

[0028] It can be understood that as Figure 2 shown, Figure 2This is the topological structure diagram of the control method for the two-phase interleaved power factor correction circuit of the present application. The topological structure diagram of the control method for the two-phase interleaved power factor correction circuit includes: a voltage error compensation module, a voltage feedforward compensation module, two current error compensation modules, a current feedforward compensation module, a current sampling and correction module, and two PWM (1, 2) output modules.

[0029] Based on this, an embodiment of the present application provides a control method for a two-phase interleaved power factor correction circuit.

[0030] Reference Figure 3 , Figure 3 This is the schematic flowchart of the first embodiment of the control method for the two-phase interleaved power factor correction circuit proposed in the embodiment of the present application.

[0031] Considering that the two-phase loads of the traditional two-phase PFC circuit are affected by hardware, it is very difficult to evenly distribute or allocate the load power of the two phases as required. Therefore, in order to ensure the flexibility and consistency of the output of the two-phase interleaved power factor correction circuit. As Figure 1 shown, the control method of the two-phase interleaved power factor correction circuit described in this embodiment is applied to at least a two-phase interleaved power factor correction circuit; The control method of the two-phase interleaved power factor correction circuit includes steps S10 to S30: Step S10: Obtain the output voltage, input voltage, and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit, as well as the sampled current and power distribution ratio of each channel.

[0032] It should be noted that the output voltage is UDC, and the input voltage is UAC. The power distribution ratio is set according to the required power of the load.

[0033] Step S20: Determine the adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power distribution ratio.

[0034] It should be noted that the adjustment coefficient KMx (x = 1 for channel 1) is introduced in the voltage feedforward link (voltage feedforward compensation module). In the actual hardware circuit, the feedback signals and output responses of the two-phase channels may be different due to component parameters and other issues, which may cause different load powers of the two channels. At this time, the voltage feedforward gain KMx of the corresponding channel can be adjusted according to the actual circuit parameters to make the load power distribution more balanced. If the load powers of the two-phase inductors need to be unevenly distributed during actual use, the two-way KMx can also be adjusted flexibly.

[0035] It can be understood that, as Figure 5 shown, Figure 5This is the block diagram of the current feedforward compensation module of the present application. In the calculation of the compensation amount in the DCCM mode (continuous mode) of the current feedforward link (current feedforward compensation module), the (feedforward) adjustment coefficient PFC_DCCMCSO and mode selection are introduced. In the translation mode (the status flag bit DDCM_SEL is 0), the calculated compensation amount of DCCM is directly added to PFC_DCCMCSO to obtain the final PWM duty cycle compensation amount PFC_COM of DCCM; in the scaling mode (the status flag bit DDCM_SEL is 1), the calculated compensation amount of DCCM is multiplied by PFC_DCCMCSO to obtain the final PWM duty cycle compensation amount PFC_COM of DCCM. In the calculation of the compensation amount in the DDCM mode (discontinuous mode) of the current feedforward link, the (feedforward) adjustment coefficient PFC_KCOM and adjustment mode selection are introduced.

[0036] Step S30: Determine the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampled current, adjustment coefficient, and feedforward adjustment coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent.

[0037] It should be noted that as Figure 2 shown, the output voltage difference is determined according to the output voltage of the two-phase interleaved PFC circuit and the voltage reference value UDC_REF. The voltage reference value UDC_REF is the DC voltage reference value set by the user. The output voltage difference is sent to the PI controller to generate the control output UDC_UK (the output of the voltage error compensation module). The voltage feedforward compensation module continuously samples the input voltage UAC, obtains the average value UAVG of the input voltage UAC, and calculates two reference values of inductor current. The current error compensation module is the inner loop of the two-phase interleaved PFC control. Its input is the difference between the output current reference value IACx_REF of the voltage feedforward compensation module and the actual inductor current IACx sampled by the ADC. This difference is sent to the PI controller to generate the control output sampled current difference IACx_UK (the output of the current error compensation module). The current feedforward compensation module first calculates the PWM duty cycle compensation amount in the continuous mode DCCM according to the sampled values of the input voltage UAC and the output voltage UDC, and then calculates the PWM duty cycle compensation amount in the discontinuous mode DDCM. The smaller one is taken as the final output PWM duty cycle compensation amount PFC_COM of the current feedforward module. The PWM output module uses the sum of the output IACx_UK of the current error compensation module and the PWM duty cycle compensation amount PFC_COM as the comparison value to output the final PWM wave, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent.

[0038] In a specific implementation, the output voltage, input voltage, and feedforward regulation coefficient of the two-phase interleaved power factor correction circuit, as well as the sampled current and power distribution ratio of each channel, are obtained; according to the power distribution ratio, the regulation coefficient of each channel in the two-phase interleaved power factor correction circuit is determined; according to the output voltage, input voltage, sampled current, regulation coefficient, and feedforward regulation coefficient, the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit is determined, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent, thereby solving the technical problem that the two-phase loads of the traditional two-phase PFC circuit are affected by hardware, and it is difficult to achieve balanced distribution or on-demand distribution of the two-phase load powers, ensuring the flexibility and consistency of the output of the two-phase interleaved power factor correction circuit.

[0039] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar content as that in the above first embodiment can be referred to the above introduction and will not be repeated hereinafter. On this basis, please refer to Figure 4 , Figure 4 which is a schematic flowchart of the second embodiment of the control method for the two-phase interleaved power factor correction circuit proposed in the embodiment of the present application.

[0040] Considering the limitations of factors such as the error of the actual sampling circuit and the calculation accuracy, there will be a certain error in the calculation of the actual DCCM and DDCM mode compensation amounts. As Figure 4 shown, step S30 in this embodiment specifically includes steps S31 to S34: Step S31: Obtain the voltage reference values of each channel in the two-phase interleaved power factor correction circuit.

[0041] It should be noted that the voltage reference value UDC_REF is the DC voltage reference value set by the user, and the sampled current is IACx (x = 1 for channel 1).

[0042] Step S32: According to the regulation coefficient, input voltage, and output voltage, determine the current reference value and the output PWM duty cycle compensation amount of each channel in the two-phase interleaved power factor correction circuit.

[0043] It should be noted that the current reference value is IACx_REF, and the output PWM duty cycle compensation amount is PFC_COM.

[0044] Step S33: According to the current reference value and the sampled current, determine the sampled current difference of each channel in the two-phase interleaved power factor correction circuit and the output of the current error compensation module in the two-phase interleaved power factor correction circuit.

[0045] It should be noted that the current error compensation module is the inner loop of the two-phase interleaved PFC control. Its input is the difference between the output current reference value IACx_REF of the voltage feedforward compensation module and the actual inductor current IACx sampled by the ADC. This difference is sent to the PI controller to generate the control output IACx_UK (the output of the current error compensation module).

[0046] Step S34: Determine the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the sampled current difference, the output of the current error compensation module, the feedforward adjustment coefficient, and the output PWM duty cycle compensation amount.

[0047] In specific implementation, obtain the voltage reference value of each channel in the two-phase interleaved power factor correction circuit; determine the current reference value and the output PWM duty cycle compensation amount of each channel in the two-phase interleaved power factor correction circuit according to the adjustment coefficient, the input voltage, and the output voltage; determine the sampled current difference of each channel in the two-phase interleaved power factor correction circuit and the output of the current error compensation module in the two-phase interleaved power factor correction circuit according to the current reference value and the sampled current; determine the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the sampled current difference, the output of the current error compensation module, and the output PWM duty cycle compensation amount, thereby reducing the difficulty of tuning the PI controller parameters of the current inner loop in the two-phase interleaved PFC circuit control.

[0048] Further, step S32 specifically includes:[[]] Determine the output voltage difference and the output of the voltage error compensation module in the two-phase interleaved power factor correction circuit according to the output voltage and the voltage reference value; Determine the average value of the input voltage according to the input voltage; Determine the current reference value according to the output voltage difference, the input voltage, the average value of the input voltage, and the adjustment coefficient; Determine the PWM duty cycle compensation amounts of the two modes of the voltage feedforward compensation module in the two-phase interleaved power factor correction circuit according to the input voltage, the output voltage, the output of the voltage error compensation module, and the feedforward adjustment coefficient; Select the minimum value of the PWM duty cycle compensation amounts as the output PWM duty cycle compensation amount.

[0049] It should be noted that, such as Figure 2As shown, the two modes include: discontinuous mode DDCM and continuous mode DCCM. The output voltage difference is determined based on the output voltage of the two-phase interleaved PFC circuit and the voltage reference value UDC_REF. The voltage reference value UDC_REF is the DC voltage reference value set by the user. The output voltage difference is sent to the PI controller to generate the control output UDC_UK (the output of the voltage error compensation module). The voltage feedforward compensation module continuously samples the input voltage UAC to obtain the average value UAVG of the input voltage UAC, and through calculation to the reference values of the inductor currents of the two paths. As Figure 5 shown, Figure 5 is the block diagram of the current feedforward compensation module of this application. The current feedforward compensation module first calculates the PWM duty cycle compensation amount in the continuous mode DCCM based on the sampled values of the input voltage UAC and the output voltage UDC, and then calculates the PWM duty cycle compensation amount in the discontinuous mode DDCM, and takes the smaller one as the final output PWM duty cycle compensation amount PFC_COM of the current feedforward module. Due to problems such as electromagnetic interference and voltage offset of the system during operation, the sampling of the feedback circuit will have errors, which will in turn affect the calculation of the current feedforward compensation amount. In the calculation of the DCCM mode compensation amount in the current feedforward link (current feedforward compensation module), the (feedforward) adjustment coefficient PFC_DCCMCSO and the mode selection are introduced. In the translation mode (the status flag bit DDCM_SEL is 0), the calculated DCCM compensation amount is directly added to PFC_DCCMCSO to obtain the final PWM duty cycle compensation amount PFC_COM of DCCM; in the scaling mode (the status flag bit DDCM_SEL is 1), the calculated DCCM compensation amount is multiplied by PFC_DCCMCSO to obtain the final PWM duty cycle compensation amount PFC_COM of DCCM. In the calculation of the DDCM mode compensation amount in the current feedforward link, the (feedforward) adjustment coefficient PFC_KCOM and the adjustment mode selection are introduced.

[0050] In specific implementation, the feedforward adjustment coefficient is obtained; based on the output voltage and the voltage reference value, the output voltage difference and the output of the voltage error compensation module in the two-phase interleaved power factor correction circuit are determined; based on the input voltage, the average value of the input voltage is determined; based on the output voltage difference, the input voltage, the average value of the input voltage and the adjustment coefficient, the current reference value is determined; based on the input voltage, the output voltage, the output of the voltage error compensation module and the feedforward adjustment coefficient, the PWM duty cycle compensation amounts of the two modes of the voltage feedforward compensation module in the two-phase interleaved power factor correction circuit are determined; the minimum value of the PWM duty cycle compensation amounts is selected as the output PWM duty cycle compensation amount. Thereby, the difficulty of tuning the PI controller parameters of the current inner loop in the control of the two-phase interleaved PFC circuit is reduced.

[0051] Furthermore, considering that the inductor current is similar to a sawtooth wave during actual operation, the instantaneous inductor current at the sampling moment is used to describe the average inductor current of the sawtooth wave. Therefore, the sampling timing has a great impact. Moreover, in the discontinuous mode, there is a moment when the current is 0. When the instantaneous current sampled by the ADC is used to reflect the actual effective current, the sampled current will be too large. Before step S10, it also includes: Obtaining a correction adjustment coefficient and an inductor current of each channel in the two-phase interleaved power factor correction circuit; According to the inductor current and the correction adjustment coefficient, the corrected sampling current of each channel in the two-phase interleaved power factor correction circuit is determined.

[0052] It should be noted that if Figure 6 As shown, Figure 6 This is the block diagram of the current sampling correction module of this application. The current sampling correction module introduces the correction (adjustment) coefficient PFC_KIAC. In continuous mode, PFC_KIAC is used to linearly scale the sampling results; in discontinuous mode, the influence of duty cycle and input voltage and output voltage is introduced to correct the sampling results. COM_ST is the status flag of the inductor continuous / discontinuous mode, which is 1 in continuous mode and 0 in discontinuous mode.

[0053] In a specific implementation, a correction adjustment coefficient and the inductor current of each channel in the two-phase interleaved power factor correction circuit are obtained; based on the inductor current and the correction adjustment coefficient, the corrected sampling current of each channel in the two-phase interleaved power factor correction circuit is determined to ensure the accuracy of the sampling current.

[0054] Based on the second embodiment of the present application, in the third embodiment of the present application, the same or similar contents as those of the second embodiment can be referred to the above introduction, and will not be repeated in the following. Figure 7 , Figure 7 This is a flow chart of a third embodiment of a control method for a two-phase interleaved power factor correction circuit proposed in an embodiment of the present application.

[0055] Considering that in actual use, the load power of the two-phase inductor needs to be distributed unevenly, in order to flexibly adjust the two-way KMx, such as Figure 7 As shown, after step S20 in this embodiment, steps S201 to S202 are also included: Step S201: obtaining the actual feedback current of each channel in the two-phase interleaved power factor correction circuit; Step S202: According to the feedback current, the output power of each channel of the two-phase interleaved power factor correction circuit is adjusted by the adjustment coefficient so that the actual output power of each channel meets the preset load demand.

[0056] It should be noted that the preset load demand can obtain its rated power (W), current (A), or voltage (U) through the load nameplate or technical manual, or can be set according to actual needs. A current detection circuit is provided at the output end of the two-phase interleaved power factor correction (PFC) circuit, such as using common current detection components such as current transformers and shunt resistors to obtain the feedback current signal in real time.

[0057] In specific implementation, the load powers of the two-phase inductors need to be unevenly distributed, and the two-way KMx can be flexibly adjusted to meet the load power requirements.

[0058] In addition, to achieve the above object, as Figure 8 shown, the present application also proposes a control device for a two-phase interleaved power factor correction circuit, and the device includes: An acquisition module 10, configured to acquire the output voltage, input voltage, and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit, as well as the sampled current and power distribution ratio of each channel; An adjustment module 20, configured to determine the adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power distribution ratio; A power module 30, configured to determine the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampled current, adjustment coefficient, and feedforward adjustment coefficient, so that the output powers of each channel in the two-phase interleaved power factor correction circuit are consistent.

[0059] The control device for the two-phase interleaved power factor correction circuit provided by the present application adopts the control method of the two-phase interleaved power factor correction circuit in the above embodiment, and can solve the technical problem that the two-phase loads of the traditional two-phase PFC circuit are affected by hardware, and it is very difficult to evenly distribute or distribute the load powers of the two phases as required. Compared with the prior art, the beneficial effects of the control device for the two-phase interleaved power factor correction circuit provided by the present application are the same as those of the control method of the two-phase interleaved power factor correction circuit provided by the above embodiment, and other technical features in the control device for the two-phase interleaved power factor correction circuit are the same as the features disclosed in the above embodiment method, and will not be elaborated here.

[0060] In addition, to achieve the above object, the present application also proposes a control device for a two-phase interleaved power factor correction circuit, and the device includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, and the computer program is configured to implement the steps of the control method of the two-phase interleaved power factor correction circuit.

[0061] As Figure 9As shown, the control device of the two-phase interleaved power factor correction circuit may include a processing device 1001 (such as a central processing unit, a graphics processing unit, etc.), which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM: Random Access Memory) 1004. In the RAM 1004, various programs and data required for the operation of the control device of the two-phase interleaved power factor correction circuit are also stored. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems may be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 may allow the control device of the two-phase interleaved power factor correction circuit to communicate with other devices wirelessly or wiredly to exchange data. Although the figure shows the control device of the two-phase interleaved power factor correction circuit having various systems, it should be understood that it is not required to implement or have all the shown systems. Instead, more or fewer systems may be implemented or had.

[0062] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program codes for performing the methods shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network through the communication device, or installed from the storage device 1003, or installed from the ROM 1002. When the computer program is executed by the processing device 1001, the above functions defined in the methods of the embodiments disclosed in the present application are executed.

[0063] The control device of the two-phase interleaved power factor correction circuit provided by this application adopts the control method of the two-phase interleaved power factor correction circuit in the above-mentioned embodiment, which can solve the technical problem that the two-phase loads of the traditional two-phase PFC circuit are affected by hardware, and it is very difficult to achieve balanced distribution or on-demand distribution of the load power of the two phases. Compared with the prior art, the beneficial effects of the control device of the two-phase interleaved power factor correction circuit provided by this application are the same as those of the control method of the two-phase interleaved power factor correction circuit provided by the above-mentioned embodiment, and other technical features in the control device of the two-phase interleaved power factor correction circuit are the same as the features disclosed in the method of the previous embodiment, which will not be elaborated here.

[0064] It should be understood that each part disclosed in this application can be implemented by hardware, software, firmware or a combination of them. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0065] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application, and all should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

[0066] In addition, to achieve the above object, this application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the control method of the two-phase interleaved power factor correction circuit are realized.

[0067] The computer-readable storage medium provided by the present application can be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or components, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this embodiment, the computer-readable storage medium can be any tangible medium that contains or stores a program, which can be used by or in conjunction with an instruction execution system, device, or component. The program code contained on the computer-readable storage medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0068] The above computer-readable storage medium can be included in the control device of the two-phase interleaved power factor correction circuit; or can exist separately without being assembled into the control device of the two-phase interleaved power factor correction circuit.

[0069] The above computer-readable storage medium carries one or more programs. When the one or more programs are executed by the control device of the two-phase interleaved power factor correction circuit, the control device of the two-phase interleaved power factor correction circuit is caused to: obtain the output voltage and input voltage of each channel in the two-phase interleaved power factor correction circuit; determine the adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit according to the input voltage and output voltage; determine the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the adjustment coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent.

[0070] Computer program code for performing the operations of this application can be written in one or more programming languages or combinations thereof. The above-mentioned programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (for example, by using an Internet service provider to connect through the Internet).

[0071] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0072] The modules described in the embodiments of this application can be implemented in software or in hardware. Among them, the name of the module does not constitute a limitation to the unit itself in some cases.

[0073] The readable storage medium provided by this application is a computer-readable storage medium, and the computer-readable storage medium stores computer-readable program instructions (i.e., computer programs) for executing the control method of the above two-phase interleaved power factor correction circuit, which can solve the technical problem that the two-phase loads of the traditional two-phase PFC circuit are affected by hardware, and it is very difficult to evenly distribute or allocate the load power of the two phases as required. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by this application are the same as those of the control method of the two-phase interleaved power factor correction circuit provided in the above embodiments, and will not be elaborated here.

[0074] In addition, to achieve the above object, this application also proposes a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the steps of the control method of the above two-phase interleaved power factor correction circuit.

[0075] The above are only the preferred embodiments of this application, and do not limit the patent scope of this application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of this application, or directly or indirectly applied to other related technical fields, shall be equally included in the patent protection scope of this application.

Claims

1. A control method for a two-phase interleaved power factor correction circuit, characterized in that The control method of the two-phase interleaved power factor correction circuit is applied to at least a two-phase interleaved power factor correction circuit; The control method of the two-phase interleaved power factor correction circuit includes: Obtaining the output voltage, input voltage, and feed-forward regulation coefficient of the two-phase interleaved power factor correction circuit, as well as the sampled current and power distribution ratio of each channel; Determining the regulation coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power distribution ratio; Determining the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampled current, regulation coefficient, and feed-forward regulation coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent.

2. The control method of the two-phase interleaved power factor correction circuit according to claim 1, characterized in that The step of determining the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampled current, regulation coefficient, and feed-forward regulation coefficient specifically includes: Obtaining the voltage reference value of each channel in the two-phase interleaved power factor correction circuit; Determining the current reference value and the output PWM duty cycle compensation amount of each channel in the two-phase interleaved power factor correction circuit according to the regulation coefficient, input voltage, and output voltage; Determining the sampled current difference of each channel in the two-phase interleaved power factor correction circuit and the output of the current error compensation module in the two-phase interleaved power factor correction circuit according to the current reference value and the sampled current; Determining the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the sampled current difference, the output of the current error compensation module, the feed-forward regulation coefficient, and the output PWM duty cycle compensation amount.

3. The control method of the two-phase interleaved power factor correction circuit according to claim 2, characterized in that, The step of determining the current reference value and the output PWM duty cycle compensation amount of each channel in the two-phase interleaved power factor correction circuit according to the regulation coefficient, input voltage, and output voltage specifically includes: Determining the output voltage difference and the output of the voltage error compensation module in the two-phase interleaved power factor correction circuit according to the output voltage and the voltage reference value; Determining the average value of the input voltage according to the input voltage; Determining the current reference value according to the output voltage difference, the input voltage, the average value of the input voltage, and the regulation coefficient; Determining the PWM duty cycle compensation amounts of two modes of the voltage feed-forward compensation module in the two-phase interleaved power factor correction circuit according to the input voltage, the output voltage, the output of the voltage error compensation module, and the feed-forward regulation coefficient; Selecting the minimum value of the PWM duty cycle compensation amounts as the output PWM duty cycle compensation amount.

4. The control method of the two-phase interleaved power factor correction circuit according to claim 1, characterized in that, Before the step of obtaining the output voltage, input voltage, and feed-forward regulation coefficient of the two-phase interleaved power factor correction circuit, as well as the sampled current and power distribution ratio of each channel, it further includes: Obtaining the correction regulation coefficient and the inductor current of each channel in the two-phase interleaved power factor correction circuit; Determining the corrected sampled current of each channel in the two-phase interleaved power factor correction circuit according to the inductor current and the correction regulation coefficient.

5. The control method of the two-phase interleaved power factor correction circuit according to claim 1, characterized in that After the step of determining the regulation coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power distribution ratio, it further includes: Obtain the actual feedback current of each channel in the two-phase interleaved power factor correction circuit; According to the feedback current, adjust the output power of each channel of the two-phase interleaved power factor correction circuit through the adjustment coefficient, so that the actual output power of each channel meets the preset load requirements.

6. A control device for a two-phase interleaved power factor correction circuit, characterized in that, The device includes: An acquisition module, configured to acquire the output voltage, input voltage, and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit, as well as the sampling current and power distribution ratio of each channel; An adjustment module, configured to determine the adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power distribution ratio; A power module, configured to determine the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampling current, adjustment coefficient, and feedforward adjustment coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent.

7. A control device for a two-phase interleaved power factor correction circuit, characterized in that, The device includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, where the computer program is configured to implement the steps of the control method of the two-phase interleaved power factor correction circuit according to any one of claims 1 to 5.

8. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the control method of the two-phase interleaved power factor correction circuit according to any one of claims 1 to 5.

9. A computer program product, characterized in that, The computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps of the control method of the two-phase interleaved power factor correction circuit according to any one of claims 1 to 5.

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