Control method, device, equipment, storage medium and product of two-phase interleaved power factor correction circuit

Abstract

The present application discloses a control method, apparatus, device, storage medium, and product for a two-phase interleaved power factor correction circuit. The method relates to the field of multi-phase interleaved PFC circuit control and is applied to a two-phase interleaved power factor correction circuit. The method comprises: obtaining the output voltage, input voltage, and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit, as well as the sampled current and power allocation ratio of each channel; determining the adjustment coefficient of each channel within the two-phase interleaved power factor correction circuit based on the power allocation ratio; and determining the PWM duty cycle of each channel within the two-phase interleaved power factor correction circuit based on the output voltage, input voltage, sampled current, adjustment coefficient, and feedforward adjustment coefficient, so as to ensure consistent output power across each channel within the two-phase interleaved power factor correction circuit. This method solves the technical problem in conventional two-phase PFC circuits where the two-phase load is affected by hardware, making it difficult to achieve balanced or on-demand load power distribution between the two phases.

Description

Technical Field

[0001] The present application relates to the technical field of control of a multi-phase interleaved PFC circuit, and in particular to a control method, apparatus, device, storage medium, and product for a two-phase interleaved power factor correction circuit. Background Art

[0002] Multi-phase interleaved power factor correction (PFC) circuits are a technology used to improve the power factor, reduce harmonic distortion, and enhance system efficiency in power electronics. By operating multiple single-phase PFC circuits in parallel with interleaved phases, multi-phase interleaved PFC circuits can effectively reduce input current ripple, lower electromagnetic interference (EMI), and improve overall system performance and reliability. Phase interleaving technology staggers the output currents of multiple single-phase PFC circuits by a certain angle (typically 360° / n, where n is the number of phases). This allows the currents of each phase to partially offset each other when combined, thereby reducing the ripple amplitude of the total input current, minimizing the size of the filter inductor and capacitor, and increasing power density.

[0003] The advantages of a multi-phase interleaved PFC circuit include: reduced input current ripple. This reduced ripple current reduces requirements for filter inductors and capacitors, reducing component size and cost. It also improves the system's electromagnetic compatibility (EMC) performance. It also improves the power factor, which approaches unity through a smoother input current waveform. It also improves system efficiency by sharing the load across phases, reducing current stress on each phase and switching losses. This improves overall system efficiency. It also enhances system reliability through multi-phase redundancy, improving system fault tolerance. It also reduces the impact of a single component failure on the system. It also increases power density and reduces the size of filter components, making the system more compact.

[0004] However, the two-phase loads of the traditional two-phase PFC circuit are affected by hardware, and it is difficult to distribute the load power of the two phases evenly or on demand. Summary of the Invention

[0005] The main purpose of this application is to provide a control method, device, equipment, storage medium and product for a two-phase interleaved power factor correction circuit, aiming to solve the technical problem that the two-phase load of a traditional two-phase PFC circuit is affected by the hardware and the load power of the two phases is difficult to be evenly distributed or distributed on demand.

[0006] To achieve the above objectives, the present application proposes a control method for a two-phase interleaved power factor correction circuit, wherein the control method for a two-phase interleaved power factor correction circuit is applied to a two-phase interleaved power factor correction circuit;

[0007] The control method of the two-phase interleaved power factor correction circuit includes:

[0008] Obtaining the output voltage, input voltage, and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit, as well as the sampling current and power distribution ratio of each channel;

[0009] Determining an adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power distribution ratio;

[0010] The PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit is determined according to the output voltage, input voltage, sampling current, regulation coefficient and feedforward regulation coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent.

[0011] Optionally, the step of determining the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, the input voltage, the sampled current, the regulation coefficient, and the feedforward regulation coefficient specifically includes:

[0012] Obtaining a voltage reference value of each channel in the two-phase interleaved power factor correction circuit;

[0013] Determining a current reference value and an output PWM duty cycle compensation amount for each channel in the two-phase interleaved power factor correction circuit according to the regulation coefficient, the input voltage, and the output voltage;

[0014] Determining the sampling current difference of each channel in the two-phase interleaved power factor correction circuit and the output of the current error compensation module in the two-phase interleaved power factor correction circuit according to the current reference value and the sampling current;

[0015] The PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit is determined according to the sampled current difference, the output of the current error compensation module, the feedforward adjustment coefficient and the output PWM duty cycle compensation amount.

[0016] Optionally, the step of determining the current reference value and the output PWM duty cycle compensation amount of each channel in the two-phase interleaved power factor correction circuit according to the adjustment coefficient, the input voltage, and the output voltage specifically includes:

[0017] Determining an output voltage difference and an output of a voltage error compensation module in a two-phase interleaved power factor correction circuit according to the output voltage and the voltage reference value;

[0018] Determining an input voltage average value based on the input voltage;

[0019] determining a current reference value according to the output voltage difference, the input voltage, the input voltage average value, and the regulation coefficient;

[0020] Determining PWM duty cycle compensation amounts of two modes of a voltage feedforward compensation module in the two-phase interleaved power factor correction circuit according to the input voltage, the output voltage, the output of the voltage error compensation module, and the feedforward adjustment coefficient;

[0021] The minimum value among the PWM duty cycle compensation amounts is selected as the output PWM duty cycle compensation amount.

[0022] Optionally, before the step of obtaining the output voltage, input voltage, and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit, as well as the sampled current and power distribution ratio of each channel, the step further includes:

[0023] Obtaining a correction adjustment coefficient and an inductor current of each channel in the two-phase interleaved power factor correction circuit;

[0024] According to the inductor current and the correction adjustment coefficient, the corrected sampling current of each channel in the two-phase interleaved power factor correction circuit is determined.

[0025] Optionally, after the step of determining the adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power allocation ratio, the method further includes:

[0026] Obtaining actual feedback current of each channel in the two-phase interleaved power factor correction circuit;

[0027] According to the feedback current, the output power of each channel of the two-phase interleaved power factor correction circuit is adjusted by the adjustment coefficient so that the actual output power of each channel meets the preset load requirement.

[0028] In addition, to achieve the above-mentioned purpose, the present application also proposes a control device for a two-phase interleaved power factor correction circuit, the device comprising:

[0029] An acquisition module is used to obtain the output voltage, input voltage and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit and the sampling current and power distribution ratio of each channel;

[0030] an adjustment module, configured to determine an adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power allocation ratio;

[0031] A power module is used to determine the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampling current, adjustment coefficient and feedforward adjustment coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent.

[0032] In addition, to achieve the above-mentioned purpose, the present application also proposes a control device for a two-phase interleaved power factor correction circuit, the device comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the control method for the two-phase interleaved power factor correction circuit.

[0033] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by the processor, the steps of the control method of the two-phase interleaved power factor correction circuit are implemented.

[0034] In addition, to achieve the above-mentioned purpose, the present application also proposes a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the steps of the control method of the two-phase interleaved power factor correction circuit.

[0035] One or more technical solutions proposed in this application have at least the following effects:

[0036] The present application discloses a control method, apparatus, device, storage medium, and product for a two-phase interleaved power factor correction circuit. The method is applied to the two-phase interleaved power factor correction circuit. The method includes: obtaining the output voltage, input voltage, and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit, as well as the sampled current and power distribution ratio of each channel; determining the adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit based on the power distribution ratio; and determining the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit based on the output voltage, input voltage, sampled current, adjustment coefficient, and feedforward adjustment coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent. This method solves the technical problem that the two-phase load of a traditional two-phase PFC circuit is affected by hardware, making it difficult to evenly distribute or distribute the load power of the two phases on demand, thereby ensuring the flexibility and consistency of the output of the two-phase interleaved power factor correction circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0038] Figure 1 The two-phase interleaved power factor correction circuit of the present application;

[0039] Figure 2This is a topological diagram of the control method of the two-phase interleaved power factor correction circuit of the present application;

[0040] Figure 3 This is a flow chart of a first embodiment of a control method for a two-phase interleaved power factor correction circuit proposed in an embodiment of the present application;

[0041] Figure 4 This is a flow chart of a second embodiment of a control method for a two-phase interleaved power factor correction circuit proposed in an embodiment of the present application;

[0042] Figure 5 This is a block diagram of the current feedforward compensation module of this application;

[0043] Figure 6 This is a block diagram of the current sampling and correction module of this application;

[0044] Figure 7 This is a flow chart of a third embodiment of a control method for a two-phase interleaved power factor correction circuit proposed in an embodiment of the present application;

[0045] Figure 8 This is a schematic diagram of the module structure of a control device for a two-phase interleaved power factor correction circuit according to an embodiment of the present application;

[0046] Figure 9 This is a schematic diagram of the device structure of the hardware operating environment involved in the control method of the two-phase interleaved power factor correction circuit in the embodiment of the present application.

[0047] Description of Figure Numbers:

[0048]

[0049] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0050] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not intended to limit the present application.

[0051] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0052] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0053] In addition, the descriptions of "first", "second", etc. in this application are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0054] The main solution of this embodiment is to introduce an adjustment coefficient KMx and a feedforward adjustment coefficient into the voltage feedforward link of a two-phase interleaved PFC circuit. By adjusting the voltage feedforward gain KMx and feedforward adjustment coefficient of the corresponding channel based on actual circuit parameters, load power distribution can be more balanced. If, in actual use, the load power of the two-phase inductors requires uneven distribution, the two KMx and feedforward adjustment coefficients can be flexibly adjusted.

[0055] In the embodiment, for ease of description, the following description is made by taking the controller of the two-phase interleaved PFC circuit as the execution subject.

[0056] The present application provides a solution, disclosing a control method, apparatus, device, storage medium, and product for a two-phase interleaved power factor correction circuit. The method is applied to the two-phase interleaved power factor correction circuit. The method comprises: obtaining the output voltage, input voltage, and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit, as well as the sampled current and power distribution ratio of each channel; determining the adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit based on the power distribution ratio; and determining the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit based on the output voltage, input voltage, sampled current, adjustment coefficient, and feedforward adjustment coefficient, so as to ensure that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent. This solves the technical problem of a traditional two-phase PFC circuit in which the two-phase load is affected by hardware, making it difficult to achieve balanced or on-demand load power distribution between the two phases, thereby ensuring the flexibility and consistency of the output of the two-phase interleaved power factor correction circuit.

[0057] It should be noted that if Figure 1 As shown, Figure 1This is the two-phase interleaved power factor correction circuit of the present application. The two-phase interleaved power factor correction circuit includes: two-phase parallel inductors (L1 and L2) coupled between the rectifier bridge and the output end; two switches coupled to the two inductors respectively; a voltage divider circuit composed of resistors R13 and R14, which divides the input voltage UAC and sends it to the input voltage sampling channel; a voltage divider circuit composed of resistors R15 and R16, which divides the output voltage UDC and sends it to the output voltage sampling channel; the divided voltage of resistor R1 is sent to operational amplifier 3 through resistors R2 and R3, and after amplification, it is sent to the sampling channel of inductor current IAC1; the divided voltage of resistor R7 is sent to operational amplifier 5 through resistors R8 and R9, and after amplification, it is sent to the sampling channel of inductor current IAC2; after collecting these feedback signals, the controller calculates the PWM duty cycle for controlling the two switches and emits two PWM waves.

[0058] It is understandable that if Figure 2 As shown, Figure 2 This is a topological diagram of the control method for the two-phase interleaved power factor correction circuit of this application. The topological diagram of the control method for the two-phase interleaved power factor correction circuit includes: a voltage error compensation module, a voltage feedforward compensation module, two current error compensation modules, a current feedforward compensation module, a current sampling correction module, and two PWM (1, 2) output modules.

[0059] Based on this, an embodiment of the present application provides a control method for a two-phase interleaved power factor correction circuit.

[0060] refer to Figure 3 , Figure 3 This is a flow chart of a first embodiment of a control method for a two-phase interleaved power factor correction circuit proposed in an embodiment of the present application.

[0061] Considering that the two-phase load of the traditional two-phase PFC circuit is affected by the hardware, it is difficult to achieve balanced distribution or on-demand distribution of the load power of the two phases, and in order to ensure the flexibility and consistency of the output of the two-phase interleaved power factor correction circuit. Figure 1 As shown, the control method of the two-phase interleaved power factor correction circuit described in this embodiment is applied to the two-phase interleaved power factor correction circuit;

[0062] The control method of the two-phase interleaved power factor correction circuit includes steps S10 to S30:

[0063] Step S10: obtaining the output voltage, input voltage and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit as well as the sampling current and power distribution ratio of each channel.

[0064] It should be noted that the output voltage is UDC and the input voltage is UAC. The power distribution ratio is set according to the load demand power.

[0065] Step S20: determining the adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power allocation ratio.

[0066] It's important to note that the voltage feedforward link (voltage feedforward compensation module) introduces an adjustment coefficient, KMx (x=1 for channel 1). In actual hardware circuits, the feedback signals and output responses of the two phases may differ due to issues like component parameters, leading to different load powers on the two channels. In this case, the voltage feedforward gain, KMx, of the corresponding channel can be adjusted based on the actual circuit parameters to achieve a more balanced load power distribution. If, in actual use, the load power of the two inductors requires uneven distribution, KMx can be flexibly adjusted for both channels.

[0067] It is understandable that if Figure 5 As shown, Figure 5 This is a block diagram of the current feedforward compensation module of this application. In the calculation of the DCCM mode (continuous mode) compensation in the current feedforward link (current feedforward compensation module), the (feedforward) adjustment coefficient PFC_DCCMCSO and mode selection are introduced. In the translation mode (status flag DDCM_SEL is 0), the calculated DCCM compensation is directly added to PFC_DCCMCSO to obtain the final DCCM PWM duty cycle compensation value PFC_COM. In the scaling mode (status flag DDCM_SEL is 1), the calculated DCCM compensation is multiplied by PFC_DCCMCSO to obtain the final DCCM PWM duty cycle compensation value PFC_COM. In the calculation of the DDCM mode (discontinuous mode) compensation in the current feedforward link, the (feedforward) adjustment coefficient PFC_KCOM and adjustment mode selection are introduced.

[0068] Step S30: Determine the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampling current, regulation coefficient and feedforward regulation coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent.

[0069] It should be noted that if Figure 2 As shown, the output voltage difference is determined according to the output voltage and voltage reference value UDC_REF of the two-phase interleaved PFC circuit. The voltage reference value UDC_REF is the DC voltage reference value set by the user. The output voltage difference is sent to the PI controller to generate the control output UDC_UK (the output of the voltage error compensation module). The voltage feedforward compensation module continuously samples the input voltage UAC and obtains the average value UAVG of the input voltage UAC. By calculating The current error compensation module is the inner loop of the two-phase interleaved PFC control. Its input is the difference between the output current reference value IACx_REF of the voltage feedforward compensation module and the actual inductor current IACx sampled by the ADC. This difference is fed into a PI controller to generate the control output sampled current difference value IACx_UK (the output of the current error compensation module). Based on the sampled values ​​of the input voltage UAC and the output voltage UDC, the current feedforward compensation module first calculates the PWM duty cycle compensation value in continuous-circuit mode (DCCM) and then calculates the PWM duty cycle compensation value in discontinuous-circuit mode (DDCM). The smaller of these two values ​​is used as the final PWM duty cycle compensation value PFC_COM output by the current feedforward module. The PWM output module uses the sum of the current error compensation module output IACx_UK and the PWM duty cycle compensation value PFC_COM as a comparison value to output the final PWM waveform to ensure consistent output power across all channels within the two-phase interleaved power factor correction circuit.

[0070] In a specific implementation, the output voltage, input voltage and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit, as well as the sampling current and power distribution ratio of each channel are obtained; based on the power distribution ratio, the adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit is determined; based on the output voltage, input voltage, sampling current, adjustment coefficient and feedforward adjustment coefficient, the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit is determined to make the output power of each channel in the two-phase interleaved power factor correction circuit consistent, thereby solving the technical problem that the two-phase load of the traditional two-phase PFC circuit is affected by hardware and the load power of the two phases is difficult to be evenly distributed or distributed on demand, thereby ensuring the flexibility and consistency of the output of the two-phase interleaved power factor correction circuit.

[0071] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the first embodiment can be referred to the above introduction and will not be described in detail later. Figure 4 , Figure 4 This is a flow chart of a second embodiment of a control method for a two-phase interleaved power factor correction circuit proposed in an embodiment of the present application.

[0072] Considering the limitations of factors such as the error of the actual sampling circuit and the calculation accuracy, the actual DCCM and DDCM mode compensation calculations will have certain errors. Figure 4 As shown, step S30 in this embodiment specifically includes steps S31 to S34:

[0073] Step S31: obtaining a voltage reference value of each channel in the two-phase interleaved power factor correction circuit.

[0074] It should be noted that the voltage reference value UDC_REF is the DC voltage reference value set by the user, and the sampling current is IACx (x=1 is channel 1).

[0075] Step S32: determining the current reference value and output PWM duty cycle compensation amount of each channel in the two-phase interleaved power factor correction circuit according to the adjustment coefficient, input voltage and output voltage.

[0076] It should be noted that the current reference value is IACx_REF, and the output PWM duty cycle compensation value is PFC_COM.

[0077] Step S33: determining the sampling current difference of each channel in the two-phase interleaved power factor correction circuit and the output of the current error compensation module in the two-phase interleaved power factor correction circuit according to the current reference value and the sampling current.

[0078] It should be noted that the current error compensation module is the inner loop of the two-phase interleaved PFC control. Its input is the difference between the output current reference value IACx_REF of the voltage feedforward compensation module and the actual inductor current IACx sampled by the ADC. This difference is sent to the PI controller to generate the control output IACx_UK (the output of the current error compensation module).

[0079] Step S34: determining the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the sampled current difference, the output of the current error compensation module, the feedforward adjustment coefficient and the output PWM duty cycle compensation amount.

[0080] In a specific implementation, a voltage reference value of each channel in the two-phase interleaved power factor correction circuit is obtained; a current reference value and an output PWM duty cycle compensation amount of each channel in the two-phase interleaved power factor correction circuit are determined based on the adjustment coefficient, the input voltage, and the output voltage; a sampled current difference of each channel in the two-phase interleaved power factor correction circuit and an output of a current error compensation module in the two-phase interleaved power factor correction circuit are determined based on the current reference value and the sampled current; and a PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit is determined based on the sampled current difference, the output of the current error compensation module, and the output PWM duty cycle compensation amount, thereby reducing the difficulty of parameter tuning of the PI controller of the current inner loop in the two-phase interleaved PFC circuit control.

[0081] Furthermore, the step S32 specifically includes:

[0082] Determining an output voltage difference and an output of a voltage error compensation module in a two-phase interleaved power factor correction circuit according to the output voltage and the voltage reference value;

[0083] Determining an input voltage average value based on the input voltage;

[0084] determining a current reference value according to the output voltage difference, the input voltage, the input voltage average value, and the regulation coefficient;

[0085] Determining PWM duty cycle compensation amounts of two modes of a voltage feedforward compensation module in the two-phase interleaved power factor correction circuit according to the input voltage, the output voltage, the output of the voltage error compensation module, and the feedforward adjustment coefficient;

[0086] The minimum value among the PWM duty cycle compensation amounts is selected as the output PWM duty cycle compensation amount.

[0087] It should be noted that if Figure 2 As shown, the two modes include: discontinuous mode DDCM and continuous mode DCCM. The output voltage difference is determined according to the output voltage of the two-phase interleaved PFC circuit and the voltage reference value UDC_REF. The voltage reference value UDC_REF is the DC voltage reference value set by the user. The output voltage difference is sent to the PI controller to generate the control output UDC_UK (the output of the voltage error compensation module). The voltage feedforward compensation module continuously samples the input voltage UAC and obtains the average value UAVG of the input voltage UAC. To the two inductor current reference values. Figure 5 As shown, Figure 5 This is a block diagram of the current feedforward compensation module of this application. Based on the sampled values ​​of the input voltage UAC and the output voltage UDC, the current feedforward compensation module first calculates the PWM duty cycle compensation in continuous mode (DCCM) and then calculates the PWM duty cycle compensation in discontinuous mode (DDCM). The smaller of the two is used as the final output PWM duty cycle compensation value, PFC_COM, of the current feedforward module. Due to issues such as electromagnetic interference and voltage offset in the system during operation, the sampling of the feedback circuit may have errors, which in turn affect the calculation of the current feedforward compensation value. The DCCM compensation calculation in the current feedforward link (current feedforward compensation module) uses the feedforward adjustment coefficient PFC_DCCMCSO and the mode selection. In shift mode (status flag DDCM_SEL is 0), the calculated DCCM compensation is directly added to PFC_DCCMCSO to obtain the final DCCM PWM duty cycle compensation, PFC_COM. In scaling mode (status flag DDCM_SEL is 1), the calculated DCCM compensation is multiplied by PFC_DCCMCSO to obtain the final DCCM PWM duty cycle compensation, PFC_COM. The DDCM compensation calculation in the current feedforward link uses the feedforward adjustment coefficient PFC_KCOM and the adjustment mode selection.

[0088] In a specific implementation, a feedforward adjustment coefficient is obtained; based on the output voltage and voltage reference value, the output voltage difference and the output of the voltage error compensation module in the two-phase interleaved power factor correction circuit are determined; based on the input voltage, the input voltage average value is determined; based on the output voltage difference, the input voltage, the input voltage average value, and the adjustment coefficient, a current reference value is determined; based on the input voltage, the output voltage, the output of the voltage error compensation module, and the feedforward adjustment coefficient, the PWM duty cycle compensation values ​​for two modes of the voltage feedforward compensation module in the two-phase interleaved power factor correction circuit are determined; and the minimum of these PWM duty cycle compensation values ​​is selected as the output PWM duty cycle compensation value. This reduces the difficulty of parameter tuning for the PI controller in the current inner loop of the two-phase interleaved PFC circuit control.

[0089] Furthermore, considering that the inductor current resembles a sawtooth wave during actual operation, the instantaneous inductor current at the sampling moment is used to describe the average inductor current of the sawtooth wave. Therefore, the sampling timing has a significant impact. Moreover, in the discontinuous mode, there are moments when the current is zero. If the instantaneous current sampled by the ADC is used to reflect the actual effective current, the sampled current will be too large. Before step S10, the following steps may also be included:

[0090] Obtaining a correction adjustment coefficient and an inductor current of each channel in the two-phase interleaved power factor correction circuit;

[0091] According to the inductor current and the correction adjustment coefficient, the corrected sampling current of each channel in the two-phase interleaved power factor correction circuit is determined.

[0092] It should be noted that if Figure 6 As shown, Figure 6 This is a block diagram of the current sampling and correction module in this application. The current sampling and correction module introduces a correction (adjustment) coefficient, PFC_KIAC. In continuous mode, PFC_KIAC is used to linearly scale the sampling results. In discontinuous mode, the effects of duty cycle and input and output voltages are introduced to correct the sampling results. COM_ST is the inductor continuous / discontinuous mode status flag, which is 1 in continuous mode and 0 in discontinuous mode.

[0093] In a specific implementation, the correction adjustment coefficient and the inductor current of each channel in the two-phase interleaved power factor correction circuit are obtained; based on the inductor current and the correction adjustment coefficient, the corrected sampling current of each channel in the two-phase interleaved power factor correction circuit is determined to ensure the accuracy of the sampling current.

[0094] Based on the second embodiment of the present application, in the third embodiment of the present application, the same or similar contents as those in the second embodiment can be referred to the above introduction and will not be described in detail later. Figure 7 , Figure 7This is a flow chart of a third embodiment of a control method for a two-phase interleaved power factor correction circuit proposed in an embodiment of the present application.

[0095] Considering that in actual use, the load power of the two-phase inductance needs to be distributed unevenly, in order to flexibly adjust the two-way KMx, such as Figure 7 As shown, after step S20 in this embodiment, steps S201 to S202 are further included:

[0096] Step S201: obtaining the actual feedback current of each channel in the two-phase interleaved power factor correction circuit;

[0097] Step S202: According to the feedback current, the output power of each channel of the two-phase interleaved power factor correction circuit is adjusted by the adjustment coefficient so that the actual output power of each channel meets the preset load requirement.

[0098] It should be noted that the preset load requirement can be obtained from the load nameplate or technical manual, including its rated power (W), current (A), or voltage (U), or it can be set according to actual needs. A current sensing circuit is provided at the output of the two-phase interleaved power factor correction (PFC) circuit, using common current sensing components such as current transformers and shunt resistors, to obtain real-time feedback current signals.

[0099] In specific implementation, the load power of the two-phase inductor needs to be distributed unevenly, and the two KMx can be flexibly adjusted to meet the load power requirements.

[0100] In addition, to achieve the above purpose, Figure 8 As shown, the present application also proposes a control device for a two-phase interleaved power factor correction circuit, the device comprising:

[0101] An acquisition module 10 is configured to acquire the output voltage, input voltage, and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit, as well as the sampling current and power distribution ratio of each channel;

[0102] An adjustment module 20, configured to determine an adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power allocation ratio;

[0103] The power module 30 is used to determine the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampling current, adjustment coefficient and feedforward adjustment coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent.

[0104] The control device for a two-phase interleaved power factor correction circuit provided in this application utilizes the control method for a two-phase interleaved power factor correction circuit in the above-described embodiments, thereby resolving the technical problem in conventional two-phase PFC circuits where the two-phase loads are affected by hardware, making it difficult to evenly distribute or distribute the load power of the two phases on demand. Compared to the prior art, the beneficial effects of the control device for a two-phase interleaved power factor correction circuit provided in this application are the same as those of the control method for a two-phase interleaved power factor correction circuit provided in the above-described embodiments. Other technical features of the control device for a two-phase interleaved power factor correction circuit are the same as those disclosed in the above-described embodiments and are not further described here.

[0105] In addition, to achieve the above-mentioned purpose, the present application also proposes a control device for a two-phase interleaved power factor correction circuit, the device comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the control method for the two-phase interleaved power factor correction circuit.

[0106] like Figure 9 As shown, the control device for a two-phase interleaved power factor correction circuit may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes based on a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. RAM 1004 also stores various programs and data required for the operation of the control device for the two-phase interleaved power factor correction circuit. Processing device 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the control device of the two-phase interleaved power factor correction circuit to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows a control device of the two-phase interleaved power factor correction circuit with various systems, it should be understood that it is not required to implement or have all of the systems shown. More or fewer systems can be implemented or have instead.

[0107] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program comprising program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0108] The control device for a two-phase interleaved power factor correction circuit provided in this application utilizes the control method for a two-phase interleaved power factor correction circuit in the above-described embodiment, thereby resolving the technical problem in conventional two-phase PFC circuits where the two-phase loads are affected by hardware, making it difficult to evenly distribute or distribute the load power on both phases on demand. Compared to the prior art, the control device for a two-phase interleaved power factor correction circuit provided in this application achieves the same beneficial effects as the control method for a two-phase interleaved power factor correction circuit provided in the above-described embodiment. Other technical features of the control device for a two-phase interleaved power factor correction circuit are the same as those disclosed in the method in the above-described embodiment and are not further elaborated upon here.

[0109] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0110] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

[0111] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by the processor, the steps of the control method of the two-phase interleaved power factor correction circuit are implemented.

[0112] The computer-readable storage medium provided herein may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including, but not limited to, wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0113] The computer-readable storage medium may be included in the control device of the two-phase interleaved power factor correction circuit; or may exist independently without being assembled into the control device of the two-phase interleaved power factor correction circuit.

[0114] The above-mentioned computer-readable storage medium carries one or more programs. When the above-mentioned one or more programs are executed by the control device of the two-phase interleaved power factor correction circuit, the control device of the two-phase interleaved power factor correction circuit: obtains the output voltage and input voltage of each channel in the two-phase interleaved power factor correction circuit; determines the adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit based on the input voltage and output voltage; determines the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit based on the adjustment coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent.

[0115] Computer program code for performing the operations of the present application may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0116] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0117] The modules described in the embodiments of the present application may be implemented in software or hardware, wherein the name of a module does not necessarily limit the unit itself.

[0118] The computer-readable storage medium provided herein stores computer-readable program instructions (i.e., a computer program) for executing the aforementioned control method for a two-phase interleaved power factor correction circuit. This computer-readable storage medium can address the technical issue of conventional two-phase PFC circuits, where the two-phase loads are affected by hardware, making it difficult to evenly distribute or distribute power on demand across the two phases. Compared to the prior art, the computer-readable storage medium provided herein offers the same beneficial effects as the control method for a two-phase interleaved power factor correction circuit provided in the aforementioned embodiments, and therefore is not further elaborated upon here.

[0119] In addition, to achieve the above-mentioned purpose, the present application also proposes a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the steps of the control method of the two-phase interleaved power factor correction circuit.

[0120] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A control method for a two-phase interleaved power factor correction circuit, characterized in that: The control method of the two-phase interleaved power factor correction circuit is applied to the two-phase interleaved power factor correction circuit; The control method of the two-phase interleaved power factor correction circuit includes: Obtaining the output voltage, input voltage, and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit, as well as the sampling current and power distribution ratio of each channel; Determining an adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power distribution ratio; Determining a PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampled current, regulation coefficient, and feedforward regulation coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent; The step of determining the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampling current, adjustment coefficient and feedforward adjustment coefficient specifically includes: Obtaining a voltage reference value of each channel in the two-phase interleaved power factor correction circuit; Determining a current reference value and an output PWM duty cycle compensation amount for each channel in the two-phase interleaved power factor correction circuit according to the regulation coefficient, the input voltage, and the output voltage; Determining the sampling current difference of each channel in the two-phase interleaved power factor correction circuit and the output of the current error compensation module in the two-phase interleaved power factor correction circuit according to the current reference value and the sampling current; The PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit is determined according to the sampled current difference, the output of the current error compensation module, the feedforward adjustment coefficient and the output PWM duty cycle compensation amount.

2. The control method of the two-phase interleaved power factor correction circuit according to claim 1, wherein: The step of determining the current reference value and the output PWM duty cycle compensation amount of each channel in the two-phase interleaved power factor correction circuit according to the adjustment coefficient, the input voltage, and the output voltage specifically includes: Determining an output voltage difference and an output of a voltage error compensation module in a two-phase interleaved power factor correction circuit according to the output voltage and the voltage reference value; Determining an input voltage average value based on the input voltage; determining a current reference value according to the output voltage difference, the input voltage, the input voltage average value, and the regulation coefficient; Determining PWM duty cycle compensation amounts of two modes of a voltage feedforward compensation module in the two-phase interleaved power factor correction circuit according to the input voltage, the output voltage, the output of the voltage error compensation module, and the feedforward adjustment coefficient; The minimum value among the PWM duty cycle compensation amounts is selected as the output PWM duty cycle compensation amount.

3. The control method of the two-phase interleaved power factor correction circuit according to claim 1, wherein: Before the step of obtaining the output voltage, input voltage, and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit, as well as the sampling current and power distribution ratio of each channel, the method further includes: Obtaining a correction adjustment coefficient and an inductor current of each channel in the two-phase interleaved power factor correction circuit; According to the inductor current and the correction adjustment coefficient, the corrected sampling current of each channel in the two-phase interleaved power factor correction circuit is determined.

4. The control method of the two-phase interleaved power factor correction circuit according to claim 1, wherein: After the step of determining the adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power allocation ratio, the method further includes: Obtaining actual feedback current of each channel in the two-phase interleaved power factor correction circuit; According to the feedback current, the output power of each channel of the two-phase interleaved power factor correction circuit is adjusted by the adjustment coefficient so that the actual output power of each channel meets the preset load requirement.

5. A control device for a two-phase interleaved power factor correction circuit, characterized in that: The device comprises: An acquisition module is used to obtain the output voltage, input voltage and feedforward adjustment coefficient of the two-phase interleaved power factor correction circuit and the sampling current and power distribution ratio of each channel; an adjustment module, configured to determine an adjustment coefficient of each channel in the two-phase interleaved power factor correction circuit according to the power allocation ratio; A power module is used to determine the PWM duty cycle of each channel in the two-phase interleaved power factor correction circuit according to the output voltage, input voltage, sampling current, adjustment coefficient and feedforward adjustment coefficient, so that the output power of each channel in the two-phase interleaved power factor correction circuit is consistent The power module is further used to obtain a voltage reference value for each channel in the two-phase interleaved power factor correction circuit; determine a current reference value and an output PWM duty cycle compensation amount for each channel in the two-phase interleaved power factor correction circuit based on the adjustment coefficient, input voltage, and output voltage; determine a sampled current difference for each channel in the two-phase interleaved power factor correction circuit and an output of a current error compensation module in the two-phase interleaved power factor correction circuit based on the current reference value and the sampled current; and determine a PWM duty cycle for each channel in the two-phase interleaved power factor correction circuit based on the sampled current difference, the output of the current error compensation module, the feedforward adjustment coefficient, and the output PWM duty cycle compensation amount.

6. A control device for a two-phase interleaved power factor correction circuit, characterized in that: The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the control method of the two-phase interleaved power factor correction circuit according to any one of claims 1 to 4.

7. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the control method of the two-phase interleaved power factor correction circuit according to any one of claims 1 to 4 are implemented.

8. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the control method of the two-phase interleaved power factor correction circuit according to any one of claims 1 to 4 are implemented.

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