XNOR gate and XOR gate circuit realized based on ternary memristor

Abstract

The invention discloses an XNOR gate and an XOR gate circuit realized based on three-valued memristors. The XNOR gate and the XOR gate circuit comprise three memristors, three voltage sources, four voltage control type switches and an auxiliary resistor, wherein the three memristors are two input memristors and one output memristor respectively. The XNOR gate controls the conduction of the voltage control type switches S1 and S3 by using the parallel partial voltage Vab input into the memristor, controls the conduction of the voltage control type switches S2 and S4 by using the partial voltage Vbc of the auxiliary resistor R, and determines the threshold voltages VS1, VS2, VS3 and VS4 of the voltage control type switches S1, S2, S3 and S4 according to the partial voltages Vab and Vbc, thereby realizing XNOR logic operation. According to the invention, the limitation of the traditional binary circuit on the information bearing capability is overcome, the operational capability of the circuit is enhanced, and the circuit structure is simpler.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital logic circuit design, and relates to a method for implementing an exclusive-NOR gate and an exclusive-OR gate circuit based on a ternary memristor. Background Art

[0002] In the past few decades, binary logic has been extremely widely used in digital logic systems, greatly promoting a million-fold reduction in chip costs. However, as the speed of shrinking the size of traditional CMOS devices slows down, the continued validity of Moore's Law is facing many dilemmas. In order to maintain the continuity of Moore's Law, researchers have proposed many ideas, one of which is to find devices with smaller sizes to replace traditional CMOS transistors. As a non-linear electronic component with a memory function, the memristor has characteristics such as small size, simple structure, easy integration, and low power consumption, and is regarded as a strong candidate to replace traditional transistors and maintain and promote the progress of Moore's Law. The unique performance characteristics of the memristor indicate that it will play a key role in the design of a new generation of computer architectures that integrate logic operations and data storage functions, and is expected to lead the innovation of computer architectures.

[0003] In traditional digital logic circuit design, binary logic is widely used because of its simple structure, easy signal generation, and strong anti-interference ability. However, this logic system has significant limitations. It only transmits information through two states of "0" and "1", which limits the amount of information carried by a single signal line, resulting in a significant increase in the wiring area in large-scale integrated circuits. As a multi-valued logic, ternary logic has the advantages of carrying more information, lower complexity between circuit connections, and stronger computing power compared with traditional binary logic, significantly improving data transmission efficiency and circuit computing power.

[0004] Research has found that digital logic circuits based on memristors can effectively reduce circuit area and power consumption. In ternary logic, the signal is no longer limited to "0" and "1", but a third state is added. This characteristic not only reduces the number of lines required to implement the same function, reduces the complexity and layout difficulty of circuit connections, but also enhances the processing ability and flexibility of the circuit, providing the possibility for designing higher-performance and larger-scale integrated circuits. Therefore, in some specific application scenarios, such as high-efficiency data transmission or complex logic operation scenarios, ternary logic exhibits more superior performance and potential than traditional binary logic. Summary of the Invention

[0005] Aiming at the deficiencies of the prior art, the present invention proposes an exclusive-NOR gate and an exclusive-OR gate circuit implemented based on a ternary memristor.

[0006] The technical solutions adopted by the present invention to solve the technical problems are as follows:

[0007] A XNOR gate circuit implemented based on three - valued memristors includes three memristors, namely two input memristors M in1 and M in2 and an output memristor M out ; three voltage sources are V, V set0 and V set2 ; four voltage - controlled switches S1, S2, S3 and S4; and an auxiliary resistor R.

[0008] In the XNOR gate circuit described above, the positive pole of voltage source V is connected to the positive poles of two input memristors M in1 and M in2 , the positive poles of voltage - controlled switches S1 and S3; the negative poles of two input memristors M in1 and M in2 , the negative poles of voltage - controlled switches S1 and S3, the positive poles of voltage - controlled switches S2 and S4 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the negative poles of voltage - controlled switches S2 and S4, the negative pole of the output memristor M out and the ground wire; voltage - controlled switches S1 and S2 are in series, and the positive pole of voltage source V set0 is connected to the positive pole of the output memristor M out through voltage - controlled switches S1 and S2; voltage - controlled switches S3 and S4 are in parallel, and the positive pole of voltage source V set2 is connected to the positive pole of the output memristor M out through voltage - controlled switches S3 and S4, and the negative poles of voltage sources V, V set0 and V set2 are all connected to the ground wire.

[0009] A three - valued XOR gate circuit implemented based on three - valued memristors includes three memristors, namely two input memristors M in1 、M in2 and an output memristor M out ; three voltage sources are V、V set0 and V set2 ; four voltage - controlled switches S1、S2、S3 and S4; and an auxiliary resistor R.

[0010] In the XOR gate circuit described above, the positive pole of voltage source V is connected to the positive poles of two input memristors M in1 and M in2 , the positive poles of voltage - controlled switches S1 and S3; the negative poles of two input memristors M in1 and M in2 , the negative poles of voltage - controlled switches S1 and S3, the positive poles of voltage - controlled switches S2 and S4 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the negative poles of voltage - controlled switches S2 and S4, the negative pole of the output memristor Mout is connected to the negative electrode and the ground wire; the voltage-controlled switches S1 and S2 are connected in series, and the positive electrode of the voltage source V set2 is connected to the output memristor M through the voltage-controlled switches S1 and S2 out at the positive electrode; the voltage-controlled switches S3 and S4 are connected in parallel, and the positive electrode of the voltage source V set0 is connected to the output memristor M through the voltage-controlled switches S3 and S4 out at the positive electrode, and the negative electrodes of the voltage sources V, V set0 and V set2 are all connected to the ground wire.

[0011] The input memristors of the exclusive-NOR gate circuit adopt a parallel structure, and the initial state of the output memristor M out is R M . The working process of the exclusive-NOR gate circuit is carried out in two stages and is driven by the excitation voltage source V. The first stage is the initial stage (0 - 10 ms), and V outputs a relatively small initial voltage V Init to obtain the initial resistance state of the memristor; the second stage is the operating stage (10 - 20 ms), and V outputs a relatively large operating voltage V Run to complete the exclusive-NOR logic operation. The voltage sources V set0 and V set2 are set voltage sources used to perform the "0" and "2" setting operations on the output memristor M out . The switches S1, S2, S3, and S4 are voltage-controlled switches, and the switches conduct only when the applied control voltage exceeds their threshold voltages. The working principle of the exclusive-NOR gate is to use the parallel voltage division V in1 of the input memristors M in2 and M ab to control the conduction of the voltage-controlled switches S1 and S3, and the voltage division V bc of the auxiliary resistor R to control the conduction of the voltage-controlled switches S2 and S4. Further, according to the voltage division of V ab and V bc , the threshold voltages V S1 , V S2 , V S3 and V S4 of the voltage-controlled switches S1, S2, S3, and S4 are determined, thus realizing the exclusive-NOR logic operation.

[0012] Based on the exclusive-NOR gate circuit, the exclusive-OR gate circuit changes the positions of the set voltage sources V set0 and V set2 . Its excitation voltage source output and switch threshold voltages are the same as those of the exclusive-NOR gate circuit, so that the circuit realizes the exclusive-OR logic operation.

[0013] Advantages of the present invention:

[0014] The present invention designs a novel three - valued logic exclusive - NOR gate and exclusive - OR circuit model based on a three - valued memristor. This innovative technology effectively overcomes the limitations of traditional binary circuits in information - carrying capacity, effectively reduces the complexity between circuit connections, enhances the computing power of the circuit, and simplifies the circuit structure. This circuit model can be used in application research in many fields such as multi - valued digital logic operations, and is of great significance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] To more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required in the description of the prior art.

[0016] Figure 1 is the exclusive - NOR gate circuit of the present invention based on a three - valued memristor;

[0017] Figure 2 is the exclusive - OR gate circuit of the present invention based on a three - valued memristor. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] To enable those skilled in the art to better understand the solution of the present invention, the following further describes the proposed model of the present invention in conjunction with the drawings and specific embodiments.

[0019] As Figure 1 shown, an exclusive - NOR gate circuit implemented based on a three - valued memristor includes three memristors, namely two input memristors M in1 , M in2 and an output memristor M out ; three voltage sources are V, V set0 and V set2 ; four voltage - controlled switches S1, S2, S3 and S4; and an auxiliary resistor R.

[0020] In the described exclusive - NOR gate circuit, the positive pole of the voltage source V is connected to the positive poles of the two input memristors M in1 and M in2 , the positive poles of the voltage - controlled switches S1 and S3; the negative poles of the two input memristors M in1 and M in2 , the negative poles of the voltage - controlled switches S1 and S3, the positive poles of the voltage - controlled switches S2 and S4 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the negative poles of the voltage - controlled switches S2 and S4, the negative pole of the output memristor M out and the ground wire; the voltage - controlled switches S1 and S2 are in series, and the positive pole of the voltage source V set0 is connected to the positive pole of the output memristor M out through the voltage - controlled switches S1 and S2; the voltage - controlled switches S3 and S4 are in parallel, and the positive pole of the voltage source V set2 is connected to the positive pole of the output memristor M through the voltage - controlled switches S3 and S4out is connected to the positive electrode, and the voltage sources V, V set0 and V set2 have their negative electrodes connected to the ground wire.

[0021] As Figure 2 shown, a ternary XOR gate circuit implemented based on a ternary memristor includes three memristors, namely two input memristors M in1 , M in2 and an output memristor M out ; three voltage sources are V, V set0 and V set2 ; four voltage-controlled switches S1, S2, S3 and S4; and an auxiliary resistor R.

[0022] In the said XOR gate circuit, the positive electrode of the voltage source V is connected to the positive electrodes of the two input memristors M in1 and M in2 , the positive electrodes of the voltage-controlled switches S1 and S3; the negative electrodes of the two input memristors M in1 and M in2 , the negative electrodes of the voltage-controlled switches S1 and S3, the positive electrodes of the voltage-controlled switches S2 and S4 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the negative electrodes of the voltage-controlled switches S2 and S4, the negative electrode of the output memristor M out and the ground wire; the voltage-controlled switches S1 and S2 are in series, and the positive electrode of the voltage source V set2 is connected to the positive electrode of the output memristor M out through the voltage-controlled switches S1 and S2; the voltage-controlled switches S3 and S4 are in parallel, and the positive electrode of the voltage source V set0 is connected to the positive electrode of the output memristor M out through the voltage-controlled switches S3 and S4, and the negative electrodes of the voltage sources V, V set0 and V set2 are all connected to the ground wire.

[0023] The ternary memristor model adopted in the present invention is a voltage-controlled threshold type ternary memristor, and its two threshold voltages are respectively v th1 = 1V, v th2 = 1.2V, where R L , R M and R H have three resistance states of 100Ω, 500Ω, 1500Ω respectively. The resistance states of the memristor are analyzed below.

[0024] (1) When the initial state of the memristor is R H or R M , if the voltage v > 1.2V at this time, the state of the memristor switches to R L . If the initial state of the memristor is RL , when \(v\geq - 1V\), the memristor maintains \(R\) L unchanged. So when \(v>1.2V\), the memristor can switch to \(R\) L state or maintain the \(R\) L state.

[0025] (2) When the initial state of the memristor is \(R\) H , if the voltage \(1V < v < 1.2V\) at this time, the state of the memristor switches to \(R\) M . When the initial state of the memristor is \(R\) L , if the voltage \(-1.2V < v < 1V\) at this time, the state of the memristor switches to \(R\) M . When the initial state of the memristor is \(R\) M , when the voltage range is \(-1.2V\leq v\leq1.2V\), the memristor maintains the state \(R\) M . Therefore, when the voltage range is \([-1.2V, 1.2V]\), the memristor can switch to the \(R\) M state or maintain the \(R\) M state.

[0026] (3) When the initial state of the memristor is \(R\) H or \(R\) M , if the voltage \(v < - 1.2V\) at this time, the state of the memristor switches to \(R\) H . When the initial state of the memristor is \(R\) H , as long as \(v\leq1V\) is ensured, its resistance value maintains \(R\) H unchanged. Therefore, when \(v < - 1.2V\), the memristor can switch to the \(R\) H state or maintain the \(R\) H state.

[0027] In order to more intuitively observe the voltage ranges required for the resistance value switching and maintaining of the ternary memristor, the above three cases are organized in Table 1.

[0028] Table 1 Voltage ranges required for resistance state switching and maintaining

[0029]

[0030]

[0031] The XNOR gate and XOR gate circuits based on the ternary memristor designed by the present invention. The ternary logic described is a multi-valued logic with three different logic states, namely: "0", "1" and "2". The ternary logic gate circuits designed by the present invention all use the resistance value of the memristor as the logic state variable. The states of the memristor corresponding to the three values are \(R\) H , \(R\) M and \(R\) L , where \(R\) HRepresents logical "0"; R M Represents logical "1"; R L Represents logical "2".

[0032] The truth tables of the XNOR gate and XOR gate designed by the present invention are shown in Table 2 below, where X1 and X2 represent the input signals of the XNOR gate and XOR gate, and Y XNOR Represents the output of the XNOR gate, and Y XOR Represents the output of the XOR gate.

[0033] Table 2 Truth tables of the positive three-valued "XNOR" gate and "XOR" gate

[0034]

[0035] The XNOR gate circuit based on the three-valued memristor designed by the present invention is as Figure 1 shown, where M in1 , M in2 are input memristors, M out is the output memristor, and the initial resistance value of M out is R M . Among the three voltage sources, V is the excitation voltage source, and V Set0 and V Set2 are set voltage sources used to perform the "0" and "2" setting operations on M out . The voltage values output by V Set0 and V Set2 are determined according to the threshold voltage of the three-valued memristor. From the above analysis of the memristor resistance value, the threshold voltages for the memristor to switch to logical "0" and "2" are -1.2V and 1.2V respectively. Therefore, V Set0 is set to -1.3V, and V Set2 is set to 1.4V. S1, S2, S3, and S4 are voltage-controlled switches in the circuit. The on and off of the switches can be controlled by voltage division. When the voltage across them is detected to exceed the set threshold, the switch will conduct; otherwise, the switch is in the off state. The auxiliary resistor R is added to the circuit to increase the voltage division situation of the circuit to assist the circuit in realizing the XNOR logic operation, and the value of R is 600Ω.

[0036] The working principle of the XNOR gate is to use the voltage division V in1 , V in2 of the input memristors M ab to control the conduction of S1 and S3, and the voltage division V bc of R to control the conduction of S2 and S4. Switches S1 and S2 in the circuit are in series, so S1 and S2 must conduct simultaneously for V Set0 to perform the "0" setting operation on M out . Switches S3 and S4 are in parallel, so as long as any one of S3 and S4 conducts, VSet2 can perform an operation of setting M to "2". out

[0037] The circuits involved in the present invention are all driven by an excitation voltage source V, and the operation can be divided into two stages. The first stage is the initial stage (0 - 10 ms), where V outputs a relatively small initial voltage V Init to obtain the initial resistance state of the memristor; the second stage is the operation stage (10 - 20 ms), where V outputs a relatively large operation voltage V Run to complete the exclusive-NOR logic operation. The exclusive-NOR gate circuit designed in this section sets V Init to 0.5 V and V Run to 1.55 V.

[0038] In the exclusive-NOR gate circuit, the threshold voltages of switches V S1 -V S4 are set to 0.2 V, 1.2 V, 0.8 V, and 1.4 V respectively. According to different inputs, it can be divided into the following nine cases:

[0039] (1) When the input is "(0, 0)", the input memristors M in1 = 1500 Ω, M in2 = 1500 Ω, corresponding to the divided voltages V ab = 0.861 V, V bc = 0.689 V. V ab is higher than the threshold V S1 of S1, higher than the threshold V S3 of S3, V bc is lower than the threshold V S2 of S2, lower than the threshold V S4 of S4. At this time, switches S1 and S3 are conducting, S2 and S4 are non-conducting, and V Set2 will set the output memristor M out to 100 Ω, and the logic gate outputs logic "2".

[0040] (2) When the input is "(0, 1)", the input memristors M in1 = 1500 Ω, M in2 = 500 Ω, corresponding to the divided voltages V ab = 0.596 V, V bc = 0.954 V. V ab is higher than the threshold V S1 of S1, lower than the threshold V S3 of S3, V bc is lower than the threshold V S2 of S2, lower than the threshold V S4 of S4. At this time, switches S1 and S2 are conducting, S3 and S4 are non-conducting, and the output memristor M out ​With the initial configuration remaining unchanged, the logic gate outputs logic "1".

[0041] (3) When the input is "(0, 2)", the input memristor M in1 = 1500 Ω, M in2 = 100 Ω, corresponding voltage division V ab = 0.209 V, V bc = 1.341 V. V ab is higher than the threshold V of S1 S1 and lower than the threshold V of S3 S3 , V bc is higher than the threshold V of S2 S2 and lower than the threshold V of S4 S4 . At this time, switch S1 is turned on, S2 is turned on, S3 is turned off, S4 is turned off, and V Set0 will set the output memristor M out to 1500 Ω, and the logic gate outputs logic "0".

[0042] (4) When the input is "(1, 0)", the input memristor M in1 = 500 Ω, M in2 = 1500 Ω, corresponding voltage division V ab = 0.596 V, V bc = 0.954 V. V ab is higher than the threshold V of S1 S1 and lower than the threshold V of S3 S3 , V bc is lower than the threshold V of S2 S2 and lower than the threshold V of S4 S4 . At this time, switch S1 is turned on, S2 is turned off, S3 is turned off, S4 is turned off, and the output memristor M out maintains the initial configuration unchanged, and the logic gate outputs logic "1".

[0043] (5) When the input is "(1, 1)", the input memristor M in1 = 500 Ω, M in2 = 500 Ω, corresponding voltage division V ab = 0.456 V, V bc = 1.094 V. V ab is higher than the threshold V of S1 S1 and lower than the threshold V of S3 S3 , V bc is lower than the threshold V of S2 S2 and lower than the threshold V of S4 S4 . At this time, switch S1 is turned on, S2 is turned off, S3 is turned off, S4 is turned off, and the output memristor M out maintains the initial configuration unchanged, and the logic gate outputs logic "1".

[0044] When the input is "(1, 2)", the input memristor M in1 = 500 Ω, M in2 = 100 Ω, corresponding partial voltage V ab = 0.189 V, V bc = 1.361 V. V ab is lower than the threshold V of S1 S1 , is lower than the threshold V of S3 S3 , V bc is higher than the threshold V of S2 S2 , is lower than the threshold V of S4 S4 , at this time, switch S1 is off, S2 is on, S3 is off, S4 is off, and the output memristor M out maintains the initial configuration unchanged, and the logic gate outputs logic "1".

[0045] (7) When the input is "(2, 0)", the input memristor M in1 = 100 Ω, M in2 = 1500 Ω, corresponding partial voltage V ab = 0.209 V, V bc = 1.341 V. V ab is higher than the threshold V of S1 S1 , is lower than the threshold V of S3 S3 , V bc is higher than the threshold V of S2 S2 , is lower than the threshold V of S4 S4 , at this time, switch S1 is on, S2 is on, S3 is off, S4 is off, V Set0 will set the output memristor M out to 1500 Ω, and the logic gate outputs logic "0".

[0046] (8) When the input is "(2, 1)", the input memristor M in1 = 100 Ω, M in2 = 500 Ω, corresponding partial voltage V ab = 0.189 V, V bc = 1.361 V. V ab is lower than the threshold V of S1 S1 , is lower than the threshold V of S3 S3 , V bc is higher than the threshold V of S2 S2 , is lower than the threshold V of S4 S4 , at this time, switch S1 is off, S2 is on, S3 is off, S4 is off, and the output memristor M out maintains the initial configuration unchanged, and the logic gate outputs logic "1".

[0047] (9) When the input is "(2, 2)", the input memristor M in1 = 100 Ω, Min2 = 100 Ω, corresponding voltage division V ab = 0.119 V, V bc = 1.431 V. V ab is lower than the threshold voltage V of S1 S1 , is lower than the threshold voltage V of S3 S3 , V bc is higher than the threshold voltage V of S2 S2 , is higher than the threshold voltage V of S4 S4 , at this time, switch S1 is off, S2 is on, S3 is off, S4 is on, V Set2 will set the output memristor M out to 100 Ω, and the logic gate outputs logic "2".

[0048] The XOR gate circuit based on the ternary memristor designed by the present invention is as Figure 2 shown. Since the output of the ternary XOR gate is opposite to that of the XNOR gate, on the basis of the ternary XNOR gate, without changing the overall circuit structure and wiring, only by swapping the positions of V Set0 and V Set2 , the ternary XOR gate circuit can be obtained. The values of V Init and V Run as well as V S1 -V S4 in the circuit are the same as those of the XNOR gate.

[0049] In the XOR gate circuit, it can be divided into the following nine cases according to different inputs:

[0050] (1) When the input is "(0, 0)", the input memristor M in1 = 1500 Ω, M in2 = 1500 Ω, corresponding voltage division V ab = 0.861 V, V bc = 0.689 V. V ab is higher than the threshold voltage V of S1 S1 , is higher than the threshold voltage V of S3 S3 , V bc is lower than the threshold voltage V of S2 S2 , is lower than the threshold voltage V of S4 S4 , at this time, switch S1 is on, S2 is off, S3 is on, S4 is off, V Set0 will set the output memristor M out to 1500 Ω, and the logic gate outputs logic "0".

[0051] (2) When the input is "(0, 1)", the input memristor M in1 = 1500 Ω, M in2 = 500 Ω, corresponding voltage division V ab = 0.596 V, V bc= 0.954V. V ab Higher than the threshold value V of S1 S1 , lower than the threshold value V of S3 S3 , V bc Lower than the threshold value V of S2 S2 , lower than the threshold value V of S4 S4 , at this time, switch S1 is turned on, S2 is turned off, S3 is turned off, S4 is turned off, and the output memristor M out Maintains the initial configuration unchanged, and the logic gate outputs logic "1".

[0052] (3) When the input is "(0, 2)", the input memristor M in1 = 1500Ω, M in2 = 100Ω, corresponding voltage division V ab = 0.209V, V bc = 1.341V. V ab Higher than the threshold value V of S1 S1 , lower than the threshold value V of S3 S3 , V bc Higher than the threshold value V of S2 S2 , lower than the threshold value V of S4 S4 , at this time, switch S1 is turned on, S2 is turned on, S3 is turned off, S4 is turned off, V Set2 Will set the output memristor M out To 100Ω, and the logic gate outputs logic "2".

[0053] (4) When the input is "(1, 0)", the input memristor M in1 = 500Ω, M in2 = 1500Ω, corresponding voltage division V ab = 0.596V, V bc = 0.954V. V ab Higher than the threshold value V of S1 S1 , lower than the threshold value V of S3 S3 , V bc Lower than the threshold value V of S2 S2 , lower than the threshold value V of S4 S4 , at this time, switch S1 is turned on, S2 is turned off, S3 is turned off, S4 is turned off, and the output memristor M out Maintains the initial configuration unchanged, and the logic gate outputs logic "1".

[0054] (5) When the input is "(1, 1)", the input memristor M in1 = 500Ω, M in2 = 500Ω, corresponding voltage division V ab = 0.456V, V bc = 1.094V. V ab Higher than the threshold value V of S1 S1, lower than the threshold value V of S3 S3 , V bc , lower than the threshold value V of S2 S2 , lower than the threshold value V of S4 S4 , at this time, switch S1 is turned on, S2 is turned off, S3 is turned off, S4 is turned off, and the output memristor M out maintains the initial configuration unchanged, and the logic gate outputs logic "1".

[0055] (6) When the input is "(1,2)", the input memristor M in1 = 500Ω, M in2 = 100Ω, corresponding voltage division V ab = 0.189V, V bc = 1.361V. V ab , lower than the threshold value V of S1 S1 , lower than the threshold value V of S3 S3 , V bc , higher than the threshold value V of S2 S2 , lower than the threshold value V of S4 S4 , at this time, switch S1 is turned off, S2 is turned on, S3 is turned off, S4 is turned off, and the output memristor M out maintains the initial configuration unchanged, and the logic gate outputs logic "1".

[0056] (7) When the input is "(2,0)", the input memristor M in1 = 100Ω, M in2 = 1500Ω, corresponding voltage division V ab = 0.209V, V bc = 1.341V. V ab , higher than the threshold value V of S1 S1 , lower than the threshold value V of S3 S3 , V bc , higher than the threshold value V of S2 S2 , lower than the threshold value V of S4 S4 , at this time, switch S1 is turned on, S2 is turned on, S3 is turned off, S4 is turned off, V Set2 will set the output memristor M out to 100Ω, and the logic gate outputs logic "2".

[0057] (8) When the input is "(2,1)", the input memristor M in1 = 100Ω, M in2 = 500Ω, corresponding voltage division V ab = 0.189V, V bc = 1.361V. V ab , lower than the threshold value V of S1 S1 , lower than the threshold value V of S3 S3 , V bc , higher than the threshold value V of S2S2 , lower than the threshold value V of S4 S4 , at this time, switch S1 is off, S2 is on, S3 is off, S4 is off, and the output memristor M out maintains the initial configuration unchanged, and the logic gate outputs logic "1".

[0058] When the input is "(2, 2)", the input memristor M in1 = 100Ω, M in2 = 100Ω, corresponding partial voltage V ab = 0.119V, V bc = 1.431V. V ab is lower than the threshold value V of S1 S1 and lower than the threshold value V of S3 S3 , V bc is higher than the threshold value V of S2 S2 and higher than the threshold value V of S4 S4 , at this time, switch S1 is off, S2 is on, S3 is off, S4 is on, V Set0 will set the output memristor M out to 1500Ω, and the logic gate outputs logic "0".

[0059] Those of ordinary skill in the art should recognize that the above embodiments are only used to verify the present invention and are not intended to limit the present invention. As long as it is within the scope of the present invention, changes and modifications to the above embodiments will fall within the protection scope of the present invention.

Claims

1. A XNOR gate circuit implemented based on a three - valued memristor, characterized in that, Including: Three memristors, namely two input memristors M in1 , M in2 and one output memristor M out ; Three voltage sources, namely V, V set0 and V set2 ; Four voltage-controlled switches, namely S1, S2, S3 and S4, and an auxiliary resistor R.

2. The XNOR gate circuit implemented based on a ternary memristor according to claim 1, wherein In the XOR gate circuit, the positive electrode of the voltage source V is connected to the positive electrodes of the two input memristors M in1 and M in2 , the positive electrodes of the voltage-controlled switches S1 and S3; the negative electrodes of the two input memristors M in1 and M in2 , the negative electrodes of the voltage-controlled switches S1 and S3, and the positive electrodes of the voltage-controlled switches S2 and S4 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the negative electrodes of the voltage-controlled switches S2 and S4, the negative electrode of the output memristor M out and the ground wire; the voltage-controlled switches S1 and S2 are in series, and the positive electrode of the voltage source V set0 is connected to the positive electrode of the output memristor M out through the voltage-controlled switches S1 and S2; the voltage-controlled switches S3 and S4 are in parallel, and the positive electrode of the voltage source V set2 is connected to the positive electrode of the output memristor M out through the voltage-controlled switches S3 and S4, and the negative electrodes of the voltage sources V, V set0 and V set2 are all connected to the ground wire.

3. The XNOR gate circuit implemented based on a ternary memristor according to claim 2, wherein The XNOR gate circuit input memristors adopt a parallel structure, and the output memristor M out has an initial state of R M ; The working process of the XNOR gate circuit is carried out in two stages, driven by the excitation voltage source V. The first stage is the initial stage, and V outputs the initial voltage V Init to obtain the initial resistance state of the memristor; The second stage is the operation stage, and V outputs the operation voltage V Run to complete the XNOR logic operation, and the operation voltage is greater than the initial voltage; Voltage source V set0 and V set2 are set voltage sources used to perform the reset and set-2 operations on the output memristor M out ; switches S1, S2, S3, and S4 are voltage-controlled switches that conduct only when the applied control voltage exceeds their threshold voltages.

4. The XNOR gate circuit implemented based on a ternary memristor according to claim 3, wherein The XNOR gate utilizes the parallel voltage division V in1 of the input memristors M in2 and M ab to control the conduction of the voltage-controlled switches S1 and S3. The voltage division V bc of the auxiliary resistor R controls the conduction of the voltage-controlled switches S2 and S4. Based on the voltage division of V ab and V bc , the threshold voltages V S1 , V S2 , V S3 and V S4 of the voltage-controlled switches S1, S2, S3 and S4 are determined to implement the XNOR logic operation.

5. A XOR gate circuit implemented based on a ternary memristor, characterized in that, It includes three memristors, namely two input memristors M in1 , M in2 and one output memristor M out ; three voltage sources are V, V set0 and V set2 ; four voltage-controlled switches S1, S2, S3 and S4; and an auxiliary resistor R; In the XOR gate circuit, the positive pole of the voltage source V is connected to the positive poles of two input memristors M in1 and M in2 , the positive poles of the voltage-controlled switches S1 and S3; the negative poles of the two input memristors M in1 and M in2 , the negative poles of the voltage-controlled switches S1 and S3, the positive poles of the voltage-controlled switches S2 and S4 are connected to the left end of the auxiliary resistor R; the right end of the auxiliary resistor R is connected to the negative poles of the voltage-controlled switches S2 and S4, the negative pole of the output memristor M out and the ground wire; the voltage-controlled switches S1 and S2 are in series, and the positive pole of the voltage source V set2 is connected to the positive pole of the output memristor M out through the voltage-controlled switches S1 and S2; the voltage-controlled switches S3 and S4 are in parallel, and the positive pole of the voltage source V set0 is connected to the positive pole of the output memristor M out through the voltage-controlled switches S3 and S4, and the negative poles of the voltage sources V, V set0 and V set2 are all connected to the ground wire.

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