Two-step ADC circuit based on automatic correction DCO, conversion method and application

Abstract

The invention discloses a two-step ADC circuit based on an automatic correction DCO, a conversion method and application. The method comprises the steps that the automatic correction DCO completes frequency correction of a coarse quantization clock and a fine quantization clock; the first step of the ADC is single-step M-bit SS ADC coarse quantization, the second step of the ADC is fine quantization, the fine quantization firstly extracts residual time through a residual time detection module, then a DCO is started through the residual time to generate a fine quantization clock to carry out N-bit time-digital quantization on the residual time, and the ADC with M + N-bit quantization precision is jointly realized through the two steps; the connection from coarse quantization to fine quantization ensures that the output fine quantization clock frequency of the DCO meets the frequency matching requirements of the two-step ADC system on the coarse quantization clock frequency and the fine quantization clock frequency through automatic correction. The circuit has the characteristics of small area, high sampling rate, high resolution, low power consumption, no need of global transmission of a high-frequency clock, limitation of action time of the high-frequency clock and the like, and is suitable for reading circuits of high-performance image sensors and infrared focal plane detectors.

Description

Technical Field

[0001] The present invention relates to an ADC circuit, and particularly to a two-step analog-to-digital convertor (ADC) circuit, a conversion method and an application based on an automatic correction digital controlled oscillator (DCO). Background Art

[0002] Image sensors usually use column-level analog-to-digital convertors (ADCs) for analog-to-digital quantization. Single-slope ADCs (SS ADCs) are widely used in image sensors. Each column uses a comparator and a counter, and the entire array shares a ramp signal generation circuit. The circuit is simple and occupies a small area, which is an ADC architecture suitable for array applications such as image sensors.

[0003] However, generally high-performance image sensors and infrared detectors have a high dynamic range, and the corresponding ADC accuracy of the readout circuit needs to reach more than 14 bits. With the continuous increase in the scale and frame rate of the image sensor array, the conversion speed requirement of the ADC is also constantly increasing. The conversion essence of the SS ADC is the conversion from the voltage domain to the time domain and then to the digital domain. In the SS ADC, 1 counting clock cycle represents the time resolution of the SS ADC. For an N-bit SS ADC, its conversion period is 2 N CLK clock cycles. To increase the sampling rate, the counting clock frequency must be increased, that is, the time resolution is increased. Therefore, a high-frequency clock is required for counting. In the column-level digital readout circuit of the image sensor, the SS ADCs are arranged on the array, and the high-frequency clock needs to be sent to the column-level SS ADCs of the entire array for use. The high-frequency clock will not only introduce large power consumption, but also pose a great challenge to ensure its transmission quality. For example, for a traditional 14-bit SS ADC with a sampling rate of 100 kS / s, a counting clock signal with a frequency as high as 1.64 GHz is required to meet the requirement, and the transmission of the 1.64 GHz clock is a huge problem.

[0004] Since the single-step SS ADC is limited by the counting clock frequency, some research has proposed a two-step (M+N)-bit SS ADC scheme with a coarse clock and a fine clock, such as Figure 1 the two-step coarse and fine clock shown. The coarse clock f MSB_CLK with a low frequency is used for the first-step coarse quantization to control the counting of the high-order most significant bits (MSBs) of M bits; the fine clock with a high frequency f LSB_CLK is used for the second-step fine quantization to control the counting of the low-order least significant bits (LSBs) of N bits. There is a strict frequency relationship between the coarse and fine clocks of this two-step ADC to meet the system requirements of the two-step ADC, as shown in Equation (1):

[0005] f LSB_CLK = 2 N × f MSB_CLK (1)

[0006] Then the quantization results of the two-step coarse and fine clocks are combined as shown in Equation (2):

[0007] D OUT = MSB_CNT × 2 N + LSB_CNT (2)

[0008] Figure 1 For the comparator's flip time t1, the time from the comparison flip moment t1 to the rising edge t2 of the next coarse quantization clock MSB_CLK can be detected, and this residual time Residue time is denoted as t residue , and this section of residual time t is counted and quantized using the fine quantization clock LSB_CLK residue . Since Residue time is the part that is overcounted in this MSB, the final voltage-to-time conversion can be represented by subtracting this residual time Residue time from the counting duration MSB COUNT time of the MSB, as shown in Equation (3):

[0009] t1 = MSB COUNT time - t residue (3)

[0010] Converting the time domain to the digital domain is represented by Equation (4):

[0011] D OUT = MSB_CNT × 2 N - LSB_CNT (4)

[0012] By adopting the method of this two-step ADC, the conversion rate of the ADC can be greatly improved. From the above working principle, for a single-step SS ADC with (M + N) bits, the quantization time is as shown in Equation (5):

[0013] TIME conversion = 2 (M+N) × SS_CLK (5)

[0014] For a two-step coarse and fine clock with (M + N) bits, the quantization time is only as shown in Equation (6):

[0015] TIME conversion = 2 (M) × MSB_CLK (6)

[0016] For example, if M = 9 and N = 5, and the coarsely quantized clock MSB_CLK is designed to be 50 MHz, then the finely quantized clock LSB_CLK is 1.6 GHz. Compared with the single-step SS ADC, the sampling rate of the two-step coarse-fine clock ADC is greatly improved. Moreover, the reduction of the frequency of the coarsely quantized clock MSB_CLK will greatly reduce the power consumption of the counter and transmission lines. However, it is very difficult to send the finely quantized clock LSB_CLK with such a high frequency of 1.6 GHz to the entire array, and it will introduce huge power consumption. In addition, it is very difficult to fully match the frequency relationship between the coarsely quantized clock MSB_CLK and the finely quantized clock LSB_CLK under the influence of the parasitic RC introduced by the large array routing. Therefore, it is difficult to implement the transmission of the high-frequency clock finely quantized clock LSB_CLK in this two-step coarse-fine clock ADC. Moreover, more seriously, errors will be introduced during the coarsely quantized residual time and the fine quantization process, which will cause problems such as missing codes or duplicate codes in the ADC, and will seriously affect the imaging quality of the image sensor. Summary of the Invention

[0017] The purpose of the present invention is to overcome the clock matching problems of the single-step column-level SS ADC and the two-step coarse-fine clock ADC, and at the same time overcome their application limitations in the area array image sensor. A two-step ADC circuit and conversion method based on an automatic calibration DCO are provided. This circuit has the characteristics of small area, high sampling rate, high resolution, low power consumption, no need for global transmission of high-frequency clocks, and limited action time of high-frequency clocks. The DCO adopted has an automatic calibration function. The digital calibration scheme has no static power consumption, is non-volatile, the calibration parameters can be stored, and it has a small area. Through the DCO calibration, the strict frequency matching requirements of the two-step ADC system can be met, ensuring the linearity of the two-step ADC, and it is suitable for application in high-performance image sensors and infrared focal plane detector readout circuits.

[0018] According to the first aspect, the technical solution adopted by the present invention is as follows:

[0019] An M-bit ramp generator module for generating a ramp voltage V required for ADC quantization. RAMP The ramp voltage V ramp has a range of [V L , V H , and this V ramp signal is connected to the positive input terminal of the comparator module.

[0020] A comparator module for comparing the magnitudes of the analog signal V in and the ramp voltage V RAMP , and HIT is the output of the comparator;

[0021] An M-bit counter module for quantization counting and storage during the first-step M-bit coarse quantization;

[0022] A residual time detection module, which is used to detect the residual time LSB_EN between the flip moment of the comparator of the SS ADC and the rising edge of the next coarse quantization clock MSB_CLK after the output HIT of the comparator of the SS ADC flips during the first-step coarse quantization;

[0023] An N-bit DCO and automatic calibration module includes a ring oscillator composed of 1 NAND gate and 4 NOT gates connected end to end, 1 N-bit ADC counter (used for counting during the fine quantization of the ADC), 1 N-bit calibration counter (operating in the calibration mode), 1 DFF, 1 AND gate, 1 Z-bit calibration counter, and a Z-bit binary weighted switched capacitor connected thereto in a matching manner. It is used to meet the frequency requirements of the two-step ADC during the automatic calibration stage, complete frequency calibration, so that the coarse quantization clock frequency f MSB_CLK and the fine quantization clock frequency f LSB_CLK meet f LSB_CLK = f MSB_CLK ×2 N and save the corresponding calibration parameters in the register; when the residual time LSB_EN effectively enables the ring oscillator during the second-step fine quantization of the ADC, the fine quantization clock LSB_CLK is generated locally, so that there is no need to transmit the high-frequency fine quantization clock LSB_CLK within the entire array, and the ring oscillator is only turned on within the residual time LSB_EN, and the operating time of the ring oscillator is very short, thus greatly saving power consumption.

[0024] The connection relationship and interaction of each module are as follows:

[0025] V in is the input analog voltage, ADC_EN is the ADC quantization enable signal, MSB_CLK is the working clock of the coarse quantization SS ADC, and the ramp voltage V ramp is generated by an M-bit V ramp ramp generator module

[0026] The positive input terminal of the comparator module is connected to the ramp voltage V ramp , the negative input terminal is connected to the input signal V in , and the comparison output is the HIT signal. When the ramp voltage V ramp is greater than the input signal V in , the output HIT signal of the comparator is 1; when the ramp voltage V ramp is less than the input signal V inWhen the output HIT signal of the comparator is 0. The output HIT signal of the comparator and the quantization enable ADC_EN generate the coarse quantization enable MSB_EN signal through an AND gate. On the one hand, the coarse quantization enable MSB_EN is used to control the M-bit counter, which controls the counter to count according to the clock MSB_CLK and outputs the coarse quantization digital code MSB_DOUT <m:1>; On the other hand, the coarse quantization enables the MSB_EN signal to be connected to the residual time detection module. The residual time detection module detects the residual time LSB_EN pulse signal of the coarse quantization enable MSB_EN signal to the next coarse quantization clock MSB_CLK. The residual time LSB_EN signal is connected to the N-bit DCO automatic correction module;

[0027] The N-bit DCO and the automatic correction module include a ring oscillator composed of 1 NAND gate and 4 NOT gates connected end to end, 1 N-bit ADC counter (used for ADC counting in the fine quantization stage), 1 N-bit correction counter (operating in the correction mode), 1 DFF and 1 AND gate, 1 Z-bit correction counter, and the Z-bit binary weighted switched capacitors C0, C1,..., C z-1 . The switched capacitor array adopts a binary weighted capacitor array, that is, the capacitance value of each bit satisfies C i = 2 i C0, i ∈ [0, Z - 1]. The connection method of the Z-bit switched capacitor array is as follows: the lower plate of capacitor C0 is grounded, and the upper plate is connected to one end of switch S0. The on / off of switch S0 is controlled by signal CAL_Q<0>; the lower plate of capacitor C1 is grounded, and the upper plate is connected to one end of switch S1. The on / off of switch S1 is controlled by signal CAL_Q<1>; and so on. The lower plate of capacitor C z-1 is grounded, and the upper plate is connected to one end of switch S z-1 . The on / off of switch S z-1 is controlled by signal CAL_Q <z-1>Control; switches S0, S1, …, S of the control capacitor array used z-1 The other ends of the capacitors not connected are connected together and used as the total capacitive load CAP_LOAD and are connected to the output node of a certain NOT gate stage in the ring oscillator circuit. The start of the DCO ring oscillator is controlled by the calibration enable CAL_EN or the least significant bit enable of the residual time LSB_EN. When the calibration enable CAL_EN is valid, it enters the automatic calibration mode. When the least significant bit enable of the residual time LSB_EN is valid, it enters the quantization mode of the second step of the residual time of the two-step ADC. Once the ring oscillator is started, it will generate the fine quantization clock LSB_CLK. On the one hand, the fine quantization clock LSB_CLK clock signal is connected to the N-bit ADC counter to generate the fine quantization digital code LSB_DOUT <n:1>; On the other hand, the finely quantized clock LSB_CLK clock signal is connected to an N-bit counter for correction. When the counter is full, an OVER_FLOW signal pulse is generated. The input of the Z-bit counter for correction is the OVER_FLOW signal of the N-bit counter for correction. This counter counts based on the rising edge of the OVER_FLOW pulse, and the output count result is CAL_Q <z-1:0>。Z-bit CAL_Q <z:1>The signal feedback is connected to the Z-bit capacitor array switches S0, S1, …, S z-1 , which is used to control the connection of the switch array. By controlling the number of capacitors connected to the ring oscillator, the frequency of the fine quantization clock LSB_CLK is adjusted, and the calibration parameters are saved in CAL_Q after the calibration is completed <z-1:0>In.

[0028] RST is a reset signal, connected to the N-bit ADC counter, the N-bit correction counter, the Z-bit correction counter, and the DFF for global reset.

[0029] The residual time detection module, after the coarse quantization ends, outputs the residual time pulse width residual time LSB_EN. During the high level validity period of the residual time LSB_EN, it turns on the ring oscillator to generate the fine quantization clock LSB_CLK, and completes the time-to-digital quantization of the residual time through the N-bit ADC counter, and outputs the fine quantization digital code LSB_DOUT <n:1>;

[0030] Finally, the output data of this ADC, which is (M + N) bits, is the coarsely quantized digital code MSB_DOUT <m:1>And the quantized digital code LSB_DOUT <n:1>Jointly combined (M+N)-bit data DOUT[M+N:1].

[0031] According to a second aspect, the technical solution adopted by the present invention is as follows:

[0032] A two-step analog-to-digital convertor (ADC) circuit and conversion method based on an automatically calibrated digital controlled oscillator (DCO), comprising the following steps:

[0033] Step 1, the DCO starts automatic digital calibration, and the method includes:

[0034] Step 1.1, the reset signal RST is invalid, the CAL_FLAG signal is valid, the coarse quantization clock MSB_CLK passes through the DFF and the CAL_FLAG signal, and a calibration enable CAL_EN for controlling the automatic calibration mode is generated. The high-level pulse of the calibration enable CAL_EN signal is one clock cycle of the coarse quantization working clock MSB_CLK. When the calibration enable CAL_EN is at a high level, the ring oscillator in the DCO module is started to generate the fine quantization clock LSB_CLK, so that the N-bit calibration counter starts to count within one clock cycle of the coarse quantization clock MSB_CLK according to the fine quantization clock LSB_CLK;

[0035] Step 1.2, CAL_Q <z-1:0>The signal is connected to the switched-capacitor load corresponding to the respective Z bit. The CAL_Q<0> signal controls whether the capacitor of the 0th bit is connected to the ring oscillator, the CAL_Q<1> signal controls whether the capacitor of the 1st bit is connected to the load of the ring oscillator, and so on. CAL_Q <z-1>The signal controls whether the (Z-1)-th bit capacitor is connected to the ring oscillator;

[0036] Step 1.3, if f LSB_CLK > f MSB_CLK ×2 N , then the N-bit correction counter counts up in one coarse quantization clock MSB_CLK and an overflow signal OVER_FLOW is generated. The rising edge of an overflow signal OVER_FLOW increments the count value of the Z-bit correction counter, and the counting result CAL_Q of this counter <z-1:0>Adding 1 will increase the total capacitive load CAP_LOAD node by the capacitance value of one unit capacitor, thereby reducing the f of the ring oscillator LSB_CLK frequency; In the second cycle, if f LSB_CLK > f MSB_CLK × 2 N , then an overflow signal OVER_FLOW will be generated by the N-bit correction counter in one coarse quantization clock MSB_CLK, and the counting result CAL_Q <z-1:0>If we add 1, then the total capacitive load at the CAP_LOAD node will increase by one unit capacitance again, which reduces the frequency f of the ring oscillator once more. This process repeats until f LSB_CLK reaches f LSB_CLK = f MSB_CLK × 2 N . At this point, the N-bit correction counter in one coarse quantization clock MSB_CLK will no longer generate an overflow signal OVER_FLOW. Therefore, CAL_Q <z-1:0>The count value remains unchanged, i.e., the total capacitance load CAP_LOAD node remains unchanged;

[0037] In step 1.4, when the CAL_FLAG signal is equal to 0, the calibration mode ends, and the calibration result CAL_Q that satisfies f LSB_CLK = f MSB_CLK ×2 N is obtained. <z-1:0>Stored in the Z - bit correction counter and used when performing two - step ADC quantization;

[0038] Step 2: The two - step ADC starts quantization. First, perform M - bit coarse quantization, and the process includes:

[0039] Step 2.1: Enable the quantization - enabled ADC_EN, enable the ramp - enabled RAMP_EN signal, the ramp generator starts integration, and the ramp voltage V ramp discharges from the high reference voltage V H while the input voltage V in should be within the voltage range of the ramp voltage V ramp in the voltage range [V L , V H ;

[0040] Step 2.2: When the ramp voltage V ramp is higher than the input signal V in the output HIT signal of the comparator is 1, the generated coarse - quantization - enabled MSB_EN is valid at 1, the M - bit counter for coarse quantization starts counting with the coarse - quantization clock MSB_CLK, and the coarse - quantization digital code MSB_DOUT is generated <m:1>;

[0041] Step 2.3, when the ramp voltage V ramp is lower than the input voltage V in the output HIT signal of the comparator flips from 1 to 0, the coarse quantization enable MSB_EN is 0, the coarse quantization counter stops counting, and the count value is the coarse quantization digital code MSB_DOUT <m:1>;

[0042] Step 3, after the output HIT signal of the comparator flips from 1 to 0, the M-bit coarse quantization ends, and the ADC enters the N-bit fine quantization process, including:

[0043] Step 3.1, the coarse quantization enable MSB_EN signal and the coarse quantization working clock MSB_CLK signal pass through the residual time detection module, and the residual time LSB_EN is output;

[0044] Step 3.2, the DCO is enabled during the high level of the residual time LSB_EN. Since the DCO has corrected the frequency f of the coarse quantization clock MSB_CLK and the frequency f of the fine quantization clock LSB_CLK during the calibration phase to satisfy f LSB_CLK = f MSB_CLK ×2 N , the fine quantization clock LSB_CLK generated by the DCO meets the system requirements of the two-step ADC. During the high level of the residual time, the N-bit ADC counter counts according to the fine quantization clock LSB_CLK. When the residual time LSB_EN becomes 0, the N-bit ADC counter stops counting and outputs the fine quantization digital code LSB_DOUT <n:1>;

[0045] Step 4, the process of combining coarse quantization and fine quantization, including:

[0046] Combining the coarse quantization digital code MSB_DOUT <m:1>With the fine quantization digital code LSB_DOUT <n:1>Combined into the final quantization value DOUT<M+N:1>, which has a total of (M+N) bits, where:

[0047] DOUT[M+N:1] =

[0048] {MSB_DOUT[M],…,MSB_DOUT[1],LSB_DOUT[N],…,LSB_DOUT[1]}(1)

[0049] In Equation (1): DOUT<M+N:1> is the quantization result of the final output of this two-step ADC, with a total of (M+N) bits, where the high M bits are the coarse quantization digital code MSB_DOUT <m:1>, the lower N bits are the finely quantized digital code LSB_DOUT <n:1>。

[0050] Further, in the fine quantization of step 2, an M-bit ramp voltage V ramp is adopted. When this two-step ADC starts to work, the ramp voltage V ramp starts from the high reference voltage V H and is integrated to the low reference voltage V M after the time of 2 L coarse quantization clock MSB_CLK, and is reset to the high reference voltage V H after the quantization of the entire two-step ADC is completed.

[0051] Further, all two-step ADCs in the entire readout circuit array share a ramp voltage V ramp , which is generated by the M-bit ramp generator module.

[0052] According to the third aspect, in the application of the two-step ADC circuit based on automatic calibration DCO in a high-performance image sensor and a readout circuit of an infrared focal plane detector, all two-step ADCs in the entire readout circuit array share a ramp voltage V ramp , which is generated by the M-bit ramp generator module.

[0053] The principle of the present invention is as follows:

[0054] The two-step analog-to-digital converter circuit based on automatic calibration DCO of the present invention adopts a two-step ADC structure. The key is to use a digitally controlled ring oscillator for automatic coarse and fine clock frequency calibration to solve the frequency requirements of the two-step ADC. The first-step coarse quantization uses a single-step SS ADC. In the second-step fine quantization, the residual time LSB_EN is first extracted by the residual time detection module, and then the DCO is enabled by the residual time LSB_EN to generate the fine quantization clock LSB_CLK to count and quantify the residual time. In the connection from coarse quantization to fine quantization, the correction circuit ensures that the frequency f LSB_CLK of the fine quantization clock LSB_CLK generated by the DCO and the frequency f MSB_CLK of the externally input coarse quantization clock MSB_CLK meet the frequency matching requirements of the two-step ADC system.

[0055] The DCO with automatic calibration in the two-step structure is a digitally controlled local ring oscillator. First, it solves the problem of generating a highly quantized clock LSB_CLK for high-frequency operation, achieving high time resolution and addressing the issues of high power consumption and difficult transmission in high-frequency time-domain full-array transmission. Second, during a single analog-to-digital conversion process, the ring oscillator is only turned on during the high-level time of the residual time LSB_EN, significantly saving power. Third, crucially, the automatically calibrated DCO uses digital control to calibrate the ring oscillator, and calibration can be performed before each ADC operation, or once per frame, or at any time in the background. Its calibration parameters are stored inside the counter and are non-volatile. The automatic calibration ensures that the frequency f LSB_CLK of the highly quantized clock LSB_CLK generated by the DCO and the frequency f MSB_CLK of the coarsely quantized clock MSB_CLK meet the frequency requirements of the two-step ADC system: f LSB_CLK = f MSB_CLK ×2 N , ensuring the carry connection requirements for the M-bit coarsely quantized SS ADC and the N-bit fine quantization of the residual time in the two-step structure. Ultimately, the two steps together achieve the analog-to-digital conversion function with (M + N)-bit quantization accuracy.

[0056] First, during the coarse quantization stage, the voltage is converted into a counting duration through the principle of the SS ADC, and then coarse quantization counting is performed using the coarsely quantized clock MSB_CLK. The minimum voltage resolution V MSB in the first-step coarse quantization SS ADC is as shown in Equation (8), and the time resolution t MSB of the coarse quantization is as shown in Equation (9):

[0057]

[0058] In the formula:

[0059] V H is the high voltage of the reference voltage of the ramp voltage generator, V L is the low voltage of the reference voltage of the ramp voltage generator. The ramp voltage V ramp is generated by the ramp generator, and the range of the ramp voltage V ramp is [V L , V H . Therefore, the range of the quantifiable input analog voltage V in is [V L , V H .

[0060] After the first-step SS ADC coarse quantization conversion, the residual time t MSB that cannot be quantified by the first-step time resolution t residue It will be quantized in the second step. After the comparator flips, the residual time detection module outputs the residual time LSB_EN pulse width that cannot be quantized in the first step. Fine quantization will complete the conversion of the residual time to a digital code: the residual time LSB_EN pulse width controls the turn-on and turn-off of the DCO. During the high-level time of the residual time LSB_EN, the DCO is turned on to generate the fine quantization clock LSB_CLK. During the pulse width of the residual time LSB_EN, the N-bit ADC counter starts counting according to the fine quantization clock LSB_CLK and outputs LSB_DOUT <n:1>, when the remaining time LSB_EN becomes low, the N-bit ADC counter stops counting, completing the fine quantization process. The two-step conversion together completes an (M+N)-bit ADC, and its V LSB is

[0061]

[0062] V LSB is the minimum resolvable voltage in the second-step fine quantization stage, and the equivalent time resolution of the second step is t LSB , as shown in Equation (11)

[0063]

[0064] The present invention is a two-step method for time-to-digital quantization of the remaining time LSB_EN after the end of coarse quantization using a fine quantization clock LSB_CLK generated based on a DCO. The DCO with automatic calibration in the present invention locally generates a high-frequency fine quantization clock LSB_CLK, and the frequency f LSB_CLK of the coarse quantization clock LSB_CLK is guaranteed by the DCO, and the corrected frequency satisfies Equation (12)

[0065] f LSB_CLK = f MSB_CLK × 2 N (12)

[0066] During automatic calibration, the frequency of the output fine quantization clock LSB_CLK is changed by controlling the capacitive load connected to the DCO through cyclic iteration. CAL_Q <z-1:0>The signal is connected to the switched-capacitor load of the corresponding Z bit. The CAL_Q<0> signal controls whether the capacitor C0 of the 0th bit is connected to the ring oscillator. The CAL_Q<1> signal controls whether the capacitor C1 of the 1st bit is connected to the load of the ring oscillator, and so on. CAL_Q <z-1>Signal controls the Z-1st bit capacitor C Z-1 Whether to connect to the ring oscillator

[0067] If f LSB_CLK >f MSB_CLK ×2 N , then the N-bit correction counter in one coarse quantization clock MSB_CLK will count up, generating an overflow signal OVER_FLOW signal. One pulse edge of the OVER_FLOW signal causes the count value of the Z-bit correction counter to increase by 1, and the counting result CAL_Q of this counter <z-1:0>If we add 1, then the total capacitive load at the CAP_LOAD node will increase by the capacitance value of one unit capacitor, thereby reducing the frequency f of the ring oscillator. LSB_CLK In the second cycle, if f LSB_CLK > f MSB_CLK × 2 N , then an overflow signal OVER_FLOW will be generated by the N-bit counter in one coarse quantization clock MSB_CLK, and the counting result CAL_Q <z-1:0>Adding 1, then the total capacitive load CAP_LOAD node will add one more unit capacitance, and the frequency of the ring oscillator will be reduced again. This process repeats until in one cycle of the coarsely quantized clock MSB_CLK, the N-bit counter no longer generates the overflow signal OVER_FLOW, then CAL_Q LSB_CLK frequency, and so on, until when in one cycle of the coarsely quantized clock MSB_CLK, the N-bit counter no longer generates the overflow signal OVER_FLOW, then CAL_Q <z-1:0>The count value remains unchanged, i.e., the calibration satisfies f LSB_CLK = f MSB_CLK × 2 N , at this time, the frequency calibration is completed, and the calibration parameters are directly stored in CAL_Q <z-1:0>In

[0068] The ring oscillator in the designed DCO is affected by process, voltage, and temperature (PVT) conditions. Since the operating temperature of the infrared image sensor is determined, and the ring array voltage can be provided by a high-precision LDO. Finally, considering factors such as process corners during design, by designing an appropriate ring oscillator size, the LSB_CLK determined frequency range can be ensured.

[0069] In the present invention, the local ring oscillator provides the high-frequency clock required for the second-step digital conversion of the residual time, solving the difficulty of high-frequency clock transmission along the surface array; the key DCO automatic correction scheme of the present invention automatically corrects the frequency of the ring oscillator, solving the matching requirement between the two-step coarse clock coarse quantization clock frequency f MSB_CLK and the fine clock fine quantization clock frequency f LSB_CLK After the correction is completed, it satisfies f LSB_CLK = f MSB_CLK ×2 N , meeting the system matching requirements of two-step quantization, and this correction function can be set to background automatic correction, or external command correction, etc.

[0070] The beneficial effects of the present invention are:

[0071] (1) The digital control automatic correction scheme adopted by the DCO of the two-step analog-to-digital converter based on the automatic correction DCO generates a high-frequency fine quantization clock LSB_CLK locally. The automatic correction corrects the frequency

[0072] f LSB_CLK of the fine quantization clock LSB_CLK to 2 MSB_CLK times the frequency f N of the coarse quantization clock MSB_CLK, that is: f LSB_CLK =

[0073] f MSB_CLK ×2 N . Automatically complete digital correction internally, meeting the frequency requirements of the two-step ADC system. This correction module enables the two-step ADC to work properly and the two steps to be correctly connected. The differential nonlinearity (DNL) of this ADC can be controlled within ±1 LSB, which can significantly improve the image quality of the sensor imaging system. This DCO correction method can be corrected in the background, can be corrected every frame time, or every line time. The correction parameters have the characteristics of non-volatility and easy storage;

[0074] (2) The DCO in the two-step analog-to-digital converter based on automatic calibration DCO locally generates a high-frequency fine quantization clock LSB_CLK, which not only overcomes the high power consumption introduced by the high-frequency clock in the full-array transmission of the image sensor, but also avoids the difficulty of high-speed clock layout and wiring, greatly reducing the power consumption overhead and being beneficial to the low-power application of large-area array sensors;

[0075] (3) The high-frequency clock fine quantization clock LSB_CLK required in the second-step fine quantization of the two-step analog-to-digital converter based on automatic calibration DCO is only turned on during the effective time of the short residual time LSB_EN in one conversion, reducing the power consumption of the ADC, greatly reducing the power consumption overhead, and being beneficial to the low-power application of large-area array sensors;

[0076] (4) The two-step analog-to-digital converter based on automatic calibration DCO adopts a two-step structure, reducing the conversion time of a single-step high-precision SS ADC with the same number of bits, greatly improving the conversion speed and reducing the power consumption. This two-step ADC reduces the 2 (M+N) MSB_CLK clock cycles of a single-step SS ADC to 2 M coarse quantization clock MSB_CLK clock cycles, which can greatly improve the conversion speed and reduce the power consumption, and is suitable for high-speed sensor applications;

[0077] (5) The two-step analog-to-digital converter based on automatic calibration DCO can achieve the functions of a high-precision (more than 14 bits), high sampling rate (100 kSps), and low-power analog-to-digital converter, and is suitable for application in large-area array image sensors and infrared detectors. It provides flexibility in the selection of the number of bits for the two steps. By appropriately selecting the number of coarse quantization bits M and the number of fine quantization bits N, different sensor imaging system requirements can be met. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] Figure 1 is the principle of the two-step SS ADC with coarse and fine clocks.

[0079] Figure 2 is the circuit schematic diagram of the two-step analog-to-digital converter based on automatic calibration DCO of the present invention.

[0080] Figure 3 is the working timing diagram of the two-step analog-to-digital converter based on automatic calibration DCO of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0081] The following further describes the present invention in detail through embodiments with reference to the accompanying drawings, but the protection scope of the present invention is not limited to the following embodiments.

[0082] As Figure 2 As shown, a two-step analog-to-digital converter circuit based on an automatic calibration DCO of the present invention includes:

[0083] M-bit V ramp ramp generator module; comparator module; M-bit counter module; residual time detection module; N-bit DCO and automatic calibration module. Among them: The V ramp signal is generated by a ramp generator circuit, and the ramp voltage V ramp has a range of [V L , V H , and this ramp voltage V ramp signal is connected to the positive input terminal of the comparator module. V in is the input analog voltage, ADC_EN is the enable signal for the ADC to start quantization, the coarse quantization clock MSB_CLK is the working clock of the coarse quantization SS ADC, the ramp voltage V ramp is generated by the M-bit ramp generator module, and the ramp voltage V ramp and the input signal V in are respectively connected to the positive and negative terminals of the comparator. The positive input terminal of the comparator module is connected to V ramp , the negative input terminal is connected to the input signal V in , and the output of the comparator is the HIT signal. When the ramp voltage V ramp is greater than the input signal V in , the output HIT signal of the comparator is 1, and when V ramp is less than V in , the output HIT signal of the comparator module is 0. The HIT signal and the enable signal ADC_EN generate the coarse quantization enable MSB_EN signal. On the one hand, the coarse quantization enable MSB_EN is used to control the M-bit counter, control the counter to count according to the coarse quantization clock MSB_CLK, and generate the coarse quantization digital code MSB_DOUT <m:1>On the other hand, the coarse quantization enables the MSB_EN signal to be connected to the residual time detection module. The residual time detection module detects the residual time LSB_EN of the coarse quantization enable MSB_EN signal to the coarse quantization clock MSB_CLK. The residual time LSB_EN signal is input into the N-bit DCO and automatic correction module;

[0084] The N-bit DCO and automatic correction module includes a ring oscillator composed of 1 NAND gate and 4 NOT gates connected end to end, 1 N-bit ADC counter (used for counting during fine quantization of the ADC), 1 N-bit counter for correction (used in the correction mode), 1 DFF and 1 AND gate, 1 Z-bit counter for correction, and a Z-bit binary weighted switched capacitor array matched and connected thereto. This switched capacitor array is a binary weighted capacitor array C0, C1, … C z-1 , that is, the capacitance value of each bit satisfies C i = 2 i C0, i ∈ [0, Z - 1]. The connection method of the Z-bit switched capacitor array is as follows: the lower plate of capacitor C0 is grounded, and the upper plate is connected to one end of switch S0. The on / off of switch S0 is controlled by signal CAL_Q<0>; the lower plate of capacitor C1 is grounded, and the upper plate is connected to one end of switch S1. The on / off of switch S1 is controlled by signal CAL_Q<1>; and so on. The lower plate of capacitor C z is grounded, and the upper plate is connected to switch S z-1 at one end. The on / off of switch S z-1 is controlled by signal CAL_Q <z-1>Control; S 0， S1,..,S z-1 One end of the switch that is not connected is connected together and used as CAP_LOAD to access the output node of a certain NOT gate in the ring oscillator circuit.

[0085] The start of the DCO ring oscillator is controlled by the calibration enable CAL_EN or the least significant bit enable LSB_EN of the residual time. When the calibration enable CAL_EN is valid, the ring oscillator is turned on to generate the finely quantized clock LSB_CLK. On the one hand, the finely quantized clock LSB_CLK signal is connected to the N-bit ADC counter to generate the finely quantized digital code LSB_DOUT. <n:1>; On the other hand, the finely quantized clock LSB_CLK clock signal is connected to an N-bit counter for correction to generate an overflow signal OVER_FLOW signal. The input of the Z-bit counter for correction is the OVER_FLOW signal. This counter counts based on the rising edge of the OVER_FLOW pulse and outputs the counting result as CAL_Q <z-1:0>。Z-bit CAL_Q <z:1>The signal feedback is connected to the Z-bit capacitor array switches S0, S1, …, S z-1 , and the frequency of the fine-quantized clock LSB_CLK is adjusted by controlling the number of capacitors connected to the ring oscillator, and it is stored in CAL_Q after the calibration is completed <z-1:0>In.

[0086] RST is a reset signal, connected to the N-bit ADC counter, the N-bit correction counter, the Z-bit correction counter, and the DFF for global reset.

[0087] The residual time detection module outputs a residual time pulse width LSB_EN after the coarse quantization. During the high level validity of the residual time LSB_EN, the ring oscillator is enabled to generate a fine quantization clock LSB_CLK, which is sent to the N-bit ADC counter for counting, and a fine quantization digital code LSB_DOUT is output. <n:1>; Finally, the output data of this ADC, which is (M+N) bits, is the coarsely quantized digital code MSB_DOUT <m:1>And the fine quantization digital code LSB_DOUT <n:1>Commonly merged (M+N)-bit data DOUT[M+N:1].

[0088] As Figure 3 shown, the working timing diagram process of a conversion method of a two-step analog-to-digital converter based on automatic calibration DCO according to the present invention is as follows:

[0089] (1) The DCO starts automatic digital calibration, and the process of automatic calibration is as follows:

[0090] a) The RST reset signal is invalid, the CAL_FLAG signal is valid, the coarse quantization clock MSB_CLK passes through the DFF and then passes through the AND gate with the CAL_FLAG signal to generate a calibration enable CAL_EN signal for controlling the automatic calibration mode. The high-level pulse of the calibration enable CAL_EN signal is one coarse quantization clock MSB_CLK cycle. When the calibration enable CAL_EN is at a high level, the ring oscillator in the DCO module is started to generate a fine quantization clock LSB_CLK, so that the N-bit calibration counter starts to count within one coarse quantization clock MSB_CLK cycle according to the fine quantization clock LSB_CLK;

[0091] b) Figure 3 The Z-bit calibration counter exemplified in is 6 bits (Z = 6), and its output CAL_Q<5:0> signal is connected to the corresponding 6-bit switched-capacitor load. The CAL_Q<0> signal controls whether the capacitor of the 0th bit is connected to the ring oscillator. The CAL_Q<1> signal controls whether the capacitor C0 of the 1st bit is connected to the CAP_LOAD capacitor load of the ring oscillator, and so on. The CAL_Q<5> signal controls whether the capacitor C5 of the 5th bit is connected to the CAP_LOAD capacitor load of the ring oscillator.

[0092] c) The coarse quantization clock MSB_CLK is sent from the outside, and the frequency is f MSB_CLK . The frequency f LSB_CLK of the fine quantization clock LSB_CLK is generated by the ring oscillator in the DCO. At the beginning of calibration, CAL_Q<5:0> is 0, so the CAP_LOAD capacitor load connected to the DCO loop is 0. If f LSB_CLK >f MSB_CLK ×2 N , then in one coarse quantization clock MSB_CLK, the N-bit calibration counter will generate an overflow signal OVER_FLOW. One pulse edge of the OVER_FLOW signal causes the count value of the Z-bit calibration counter to increase by 1, that is, the count result CAL_Q<5:0> increases by 1. Then the total CAP_LOAD capacitor load node will increase the capacitance value of one unit capacitor, thereby reducing the frequency f LSB_CLK of the fine quantization clock generated by the ring oscillator; in the second cycle, if f LSB_CLK >f MSB_CLK ×2 N , an overflow signal OVER_FLOW will be generated by the N-bit correction counter in a coarse quantization clock MSB_CLK, and the count result CAL_Q<5:0> is incremented by 1. Then, an additional unit capacitance is added to the total capacitance load CAP_LOAD node, which reduces the frequency f of the ring oscillator again. This process repeats until f LSB_CLK frequency meets the requirement. This cycle continues until f LSB_CLK = f MSB_CLK ×2 N . At this point, the N-bit correction counter in a coarse quantization clock MSB_CLK no longer generates an overflow signal OVER_FLOW, and the count value of CAL_Q<5:0> remains unchanged. In the figure, the calibration result is CAL_Q<5:0> = 001100, and this calibration parameter is stored in the counter for use in the subsequent two-step ADC quantization.

[0093] (2) The two-step ADC starts quantization, and the process is as follows:

[0094] a) First, perform M-bit coarse quantization. The quantization enable ADC_EN signal is valid, the RAMP_EN signal is valid, and the ramp generator starts to integrate. The ramp voltage V ramp signal discharges from V H . The input signal V in range should be included in the voltage range [V ramp , V L , V H of the ramp voltage V

[0095] b) Initially, when the ramp voltage V ramp is higher than the input signal V in voltage, the generated coarse quantization enable MSB_EN is valid with a value of 1. The M-bit counter for coarse quantization starts counting with the coarse quantization clock MSB_CLK to generate the coarse quantization digital code MSB_DOUT <m:1>; When the ramp voltage V ramp is lower than the input signal V in , the output HIT signal of the comparator flips from 1 to 0, the coarse quantization enable MSB_EN is 0, the coarse quantization M-bit counter stops counting, and the coarse quantization digital code MSB_DOUT <m:1>The value remains unchanged.

[0096] c) After the output HIT signal of the comparator flips from 1 to 0, the M-bit coarse quantization ends, and the ADC enters the N-bit fine quantization. The coarse quantization enable MSB_EN and the coarse quantization clock MSB_CLK pass through the residual time detection module, and the residual time LSB_EN is output.

[0097] d) Since the DCO has corrected the coarse quantization clock frequency f MSB_CLK and the fine quantization clock frequency f LSB_CLK during the calibration phase to meet f LSB_CLK = f MSB_CLK ×2 N , and the calibration parameter CAL_Q<5:0> is saved. The high level of the residual time LSB_EN turns on the ring oscillator in the DCO to generate the fine quantization clock LSB_CLK to meet the system requirement f LSB_CLK = f MSB_CLK ×2 N of the two-step ADC. During the high level of the residual time LSB_EN, the N-bit ADC counter counts according to the fine quantization clock LSB_CLK to generate the fine quantization digital code LSB_DOUT <n:1>After the end of the high-level period of the remaining time LSB_EN, the DCO ring oscillator is turned off, and the fine quantization clock LSB_CLK is not generated. The N-bit ADC counter stops counting, and the fine quantization process ends.

[0098] e) The process of combining coarse quantization and fine quantization, including: the coarse quantization digital code MSB_DOUT <m:1>With the fine quantization digital code LSB_DOUT <n:1>Combined into the final quantization value DOUT<M+N:1>, where:

[0099] DOUT[M+N:1] = {MSB_DOUT[M],…,MSB_DOUT[1],LSB_DOUT[N],…,LSB_DOUT[1]}(13)

[0100] DOUT<M+N:1> is the quantization result of the final output of this two-step ADC, which is a total of (M+N) bits, where the high M bits are the coarse quantization digital code MSB_DOUT <m:1>, the low N bits are the finely quantized digital code LSB_DOUT <n:1>。

[0101] Furthermore, the entire readout circuit array shares the same M-bit ramp voltage V ramp , which is generated by the ramp generator module.

[0102] As mentioned above, these are only some specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A two-step ADC circuit based on an automatically calibrated DCO, characterized in that, The automatic calibration DCO automatically completes the frequency calibration of the coarse clock required for coarse quantization and the fine clock required for fine quantization; the first step of the two-step ADC is single-step M-bit SSADC coarse quantization, and the second step is fine quantization. In the fine quantization, the residual time LSB_EN is first extracted by the residual time detection module, and then the DCO is enabled by the residual time LSB_EN to generate the fine quantization clock LSB_CLK to perform N-bit time-to-digital quantization on the residual time LSB_EN. The two steps together achieve the analog-to-digital conversion function with a quantization accuracy of (M + N) bits; The connection from coarse quantization to fine quantization is automatically calibrated so that the frequency of the output fine quantization clock LSB_CLK of the DCO meets the frequency matching requirements of the coarse quantization clock MSB_CLK and the fine quantization clock LSB_CLK of the two-step ADC system.

2. The ADC circuit according to claim 1, wherein: Automatic calibration of the DOC is performed before each ADC operation, or once per frame, or at any time by sending a calibration instruction in the background; the calibration parameters are saved inside the counter, and the automatic calibration corrects the output frequency of the ring oscillator DCO through detection to meet the coarse quantization clock frequency f of the two-step ADC system MSB_CLK and the fine quantization clock frequency f LSB_CLK Frequency requirement: f LSB_CLK = f MSB_CLK ×2 N , which is used to meet the carry connection requirements of the M-bit coarse quantization SS ADC and the N-bit fine quantization of the residual time in the two-step ADC structure.

3. The ADC circuit according to claim 1, wherein This ADC circuit includes: M-bit ramp generator module for generating the ramp voltage V required for ADC quantization ramp ; Comparator module, used to compare the analog signal V in and the ramp voltage V ramp in magnitude, and output a comparison result HIT; An M-bit counter module for quantization counting and storage during the first-step M-bit coarse quantization; A residual time detection module for detecting the residual time LSB_EN between the flip moment of the comparator and the rising edge of the next coarse quantization clock MSB_CLK after the first-step coarse quantization SS ADC completes coarse quantization and the comparator output flips; An N-bit DCO and automatic calibration module, and the N-bit DCO and automatic calibration module include: A ring oscillator composed of 1 NAND gate and 4 NOT gates connected end to end, 1 N-bit ADC counter for the ADC to count during fine quantization, 1 N-bit calibration counter used in the calibration mode, 1 DFF and 1 AND gate, 1 Z-bit calibration counter and a switched capacitor array connected thereto in a matching manner, and the Z-bit calibration counter outputs a count result CAL_Q <z-1:0>Is the switch control signal for the switched capacitor array.

4. The ADC circuit according to claim 3, wherein: The comparison result HIT signal and the quantization enable ADC_EN signal generate a coarse quantization enable MSB_EN signal, and the coarse quantization enable MSB_EN signal is used to control an M-bit counter to count according to a coarse quantization clock MSB_CLK and output a coarse quantization digital code MSB_DOUT <m:1>; The coarse quantization enable MSB_EN signal is also used to connect to the residual time detection module, and the residual time detection module detects the residual time LSB_EN and accesses the N-bit DCO and automatic calibration module.

5. The ADC circuit according to claim 4, wherein: The remaining time is valid during the high level of LSB_EN, and is used to enable the DCO to generate the finely quantized clock LSB_CLK and send it to the N-bit ADC counter for counting, and output the finely quantized digital code LSB_DOUT <n:1>; Finally, the output data of the ADC, (M + N) bits, is the coarsely quantized digital code MSB_DOUT <m:1>And fine quantization digital code LSB_DOUT <n:1>The jointly combined (M + N)-bit data DOUT[M + N:1].

6. The ADC circuit according to claim 3, wherein The switch capacitor array includes C0, C1, … C z-1 A total of Z capacitors C and S0, S1, …, S z-1 A total of Z switches, and the connection mode of the capacitor array is as follows: The lower plate of capacitor C0 is grounded, and the upper plate is connected to one end of switch S0. The on / off of switch S0 is controlled by the signal CAL_Q<0> output by the Z-bit calibration counter; the lower plate of capacitor C1 is grounded, and the upper plate is connected to one end of switch S1. The on / off of switch S1 is controlled by the signal CAL_Q<1> output by the Z-bit calibration counter; And so on, capacitor C z has its lower plate grounded and its upper plate connected to one end of switch S z-1 . The on / off state of switch S z-1 is controlled by CAL_Q output from the counter for signal Z bit correction <z-1>Control; The switches S0, S1, …, S z-1 The other ends that are not connected to the capacitors are all connected together and used as the total capacitive load CAP_LOAD and are connected to the output node of a certain NOT gate in the ring oscillator circuit; The switch capacitor array is a binary weighted capacitor array C0, C1, … C z-1 , and the capacitance value of each bit satisfies C i = 2 i C0, i ∈ [0, Z - 1]; The start of the DCO ring oscillator is controlled by the calibration enable CAL_EN or the residual time LSB_EN. When the calibration enable CAL_EN is valid, it enters the automatic calibration. When the residual time LSB_EN is valid, it is the fine quantization process of the formal quantization of the two-step ADC.

7. The ADC circuit according to claim 2, wherein: The coarse quantization clock frequency f MSB_CLK and the fine quantization clock frequency f LSB_CLK The matching relationship is corrected by the DCO. It consists of an N-bit counter for correction and a Z-bit counter for correction. Whether to connect more capacitive loads is judged by the overflow signal OVER_FLOW of the N-bit counter for correction. The specific correction process is as follows: If f LSB_CLK > f MSB_CLK × 2 N , then in a coarse quantization clock MSB_CLK, an N-bit correction counter will generate an overflow signal OVER_FLOW. One overflow signal OVER_FLOW signal pulse edge causes the count value of the Z-bit correction counter to increase by 1. The counting result CAL_Q of this counter <z-1:0>Adding 1 to the total capacitive load CAP_LOAD node will increase the capacitance value of one unit capacitor, thereby reducing the f of the ring oscillator LSB_CLK frequency; in the second cycle, if f LSB_CLK > f MSB_CLK ×2 N , an overflow signal OVER_FLOW will be generated by the N-bit correction counter in one coarse quantization clock MSB_CLK, and the counting result CAL_Q <z-1:0>Adding 1, one more unit capacitor will be added to the total capacitive load CAP_LOAD node, and the frequency f of the ring oscillator will be reduced again; this cycle continues until in one cycle of the coarse quantization clock MSB_CLK, the N-bit correction counter no longer generates the overflow signal OVER_FLOW exactly, CAL_Q LSB_CLK frequency; and so on in a loop until in one cycle of the coarse quantization clock MSB_CLK, the N-bit correction counter no longer generates the overflow signal OVER_FLOW exactly, CAL_Q <z-1:0>The count value remains unchanged, and the calibration satisfies f LSB_CLK = f MSB_CLK × 2 N When the frequency calibration is completed, and the calibration parameters are directly stored in CAL_Q <z-1:0>, and the calibration parameters are used for subsequent two-step ADC quantization.

8. A conversion method of a two-step ADC circuit based on an automatically calibrated DCO according to any one of claims 1-7, characterized in that, Includes the following steps: Step 1, the DCO starts automatic digital calibration, and the method includes: Step 1.1, the reset signal RST is invalid, the CAL_FLAG signal is valid, the coarse quantization clock MSB_CLK passes through the DFF and the CAL_FLAG signal to generate a calibration enable CAL_EN for controlling the auto-calibration mode. The high-level pulse of the calibration enable CAL_EN signal is one clock cycle of the coarse quantization working clock MSB_CLK. When the calibration enable CAL_EN is high, the ring oscillator in the DCO module is started to generate the fine quantization clock LSB_CLK, so that the N-bit calibration counter starts to count within one clock cycle of the coarse quantization clock MSB_CLK according to the fine quantization clock LSB_CLK; Step 1.2, CAL_Q <z-1:0>The signal is connected to the switched-capacitor load corresponding to the respective Z bit. The CAL_Q<0> signal controls whether the capacitor of the 0th bit is connected to the ring oscillator, the CAL_Q<1> signal controls whether the capacitor of the 1st bit is connected to the load of the ring oscillator, and so on. CAL_Q <z-1>The signal controls whether the (Z - 1)-th capacitor is connected to the ring oscillator;< / z-1> Step 1.3, if f LSB_CLK > f MSB_CLK × 2 N , then the N-bit correction counter counts up in one coarse quantization clock MSB_CLK and an overflow signal OVER_FLOW is generated. The rising edge of an overflow signal OVER_FLOW increments the count value of the Z-bit correction counter, and the counting result CAL_Q of this counter <z-1:0>Adding 1, the total capacitive load CAP_LOAD node will increase by one unit capacitance value, thereby reducing the f of the ring oscillator LSB_CLK frequency; In the second cycle, if f LSB_CLK > f MSB_CLK × 2 N , then in one coarse quantization clock MSB_CLK, the N-bit correction counter will generate an overflow signal OVER_FLOW, and the counting result CAL_Q <z-1:0>If we add 1, then the total capacitive load at the CAP_LOAD node will increase by one unit capacitance again, which reduces the frequency f of the ring oscillator once more. This process repeats until f LSB_CLK reaches a certain value. When f LSB_CLK equals f MSB_CLK multiplied by 2 N , the N-bit correction counter will no longer generate an overflow signal OVER_FLOW within a coarse quantization clock MSB_CLK. Therefore, CAL_Q <z-1:0>The count value remains unchanged, that is, the total capacitance load CAP_LOAD node remains unchanged;< / z-1:0> Step 1.4, when the CAL_FLAG signal is equal to 0, the calibration mode ends, and the calibration result CAL_Q that satisfies f LSB_CLK = f MSB_CLK × 2 N is obtained <z-1:0>It is saved in the Z-bit calibration counter and provided for use in the two-step ADC quantization;< / z-1:0> Step 2, the two-step ADC starts quantization. First, M-bit coarse quantization is performed, and the process includes: Step 2.1, make the quantization enable ADC_EN effective, make the ramp enable RAMP_EN signal effective, the ramp generator starts to integrate, and the ramp voltage V ramp discharges from the high reference voltage V H while the input voltage V in range should be included in the voltage range [V ramp , V L , V H of the ramp voltage V; Step 2.2, when the ramp voltage V ramp is higher than the input signal V in , the output HIT signal of the comparator is 1, and the generated coarse quantization enable MSB_EN is valid at 1. The M-bit counter for coarse quantization starts counting with the coarse quantization clock MSB_CLK, generating the coarse quantization digital code MSB_DOUT <m:1> ；< / m:1> Step 2.3, when the ramp voltage V ramp is lower than the input voltage V in the output HIT signal of the comparator flips from 1 to 0, the coarse quantization enable MSB_EN is 0, the coarse quantization counter stops counting, and the count value is the coarse quantization digital code MSB_DOUT <m:1> ；< / m:1> Step 3, after the output HIT signal of the comparator flips from 1 to 0, the M-bit coarse quantization ends, and the ADC enters the N-bit fine quantization process, including: Step 3.1, the coarse quantization enable MSB_EN signal and the coarse quantization working clock MSB_CLK signal pass through the residual time detection module, and the residual time LSB_EN is output; Step 3.2, turn on the DCO during the high level of the remaining time LSB_EN. Since the DCO has corrected the frequencies f MSB_CLK of the coarse quantization clock and f LSB_CLK of the fine quantization clock during the calibration phase to meet f LSB_CLK = f MSB_CLK ×2 N , the fine quantization clock LSB_CLK generated by the DCO meets the system requirements of the two-step ADC. During the high level of the remaining time, the N-bit ADC counter counts according to the fine quantization clock LSB_CLK. When the remaining time LSB_EN becomes 0, the N-bit counter stops counting and outputs the fine quantization digital code LSB_DOUT <n:1> ；< / n:1> Step 4, the coarse quantization and fine quantization merging process, including: The coarsely quantized digital code MSB_DOUT <m:1>With the fine quantization digital code LSB_DOUT <n:1>It is merged into the final quantization value DOUT<M+N:1>, with a total of (M + N) bits, where:< / n:1> DOUT[M+N:1] = {MSB_DOUT[M],…,MSB_DOUT[1],LSB_DOUT[N],…,LSB_DOUT[1]}(1)In formula (1): DOUT<M+N:1> is the quantization result finally output by this two-step ADC, with a total of (M+N) bits. Among them, the high M bits are the coarse quantization digital code MSB_DOUT <m:1>, the lower N bits are the finely quantized digital code LSB_DOUT <n:1> 。< / n:1> 9. The conversion method according to claim 8, characterized in that: In the fine quantization of step 2, an M-bit ramp voltage generator is used to generate a ramp voltage V ramp . When this two-step ADC starts to work, the ramp voltage V ramp starts from the high reference voltage V H and integrates to the low reference voltage V M after the time of 2 L coarse quantization clocks MSB_CLK. After the quantization of the entire two-step ADC is completed, it is reset to the high reference voltage V H .

10. Application of a two-step ADC circuit based on automatic calibration DCO in a high-performance image sensor readout circuit, where the ramp voltage V generated by the M-bit ramp generator module is shared by all two-step ADCs in the entire readout circuit array ramp .

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