Network equipment and self-adaptive clock recovery method

Abstract

The invention provides a network device and an adaptive clock recovery method, and the network device comprises a phase modulation unit which is used for carrying out the phase modulation of a local reference clock signal, obtaining N initial clock signals of different phases, and inputting the N initial clock signals to N frequency dividers; for each frequency divider, if a first adjustment signal is received, the first adjustment signal comprises a first phase adjustment value, the initial clock phase value is adjusted based on the first phase adjustment value to obtain a target clock phase value, and the initial clock signal is subjected to frequency division based on the target clock phase value to obtain a target clock signal; inputting the target clock signal into a clock selection unit; and the clock selection unit is used for selecting one target clock signal from the target clock signals corresponding to all the frequency dividers, and the target clock signal is used for controlling the interface rate of data transmission of the network equipment. According to the scheme, the influence of delay jitter on the clock is reduced through the N frequency dividers, and the clock quality can be improved.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a network device and an adaptive clock recovery method. Background Art

[0002] ACR (Adaptive Clock Recovery) is a clock synchronization technology mainly used to recover clock signals in digital communications. In ACR technology, the receiving-end device recovers the clock signal from the packet data through an algorithm, thereby achieving clock synchronization. ACR technology does not require the source-end device to participate in clock recovery, and the receiving-end device recovers the clock information by itself, thus improving the flexibility and reliability of clock recovery. For example, ACR technology recovers clock information based on the receiving rate of packet data, does not need to carry timestamps in the packet data, and the receiving-end device recovers the clock information by itself.

[0003] Since the network between the sending-end device and the receiving-end device adds delay to the transmission of packet data, ACR technology is affected by the delay jitter of packet data. Network delay affects the receiving time of packet data, and delay jitter will be converted into noise for the recovered clock, resulting in poor quality of the recovered clock. Summary of the Invention

[0004] This application provides a network device, which includes:

[0005] A phase modulation unit, configured to perform phase modulation on a local reference clock signal to obtain N initial clock signals with different phases, and input the N initial clock signals into N frequency dividers, where N is a positive integer greater than 1;

[0006] For each frequency divider, if a first adjustment signal carrying an obtained first phase adjustment value is received, the initial clock phase value is adjusted based on the first phase adjustment value to obtain a target clock phase value, the initial clock signal is frequency-divided based on the target clock phase value to obtain a target clock signal, and the target clock signal is input into a clock selection unit; wherein, the initial clock phase value is determined based on the proportional relationship between the local reference clock frequency and the configured target clock frequency; wherein, if the first interface rate of data transmission of the network device is less than the second interface rate of data reception, the first phase adjustment value is used to make the target clock phase value advance relative to the initial clock phase value; if the first interface rate is greater than the second interface rate, the first phase adjustment value is used to make the target clock phase value lag behind the initial clock phase value;

[0007] A clock selection unit, configured to select a target clock signal from the target clock signals corresponding to all frequency dividers based on the acquired target phase, where the target clock signal is used to control the interface rate of data transmission of the network device.

[0008] This application provides an adaptive clock recovery method, which is applied to a network device and includes:

[0009] Phase-adjust the local reference clock signal to obtain N initial clock signals with different phases, and input the N initial clock signals into N frequency dividers, where N is a positive integer greater than 1;

[0010] For each frequency divider of the network device, if a first adjustment signal carrying the acquired first phase adjustment value is received through the frequency divider, adjust the initial clock phase value based on the first phase adjustment value to obtain a target clock phase value, and divide the initial clock signal based on the target clock phase value to obtain a target clock signal; where the initial clock phase value is determined based on the proportional relationship between the local reference clock frequency and the configured target clock frequency; where, if the first interface rate of data transmission of the network device is less than the second interface rate of data reception, the first phase adjustment value is used to make the target clock phase value advance the initial clock phase value; if the first interface rate is greater than the second interface rate, the first phase adjustment value is used to make the target clock phase value lag the initial clock phase value;

[0011] Select a target clock signal from the target clock signals corresponding to all frequency dividers based on the acquired target phase, where the target clock signal is used to control the interface rate of data transmission of the network device.

[0012] This application provides a computer program product, where the computer program product includes a computer program, and when the computer program is executed by a processor, it implements the adaptive clock recovery method in the above example.

[0013] This application provides a network device, including: a processor and a machine-readable storage medium, where the machine-readable storage medium stores machine-executable instructions that can be executed by the processor; where the processor is used to execute the machine-executable instructions to implement the adaptive clock recovery method in the above example of this application.

[0014] This application provides a machine-readable storage medium, where the machine-readable storage medium stores machine-executable instructions that can be executed by the processor; where the processor is used to execute the machine-executable instructions to implement the adaptive clock recovery method in the above example of this application.

[0015] As can be seen from the above technical solutions, in the embodiments of the present application, by performing phase modulation on the local reference clock signal, N initial clock signals with different phases are obtained. The N initial clock signals are input into N frequency dividers, and the target clock signal is obtained by dividing the initial clock signals through the N frequency dividers. One target clock signal is selected from the target clock signals corresponding to all the frequency dividers. In this way, the influence of packet delay jitter on the generated clock is reduced through the N frequency dividers, the quality of the generated clock is improved, the recovered clock has good quality, and the adaptive recovery of the clock is achieved. When the first interface rate of data transmission of the network device is less than the second interface rate of data reception, the initial clock phase value can be decreased based on the first phase adjustment value to obtain the target clock phase value, such that the target clock phase value is less than the initial clock phase value (i.e., the target clock phase value is advanced relative to the initial clock phase value). In this way, when the target clock signal is obtained by dividing the initial clock signal based on the target clock phase value, the earlier target clock signal is selected, so that more data can be transmitted in a shorter time, making the first interface rate close to the first interface rate. When the first interface rate is greater than the second interface rate, the initial clock phase value can be increased based on the first phase adjustment value to obtain the target clock phase value, such that the target clock phase value is greater than the initial clock phase value (i.e., the target clock phase value lags behind the initial clock phase value). In this way, when the target clock signal is obtained by dividing the initial clock signal based on the target clock phase value, the later target clock signal is selected, so that less data can be transmitted in a longer time, making the first interface rate close to the first interface rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic structural diagram of a network device in an embodiment of the present application;

[0017] Figure 2 is a schematic diagram of an application scenario in an embodiment of the present application;

[0018] Figure 3 is a schematic structural diagram of a network device in an embodiment of the present application;

[0019] Figure 4 is a schematic diagram of the initial frequency ratio obtained by the frequency offset calculation unit in an embodiment of the present application;

[0020] Figure 5 is a schematic structural diagram of a network device in an embodiment of the present application;

[0021] Figure 6 is a schematic flowchart of an adaptive clock recovery method in an embodiment of the present application;

[0022] Figure 7 is a hardware structure diagram of a network device in an embodiment of the present application. Detailed implementation manners

[0023] In an embodiment of the present application, a network device (such as a router, a switch, etc.) is proposed. Refer to Figure 1 As shown, it is a schematic structural diagram of the network device. The network device may include:

[0024] A phase modulation unit for performing phase modulation on a local reference clock signal to obtain N initial clock signals with different phases, and inputting the N initial clock signals into N frequency dividers, where N is a positive integer greater than 1.

[0025] For each frequency divider, if a first adjustment signal is received, the first adjustment signal may include a first phase adjustment value that has been obtained. Then, based on the first phase adjustment value, the initial clock phase value is adjusted to obtain a target clock phase value. Based on the target clock phase value, the initial clock signal is frequency-divided to obtain a target clock signal, and the target clock signal is input into a clock selection unit. Among them, the initial clock phase value may be determined based on the proportional relationship between the local reference clock frequency and the configured target clock frequency. Among them, if the first interface rate of data transmission of the network device is less than the second interface rate of data reception, the first phase adjustment value is used to make the target clock phase value less than the initial clock phase value (that is, the first phase adjustment value is used to make the target clock phase value ahead of the initial clock phase value); if the first interface rate is greater than the second interface rate, the first phase adjustment value is used to make the target clock phase value greater than the initial clock phase value (that is, the first phase adjustment value is used to make the target clock phase value lag behind the initial clock phase value).

[0026] For example, if the first interface rate is equal to or approximately equal to the second interface rate, the frequency divider does not receive the first adjustment signal and does not adjust the initial clock phase value. In this way, the initial clock phase value can be used as the target clock phase value, and the initial clock signal is frequency-divided to obtain the target clock signal. Or rather, the initial clock signal is frequency-divided using the initial clock phase value to obtain the target clock signal.

[0027] A clock selection unit for selecting a target clock signal from the target clock signals corresponding to all frequency dividers based on the obtained target phase. The target clock signal is used to control the interface rate of data transmission of the network device. For example, if the current phase is the phase used by the clock selection unit when selecting the target clock signal last time, the current phase can be used as the target phase. The clock selection unit uses the target phase when selecting the target clock signal this time. Or, the current phase can be adjusted to obtain the target phase.

[0028] In an example, the network device may further include (not shown in Figure 1 ):

[0029] An adjustment calculation unit, configured to determine a first phase adjustment value based on the obtained target frequency ratio and send the first phase adjustment value to an adjustment control unit; wherein, the target frequency ratio represents the frequency ratio between the original code stream clock and the local reference clock; if the target frequency ratio represents that the original code stream clock and the local reference clock differ by A integer cycles within the configured adjustment unit period, the first phase adjustment value is A; if the target frequency ratio is greater than 1, the first interface rate is less than the second interface rate, and the first phase adjustment value is negative. If the target frequency ratio is less than 1, the first interface rate is greater than the second interface rate, and the first phase adjustment value is positive;

[0030] An adjustment control unit, configured to obtain the first phase adjustment value from the adjustment calculation unit and send a first adjustment signal to each frequency divider based on the first phase adjustment value. For example, the adjustment control unit sends a first adjustment signal to each frequency divider, and the first adjustment signal may include the obtained first phase adjustment value.

[0031] In one example, the adjustment calculation unit is further configured to determine a second phase adjustment value based on the target frequency ratio and send the second phase adjustment value to the adjustment control unit; wherein, if the target frequency ratio represents that the original code stream clock and the local reference clock differ by B fractional cycles within the adjustment unit period, the second phase adjustment value is determined based on B and N; if the target frequency ratio is greater than 1, the second phase adjustment value is negative. If the target frequency ratio is less than 1, the second phase adjustment value is positive; the adjustment control unit is further configured to send a second adjustment signal to the clock selection unit based on the second phase adjustment value, and the second adjustment signal includes the second phase adjustment value;

[0032] When the clock selection unit selects a target clock signal from the target clock signals corresponding to all frequency dividers based on the obtained target phase, it is specifically configured to: adjust the current phase of the clock selection unit based on the second phase adjustment value to obtain the target phase, and select the target clock signal corresponding to the frequency divider corresponding to the target phase.

[0033] In one example, the network device may further include (not shown in Figure 1 ):

[0034] A frequency offset calculation unit, configured to count the total size of circuit emulation packets received by the network device within a reference period, determine a transmission period based on the quotient of the total size of the packets and the configured original code stream rate, and determine an initial frequency ratio based on the quotient of the transmission period and the reference period; wherein, the transmission period represents the time required to transmit data of the total size of the packets; wherein, the initial frequency ratio is used to determine the target frequency ratio.

[0035] In one example, the frequency offset calculation unit is further configured to determine the initial frequency ratio as the target frequency ratio and send the target frequency ratio to the adjustment calculation unit; alternatively, the network device further includes: a low-pass filter; the frequency offset calculation unit is further configured to send the initial frequency ratio to the low-pass filter; the low-pass filter is configured to perform a low-pass filtering operation on the initial frequency ratio to obtain the target frequency ratio and send the target frequency ratio to the adjustment calculation unit.

[0036] In one example, the network device further includes (not shown in Figure 1 ):

[0037] A timer, configured to generate a timing pulse signal corresponding to a reference period based on a local reference clock signal and send the timing pulse signal to the frequency offset calculation unit; wherein, the time interval between two adjacent timing pulse signals generated by the timer is the reference period; the frequency offset calculation unit is configured to receive the timing pulse signal output by the timer and determine the time interval between two adjacent timing pulse signals as the reference period.

[0038] In one example, the network device further includes: a buffer unit, configured to buffer the circuit emulation packets received by the network device; the adjustment control unit is further configured to determine a third phase adjustment value when the total packet size of the circuit emulation packets in the buffer unit is greater than a first threshold, where the third phase adjustment value can be negative, and send a third adjustment signal to each frequency divider, where the third adjustment signal can include the third phase adjustment value, so that each frequency divider adjusts the initial clock phase value based on the third phase adjustment value to obtain the target clock phase value; or, when the total packet size of the circuit emulation packets in the buffer unit is less than a second threshold, and the second threshold is less than the first threshold, determine a fourth phase adjustment value, where the fourth phase adjustment value can be positive, and send a fourth adjustment signal to each frequency divider, where the fourth adjustment signal can include the fourth phase adjustment value, so that each frequency divider adjusts the initial clock phase value based on the fourth phase adjustment value to obtain the target clock phase value.

[0039] In one example, the adjustment control unit is further configured to store a plurality of historical phase adjustment values within a historical time; wherein, the plurality of historical phase adjustment values are the first phase adjustment values sent by the adjustment calculation unit within the historical time; the adjustment control unit is further configured to, if the first phase adjustment value sent by the adjustment calculation unit is not received at the current time, determine the first phase adjustment value based on the stored plurality of historical phase adjustment values and send a first adjustment signal to each frequency divider, where the first adjustment signal includes the first phase adjustment value.

[0040] As can be seen from the above technical solutions, in the embodiments of the present application, by performing phase modulation on the local reference clock signal, N initial clock signals with different phases are obtained. The N initial clock signals are input into N frequency dividers, and the target clock signal is obtained by dividing the initial clock signals through the N frequency dividers. One target clock signal is selected from the target clock signals corresponding to all the frequency dividers. In this way, the influence of packet delay jitter on the generated clock is reduced through the N frequency dividers, the quality of the generated clock is improved, the quality of the recovered clock is better, and the adaptive recovery of the clock is achieved. When the first interface rate of data transmission of the network device is less than the second interface rate of data reception, the initial clock phase value can be decreased based on the first phase adjustment value to obtain the target clock phase value, so that the target clock phase value is less than the initial clock phase value. In this way, when the target clock signal is obtained by dividing the initial clock signal based on the target clock phase value, the earlier target clock signal is selected, so that more data can be sent in a shorter time, and the first interface rate approaches the first interface rate. When the first interface rate is greater than the second interface rate, the initial clock phase value can be increased based on the first phase adjustment value to obtain the target clock phase value, so that the target clock phase value is greater than the initial clock phase value. In this way, when the target clock signal is obtained by dividing the initial clock signal based on the target clock phase value, the later target clock signal is selected, so that less data can be sent in a longer time, and the first interface rate approaches the first interface rate.

[0041] The above technical solutions of the embodiments of the present application are described below in combination with specific application scenarios.

[0042] See Figure 2 As shown, it is a schematic diagram of the application scenario of the embodiments of the present application. The source device can be connected to the sending device through a specified type of interface, the destination device can be connected to the receiving device through a specified type of interface, and the sending device and the receiving device can be connected through a network. The source device can be a terminal device (such as a personal computer, a laptop, a smart phone, etc.) or a server, the destination device can be a terminal device or a server, the sending device can be a router or a switch, etc., and the receiving device can be a router or a switch, etc. The types of these devices are not limited in this embodiment.

[0043] When the source device sends a data stream to the destination device, the source device sends the data stream to the sending device through a specified type of interface. The sending device receives the data stream through the specified type of interface and encapsulates the data stream into a circuit emulation message (the data message in this embodiment is called a circuit emulation message). The sending device sends the circuit emulation message to the receiving device through the network. The receiving device receives the circuit emulation message through the network and sends the data stream carried in the circuit emulation message to the destination device through the specified type of interface. The destination device receives the data stream through the specified type of interface.

[0044] In the above application scenario, assume that the rate at which the source device sends a data stream to the sending device through the specified type of interface is S1, and the rate at which the receiving device sends a data stream to the destination device through the specified type of interface is S2. Then, it is necessary to control the rate S2 to be the same as the rate S1, that is, the rates of the data streams transmitted on the specified type of interface are the same. In this way, when the source device sends a data stream at the rate S1, the destination device receives the data stream at the same rate S2 (i.e., the rate S1).

[0045] The specified type of interface can be an E1 interface or other types of interfaces. Taking the E1 interface as an example, a time-division multiplexing frame of the E1 interface (with a length T = 125 us, that is, the sampling period is 125 microseconds) is divided into 32 equal time slots, and the time slot numbers are CH0 to CH31. The time slot CH0 is used for frame synchronization, the time slot CH16 is used to transmit signaling, and the remaining 30 time slots CH1 to CH15 and CH17 to CH31 are used for data messages. Each time slot transmits 8 bits, so a total of 256 bits are used. 8000 frames are transmitted per second. Therefore, the data rate supported by the E1 interface is 2.048 Mbit / s. On this basis, the rate at which the source device sends a data stream to the sending device through the E1 interface is 2.048 Mbit / s (rate S1), and the rate at which the receiving device sends a data stream to the destination device through the E1 interface is 2.048 Mbit / s (rate S2).

[0046] In the above application scenario, in an embodiment of the present application, a network device is proposed. This network device can be a receiving device, that is, the network device is connected to the destination device through a specified type of interface (such as an E1 interface), and the network device is connected to the sending device through the network. In this embodiment, the data stream sent by the source device to the sending device through the E1 interface is called a data stream, the circuit emulation message sent by the sending device to the receiving device (i.e., this network device) is called a circuit emulation message, that is, the network device receives the circuit emulation message sent by the sending device through the network, and the data stream sent by the network device to the destination device through the specified type of interface is called a data stream.

[0047] In an example, see Figure 3As shown in the figure, it is a schematic structural diagram of a network device. The network device may include a timer, a frequency offset calculation unit, a low-pass filter, a clock generation unit, and a buffer unit.

[0048] First, the timer. The timer can generate a timing pulse signal corresponding to the reference period T based on the local reference clock signal and send the timing pulse signal to the frequency offset calculation unit.

[0049] In one example, the value of the reference period T can be pre-configured. The reference period T can be configured according to actual experience, and there is no limitation on this reference period T. For example, the larger the reference period T, the more accurate the subsequent generated frequency ratio, but the longer the required time and the slower the clock adjustment. In the case of rapid clock changes in the source device, the tracking ability is relatively poor. Based on this, the reference period T cannot be too large, such as the reference period T is less than a certain threshold. For example, the smaller the reference period T, the more distorted the subsequent generated frequency ratio. Since the circuit simulation messages are sent one by one and there are multiple original code streams in one circuit simulation message, in the case where the reference period T is too small, it may cover the middle position of the circuit simulation message and introduce additional errors. Based on this, the reference period T cannot be too small, such as the reference period T is greater than a certain threshold.

[0050] In one example, based on the known reference period T, the timer can generate a timing pulse signal corresponding to the reference period T based on the local reference clock signal, that is, the time interval between two adjacent timing pulse signals generated by the timer is the reference period T. For example, assume that the reference period T corresponds to 1000 local reference clock signals (that is, the signals generated by the local reference clock, and the total duration of 1000 local reference clock signals is the reference period T). When the timer receives the 1st local reference clock signal, it sends the timing pulse signal 1 to the frequency offset calculation unit. When the timer receives the 1001st local reference clock signal, it sends the timing pulse signal 2 to the frequency offset calculation unit. When the timer receives the 2001st local reference clock signal, it sends the timing pulse signal 3 to the frequency offset calculation unit, and so on. Obviously, the time interval between the timing pulse signal 2 and the timing pulse signal 1 can be the reference period T, and so on.

[0051] Second, the frequency offset calculation unit. The input of the frequency offset calculation unit can be the timing pulse signal and the circuit simulation message, and the output of the frequency offset calculation unit can be the initial frequency ratio, that is, the frequency offset calculation unit determines the initial frequency ratio based on the timing pulse signal and the circuit simulation message and sends the initial frequency ratio to the low-pass filter. See Figure 4 As shown in the figure, it is a schematic diagram of the frequency offset calculation unit obtaining the initial frequency ratio. This process may include:

[0052] Step 401: The frequency offset calculation unit receives the timing pulse signal output by the timer, and determines the time interval between two adjacent timing pulse signals as the reference period, i.e., the reference period T.

[0053] For example, when the frequency offset calculation unit receives the timing pulse signal 1, it takes the reception time of the timing pulse signal 1 as the start time of the reference period. When the frequency offset calculation unit receives the timing pulse signal 2, it takes the reception time of the timing pulse signal 2 as the end time of the reference period. In this way, the time interval between the timing pulse signal 2 and the timing pulse signal 1 can be determined as the reference period T1.

[0054] When the frequency offset calculation unit receives the timing pulse signal 2, it takes the reception time of the timing pulse signal 2 as the start time of the reference period. When the frequency offset calculation unit receives the timing pulse signal 3, it takes the reception time of the timing pulse signal 3 as the end time of the reference period. In this way, the time interval between the timing pulse signal 3 and the timing pulse signal 2 can be determined as the reference period T2, and so on.

[0055] Step 402: The frequency offset calculation unit counts the total size of the circuit emulation packets received by the network device within the reference period. For example, the total size of the circuit emulation packets can be M bits (bit).

[0056] For example, starting from the start time of the reference period T1 (i.e., the reception time of the timing pulse signal 1), each time the frequency offset calculation unit receives a circuit emulation packet, it increments the packet reference count by 1. The initial value of the packet reference count is 0. In this way, until the end time of the reference period T1 (i.e., the reception time of the timing pulse signal 2), the increment of the packet reference count stops, and thus the packet reference count of the circuit emulation packets in the reference period T1 is obtained. Further, since the size of each circuit emulation packet is the same and the size of a single circuit emulation packet is a known value, therefore, based on the packet reference count and the size of a single circuit emulation packet, the total size M of the circuit emulation packets can be determined. For example, the product value between the packet reference count and the size of a single circuit emulation packet is the total size M of the packets in the reference period T1. Obviously, for each reference period, the frequency offset calculation unit can obtain the total size M of the packets in that reference period.

[0057] Step 403: The frequency offset calculation unit determines the transmission period based on the quotient of the total packet size M and the configured original code stream rate. For example, the quotient of the total packet size M and the original code stream rate is used as the transmission period.

[0058] For example, if the rate at which the source device sends a data stream to the sending device through an E1 interface is 2.048 Mbit / s (i.e., rate S1), and the rate at which the receiving device (i.e., this network device) sends a data stream to the destination device through an E1 interface is 2.048 Mbit / s (i.e., rate S2), then the original stream rate can be 2.048 Mbit / s. Obviously, the original stream rate represents the rate at which the source device sends a data stream to the sending device through the E1 interface, and also represents the rate at which this network device sends a data stream to the destination device through the E1 interface. The original stream rate can be pre-configured, such as 2.048 Mbit / s.

[0059] In one example, the following formula can be used to determine the transmission period: Ts = M / P. Ts can represent the transmission period, M can represent the total size of the packets, and P can represent the original stream rate, with the unit of bit / S. Obviously, the transmission period Ts represents the time required to send the data of the total size of the packets (i.e., the data stream). For example, the transmission period Ts represents the time required to send M bits at the original stream rate.

[0060] Step 404: The frequency offset calculation unit determines an initial frequency ratio based on the quotient of the transmission period Ts and the reference period T, such as using the quotient of the transmission period Ts and the reference period T as the initial frequency ratio.

[0061] In one example, the following formula can be used to determine the initial frequency ratio: Fp = Ts / T. Fp can represent the initial frequency ratio, Ts can represent the transmission period, and T can represent the reference period. Among them, the initial frequency ratio can represent the frequency ratio of the original stream clock to the local reference clock. For example, the reference period T is determined based on the local reference clock, while the transmission period Ts is determined based on the original stream rate (i.e., the rate at which the source device sends a data stream to the sending device through the E1 interface) and the total size M of the packets (considering that the rate at which the sending device sends circuit emulation packets to this network device is the same as the rate at which the source device sends a data stream to the sending device through the E1 interface, the total size M of the packets can be the total size of the data stream packets sent by the source device to the sending device through the E1 interface), that is, the transmission period Ts is determined based on the clock of the source device (the clock of the source device is called the original stream clock). On this basis, the proportional relationship between the transmission period Ts and the reference period T can represent the proportional relationship between the original stream clock and the local reference clock. In this way, the initial frequency ratio represents the frequency ratio of the original stream clock to the local reference clock.

[0062] Step 405: The frequency offset calculation unit sends the initial frequency ratio to the low-pass filter.

[0063] Third, a low-pass filter. The low-pass filter performs a low-pass filtering operation on the initial frequency ratio to obtain a target frequency ratio (i.e., the frequency ratio after the low-pass filtering operation), and sends the target frequency ratio to the clock generation unit. For example, the low-pass filter sends the target frequency ratio to the adjustment calculation unit of the clock generation unit.

[0064] In one example, the low-pass filter can perform a low-pass filtering operation on the initial frequency ratio. By performing a low-pass filtering operation on the initial frequency ratio, it is possible to filter out the frequency ratio jitter caused by the time delay change of high-frequency circuit simulation packets. Regarding the filtering parameters of the low-pass filter, such as the cut-off frequency, stopband cut-off frequency, and stopband gain, they can be set according to actual needs to make the performance of the low-pass filter match the actual application scenario.

[0065] For example, regarding the cut-off frequency of the low-pass filter, when the cut-off frequency is smaller, the filtering effect on the time delay jitter is better, but the tracking performance is worse. In the case of a rapid change in the clock of the source device, the generated clock cannot track the clock of the source device well. Therefore, the cut-off frequency cannot be too small. When the cut-off frequency is larger, the filtering effect on the time delay jitter is worse. Therefore, the cut-off frequency cannot be too large.

[0066] For this low-pass filter, the low-pass filter can be an FIR (Finite Impulse Response) filter, or it can be other types of low-pass filters, and there is no restriction on this.

[0067] Fourth, a buffer unit. The buffer unit buffers the circuit simulation packets received by the network device.

[0068] For example, each time the network device receives a circuit simulation packet, it can buffer the circuit simulation packet into this buffer unit, that is, the buffer unit performs buffering of the circuit simulation packet. For example, the buffer unit can be a specified storage medium, as long as it can implement the data storage function, such as the memory of the network device, etc.

[0069] Fifth, a clock generation unit. The inputs of the clock generation unit are the target frequency ratio, the local reference clock signal, and the buffer waterline position (such as the total packet size of the circuit simulation packets in the buffer unit), and the output of the clock generation unit is a clock (i.e., the target clock signal). The clock generation unit obtains the target clock signal based on the target frequency ratio, the local reference clock signal, the buffer waterline position, etc., and outputs the target clock signal.

[0070] After the target clock signal is output, the circuit simulation message can be controlled to be read out from the buffer unit based on the target clock signal, and the circuit simulation message is read out from the buffer unit. For example, instead of reading the circuit simulation message from the buffer unit based on the local reference clock signal, the circuit simulation message is read out from the buffer unit based on the target clock signal, that is, the target clock signal is used to control the interface rate of data transmission of the network device.

[0071] For example, assume that the rate at which the network device sends a data stream to the destination device through the E1 interface is 2.048 Mbit / s, and 2.048 Mbit / s corresponds to P clock signals. Then, when the local reference clock generates P local reference clock signals, 2.048 Mbit of data needs to be read out from the buffer unit.

[0072] On this basis, in this embodiment, when the clock generation unit outputs P target clock signals, 2.048 Mbit of data needs to be read out from the buffer unit. Obviously, between two adjacent target clock signals output by the clock generation unit, 2.048 Mbit / P of data needs to be read out from the buffer unit. In summary, it can be seen that the target clock signal is used to control the interface rate of data transmission of the network device, that is, how many bits of data are read.

[0073] It should be noted that the total duration of the P target clock signals output by the clock generation unit may be different from the total duration of the P local reference clock signals generated by the local reference clock. That is, the data is read out from the buffer unit based on the target clock signal output by the clock generation unit, rather than based on the local reference clock signal generated by the local reference clock, so that the interface rate of the network device sending data through the E1 interface is close to the interface rate of the source device sending data through the E1 interface.

[0074] In one example, see Figure 5 As shown, it is a schematic structural diagram of a network device. For the clock generation unit of the network device, the clock generation unit may include a phase modulation unit, N frequency dividers, a clock selection unit, an adjustment calculation unit, an adjustment control unit, and a clock information storage unit. For the N frequency dividers, N may be a positive integer greater than 1. For example, when N is 4, there are 4 frequency dividers.

[0075] Sixth, the phase modulation unit. The phase modulation unit performs phase modulation on the local reference clock signal to obtain N initial clock signals with different phases, and inputs the N initial clock signals into the N frequency dividers.

[0076] For example, the input of the phase modulation unit is a local reference clock signal generated by a local reference clock, and the output of the phase modulation unit is N initial clock signals with different phases. The phase modulation unit can perform phase modulation on the local reference clock signal to obtain N initial clock signals with different phases. Regarding how to perform phase modulation on the local reference clock signal, no limitation is made in this embodiment, and the phase modulation unit can have various implementation manners, such as a PLL (Phase Locked Loop), a delay link, etc. Among them, when obtaining N initial clock signals with different phases, the N different phases can cover 360 degrees of the phase of the local reference clock signal.

[0077] For example, taking the local reference clock as 65.536 MHz as an example, if the number of N is 4, then 4 initial clock signals with phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees are generated by the phase modulation unit.

[0078] In an example, when the phase modulation unit obtains N initial clock signals with different phases, the N phases correspond to N frequency dividers one by one. For example, phase 1 corresponds to frequency divider 1, phase 2 corresponds to frequency divider 2, and so on, phase N corresponds to frequency divider N. On this basis, the initial clock signal of phase 1 is input to frequency divider 1 corresponding to phase 1, the initial clock signal of phase 2 is input to frequency divider 2 corresponding to phase 2, and so on, the initial clock signal of phase N is input to frequency divider N corresponding to phase N.

[0079] Seventh, an adjustment calculation unit. The adjustment calculation unit determines a first phase adjustment value and a second phase adjustment value based on the target frequency ratio, and sends the first phase adjustment value and the second phase adjustment value to the adjustment control unit.

[0080] In an example, the initial frequency ratio represents the frequency ratio of the original code stream clock to the local reference clock, and the target frequency ratio represents the frequency ratio of the original code stream clock to the local reference clock. If the target frequency ratio indicates that the original code stream clock and the local reference clock differ by A integer cycles within the adjustment unit period, the first phase adjustment value can be A. If the target frequency ratio indicates that the original code stream clock and the local reference clock differ by B fractional cycles within the adjustment unit period, the second phase adjustment value can be determined based on B and N. For example, taking the floor of B multiplied by N to obtain the second phase adjustment value, or taking the ceiling of B multiplied by N as the second phase adjustment value.

[0081] If the target frequency ratio is greater than 1, it means that the first interface rate of data transmission of the network device is less than the second interface rate of data reception of the network device. The first interface rate is the rate at which the network device sends data streams to the destination device through the E1 interface. This first interface rate is the actual rate and may be different from 2.048 Mbit / s. It is expected that the first interface rate is 2.048 Mbit / s. The second interface rate at which the network device receives data is the same as the interface rate at which the source device sends data through the E1 interface, that is, the second interface rate is the rate at which the source device sends data streams through the E1 interface. This second interface rate is the actual rate of the source device and may be different from 2.048 Mbit / s. It is expected that the second interface rate is 2.048 Mbit / s.

[0082] If the target frequency ratio is less than 1, it means that the first interface rate is greater than the second interface rate.

[0083] If the target frequency ratio is equal to 1, it means that the first interface rate is equal to the second interface rate.

[0084] If the target frequency ratio is greater than 1, the first phase adjustment value can be negative. For example, the first phase adjustment value can be -A. The second phase adjustment value can be negative. For example, the second phase adjustment value can be -C, and C can be the floor of B multiplied by N or the ceiling of B multiplied by N. By setting the first phase adjustment value and the second phase adjustment value to negative values, the phase can be advanced, and the interval between the two target clock signals is shorter, thereby increasing the first interface rate and making the first interface rate the same as or close to the second interface rate.

[0085] If the target frequency ratio is less than 1, the first phase adjustment value can be positive. For example, the first phase adjustment value can be +A. The second phase adjustment value can be positive. For example, the second phase adjustment value can be +C, and C can be the floor of B multiplied by N or the ceiling of B multiplied by N. By setting the first phase adjustment value and the second phase adjustment value to positive values, the phase can be delayed, and the interval between the two target clock signals is longer, thereby reducing the first interface rate and making the first interface rate the same as or close to the second interface rate.

[0086] If the target frequency ratio is equal to 1, the first phase adjustment value can be 0, and the second phase adjustment value can be 0, that is, no phase adjustment is performed, and the interval between the two target clock signals can remain unchanged.

[0087] For example, assume that the target frequency ratio is 1.00125. If the adjustment unit period is 1000 cycles, the adjustment unit period can be configured according to experience. Taking 1000 cycles as an example, it means that when the local clock has passed 1000 cycles, the clock of the source device has passed 1001.25 cycles. On this basis, the target frequency ratio indicates that the original code stream clock and the local reference clock differ by 1 (1001 - 1000) integer cycle within the adjustment unit period, and the first phase adjustment value can be -1. The target frequency ratio indicates that the original code stream clock and the local reference clock differ by 0.25 (0.25 - 0) fractional cycle within the adjustment unit period. If the number N of frequency dividers is 4, then rounding down (0.25 * 4), the second phase adjustment value is obtained, that is, the second phase adjustment value can be -1.

[0088] Assume that the target frequency ratio is 1.0015 and the adjustment unit period is 1000 cycles. The target frequency ratio indicates that the original code stream clock and the local reference clock differ by 1 integer cycle within the adjustment unit period, and the first phase adjustment value can be -1. In addition, the target frequency ratio indicates that the original code stream clock and the local reference clock differ by 0.5 fractional cycle within the adjustment unit period, then the second phase adjustment value can be -2.

[0089] Assume that the target frequency ratio is 1.00025 and the adjustment unit period is 1000 cycles. The target frequency ratio indicates that the original code stream clock and the local reference clock differ by 0 integer cycles within the adjustment unit period, and the first phase adjustment value can be 0. In addition, the target frequency ratio indicates that the original code stream clock and the local reference clock differ by 0.25 fractional cycle within the adjustment unit period, then the second phase adjustment value can be -1.

[0090] Assume that the target frequency ratio is 0.9995 and the adjustment unit period is 1000 cycles. The target frequency ratio indicates that the original code stream clock and the local reference clock differ by 1 integer cycle within the adjustment unit period, and the first phase adjustment value can be +1. In addition, the target frequency ratio indicates that the original code stream clock and the local reference clock differ by 0.5 fractional cycle within the adjustment unit period, then the second phase adjustment value can be +2.

[0091] In summary, the adjustment calculation unit can obtain the first phase adjustment value and the second phase adjustment value, and send the first phase adjustment value and the second phase adjustment value to the adjustment control unit. The information transmission format between the adjustment calculation unit and the adjustment control unit can be ±A.C, that is, within the adjustment unit period (such as 1000), A coarse adjustments and B fine adjustments are required. A coarse adjustments indicate adjusting the frequency divider based on the first phase adjustment value, and B fine adjustments indicate adjusting the clock selection unit based on the second phase adjustment value.

[0092] For example, if the target frequency ratio is greater than 1, then the "-" is transmitted in "±", that is, A represents a negative value, C represents a negative value, A is not 0 and C is not 0, or, A is not 0 and C is 0, or, A is 0 and C is not 0. Or, if the target frequency ratio is less than 1, then the "+" is transmitted in "±", that is, A represents a positive value, C represents a positive value, A is not 0 and C is not 0, or, A is not 0 and C is 0, or, A is 0 and C is not 0. Or, if the target frequency ratio is equal to 1, then ±A.C may not be transmitted. Of course, +0.0 may also be transmitted, and -0.0 may also be transmitted, that is, A is 0 and C is 0.

[0093] For example, if the target frequency ratio is 1.00125, the information transmission format between the adjustment calculation unit and the adjustment control unit can be -1.1, that is, the first phase adjustment value is -1 and the second phase adjustment value is -1.

[0094] Considering that within an adjustment unit period (such as 1000), A coarse adjustments and B fine adjustments need to be performed. Therefore, the adjustment calculation unit only needs to send ±A.C once within the adjustment unit period, that is to say, within the adjustment unit period, the adjustment calculation unit only calculates the first phase adjustment value and the second phase adjustment value once.

[0095] Eighth, the adjustment control unit. The adjustment control unit can obtain the first phase adjustment value and the second phase adjustment value from the adjustment calculation unit. The adjustment control unit can send a first adjustment signal to each frequency divider, and the first adjustment signal can include the first phase adjustment value. The adjustment control unit can send a second adjustment signal to the clock selection unit, and the second adjustment signal includes the second phase adjustment value.

[0096] For example, the adjustment control unit can obtain the information of ±A.C from the adjustment calculation unit. If the information obtained is -A.C, then the adjustment control unit determines that the first phase adjustment value is -A and the second phase adjustment value is -C. In this way, the first adjustment signal includes the first phase adjustment value of "-A", and the second adjustment signal includes the second phase adjustment value of "-C". Or, if the information obtained is +A.C, then the adjustment control unit determines that the first phase adjustment value is +A and the second phase adjustment value is +C. In this way, the first adjustment signal includes the first phase adjustment value of "-C", and the second adjustment signal includes the second phase adjustment value of "+C".

[0097] For example, when the adjustment control unit sends the first adjustment signal and the second adjustment signal, within the adjustment unit period (such as 1000), it only needs to send the first adjustment signal and the second adjustment signal once. When the adjustment control unit sends the second adjustment signal to the clock selection unit, the second adjustment signal is also called a selection signal.

[0098] Ninth, an N - th frequency divider. For each frequency divider, if the frequency divider receives a first adjustment signal and the first adjustment signal includes a first phase adjustment value, then the initial clock phase value is adjusted based on the first phase adjustment value to obtain a target clock phase value, the initial clock signal is divided based on the target clock phase value to obtain a target clock signal, and the target clock signal is input to the clock selection unit. Alternatively, if the frequency divider does not receive the first adjustment signal, then the initial clock phase value is used as the target clock phase value, the initial clock signal is divided based on the target clock phase value to obtain a target clock signal, and the target clock signal is input to the clock selection unit.

[0099] In an example, the initial clock phase value can be determined. The initial clock phase value can be determined based on the proportional relationship between the local reference clock frequency and the configured target clock frequency. The target clock frequency is the clock frequency used when the network device sends a data stream to the destination device through the E1 interface. The target clock frequency is pre - configured and corresponds to the first interface rate. For example, the target clock frequency can be 2.048 MHz, and the interface rate (i.e., the first interface rate) corresponding to the target clock frequency of 2.048 MHz is 2.048 Mbit / s, so that the rate at which the network device sends a data stream to the destination device through the E1 interface is 2.048 Mbit / s.

[0100] The local reference clock frequency is the frequency used by the clock of the network device and can be an integer multiple of the target clock frequency, such as 8 times, 16 times, 32 times, 64 times, 128 times, etc. The local reference clock frequency can be selected according to experience. Taking the local reference clock frequency of 65.536 MHz as an example, the local reference clock frequency is 32 times the target clock frequency. On this basis, the proportional relationship between the local reference clock frequency and the target clock frequency can be calculated, and this proportional relationship is used as the division value. For example, the division value can be 32. Then, the initial clock phase value can be determined based on this division value. For example, the initial clock phase value of 32 means that the interval between two adjacent clock signals output by the frequency divider is the initial clock phase value of 32.

[0101] After obtaining the initial clock phase value, the frequency divider can use this initial clock phase value to divide the initial clock signal to obtain a target clock signal. Assuming the initial clock phase value is 32, the frequency divider outputs only 1 target clock signal for every 32 initial clock signals received, that is, the interval between two adjacent target clock signals is 32. For example, when the frequency divider receives the 1st initial clock signal, it outputs 1 target clock signal; when receiving the 2nd - 32nd initial clock signals, it does not output a target clock signal; when receiving the 33rd initial clock signal, it outputs 1 target clock signal, and so on. Another example, when the frequency divider receives the 2nd initial clock signal, it outputs 1 target clock signal; when receiving the 34th initial clock signal, it outputs 1 target clock signal, and so on. Obviously, based on the local reference clock frequency of 65.536 MHz, the target clock frequency of 2.048 MHz can be obtained by using a 32 - division method.

[0102] In one example, if the frequency divider does not receive the first adjustment signal, the initial clock phase value can be used as the target clock phase value, and the initial clock signal is divided based on this target clock phase value to obtain a target clock signal, which is input to the clock selection unit. For example, when the frequency divider receives the hth initial clock signal, it outputs 1 target clock signal to the clock selection unit; when receiving the (h + 32)th initial clock signal, it outputs 1 target clock signal to the clock selection unit, and so on.

[0103] In one example, if the frequency divider receives the first adjustment signal, and the first adjustment signal includes a first phase adjustment value, when this first phase adjustment value is negative (i.e., the first interface rate is less than the second interface rate), such as -A, the initial clock phase value is adjusted based on the first phase adjustment value to obtain the target clock phase value, and the target clock phase value is less than the initial clock phase value, and the target clock phase value is the initial clock phase value minus A. Then, the initial clock signal is divided based on this target clock phase value to obtain a target clock signal, which is input to the clock selection unit. For example, when A is 1, when the frequency divider receives the hth initial clock signal, it outputs 1 target clock signal to the clock selection unit; when receiving the (h + 31)th (the target clock phase value is 32 (initial clock phase value) minus 1, that is, the target clock phase value is 31) initial clock signal, it outputs 1 target clock signal to the clock selection unit, and so on. Obviously, the clock phase obtained by the frequency divider can be adjusted by the division count value. For example, if it is necessary to adjust the phase forward by 1 / 32 of a cycle, the division count reaches 31 to generate the target clock edge. In this way, more target clock signals can be generated in a shorter time, so that more data can be read in a shorter time, making the first interface rate increase and approach the second interface rate.

[0104] In one example, if the frequency divider receives a first adjustment signal and the first adjustment signal includes a first phase adjustment value, when the first phase adjustment value is positive (i.e., the first interface rate is greater than the second interface rate), such as +A, the initial clock phase value is adjusted based on the first phase adjustment value to obtain a target clock phase value, and the target clock phase value is greater than the initial clock phase value. The target clock phase value is the initial clock phase value plus A. Then, the initial clock signal is divided based on the target clock phase value to obtain a target clock signal, and the target clock signal is input to the clock selection unit. For example, when A is 1, when the frequency divider receives the h-th initial clock signal, it outputs 1 target clock signal to the clock selection unit. When receiving the (h + 33) -th initial clock signal (the target clock phase value is 32 plus 1 of the initial clock phase value, that is, the target clock phase value is 33), it outputs 1 target clock signal to the clock selection unit, and so on. Obviously, the clock phase obtained by the frequency divider can be adjusted by the division count value. For example, if it is necessary to adjust the phase backward by 1 / 32 of a cycle, the division count reaches 33 to generate the target clock edge. In this way, fewer target clock signals can be generated in a longer time, so that less data is read in a longer time, making the first interface rate smaller and approaching the second interface rate.

[0105] In summary, when the counter in the frequency divider steps one unit (the division count value is incremented or decremented by 1, and the division count value is the initial clock phase value), the generated target clock signal can be accelerated or decelerated by the time of 1 reference clock cycle, which can be called coarse adjustment. If the coarse adjustment value (i.e., the first phase adjustment value) is positive, the division count value can be incremented by 1. If the coarse adjustment value is negative, the division count value can be decremented by 1.

[0106] Tenth, the clock selection unit. The clock selection unit can select one target clock signal from all the target clock signals corresponding to the frequency dividers and output the target clock signal.

[0107] In one example, frequency divider 1 is the frequency divider corresponding to phase 1, frequency divider 2 is the frequency divider corresponding to phase 2, and so on. Frequency divider N is the frequency divider corresponding to phase N. Based on this, assuming the current phase is phase W (such as phase 1, etc.), the target clock signal corresponding to frequency divider W is selected from all the target clock signals corresponding to the frequency dividers, and the target clock signal corresponding to frequency divider W is output.

[0108] In one example, if the clock selection unit does not receive the second adjustment signal, the current phase remains unchanged. The target clock signal corresponding to frequency divider W is selected from all the target clock signals corresponding to the frequency dividers, and the target clock signal corresponding to frequency divider W is output, and the target clock signals corresponding to other frequency dividers are not selected.

[0109] In one example, if the clock selection unit receives a second adjustment signal and the second adjustment signal includes a second phase adjustment value, when the second phase adjustment value is negative (i.e., the first interface rate is less than the second interface rate), such as -C, the current phase W is adjusted based on the second phase adjustment value to obtain a target phase (i.e., W - C), and the target clock signal corresponding to the frequency divider (W - C) corresponding to the target phase is selected. For example, when C is 1, the clock selection unit determines that the target phase is W - 1, selects the target clock signal corresponding to the frequency divider (W - 1) corresponding to the target phase (W - 1), and outputs the target clock signal.

[0110] In one example, if the clock selection unit receives a second adjustment signal and the second adjustment signal includes a second phase adjustment value, when the second phase adjustment value is positive (i.e., the first interface rate is greater than the second interface rate), such as +C, the current phase W is adjusted based on the second phase adjustment value to obtain a target phase (i.e., W + C), and the target clock signal corresponding to the frequency divider (W + C) corresponding to the target phase is selected. For example, when C is 1, the clock selection unit determines that the target phase is W + 1, selects the target clock signal corresponding to the frequency divider (W + 1) corresponding to the target phase (W + 1), and outputs the target clock signal.

[0111] For example, if there are a total of 4 frequency dividers, when the frequency divider W is the frequency divider 4 and C is 1, the frequency divider (W + C) is the frequency divider 1, that is, it cycles to the frequency divider 1. Similarly, when the frequency divider W is the frequency divider 1 and C is 1, the frequency divider (W - C) is the frequency divider 4, that is, it cycles to the frequency divider 4.

[0112] In summary, the clock selection unit can switch between clocks of different phases, and can speed up or slow down the generated clock by C reference clock cycles, which can be called fine-tuning. If the fine-tuning value (i.e., the second phase adjustment value) is positive, the current phase W can be added with C phases to obtain the target phase. If the fine-tuning value is negative, the current phase W can be subtracted by C phases to obtain the target phase.

[0113] In one example, for scenarios such as circuit simulation, the generated target clock signal is used to control the reading of the packet buffer. In some unexpected situations, such as severe network congestion, it may cause a large change in the waterline of the packet buffer, approaching the upper and lower boundaries of the buffer. In such extreme cases, in order to ensure that the transmitted data does not appear abnormal, rapid clock adjustment can be performed. For example, when the buffer waterline is too low, the output clock frequency is rapidly slowed down; when the buffer waterline is too high, the output clock frequency is rapidly increased. Therefore, the adjustment control module can also adjust the clock output frequency according to the buffer waterline to implement the abnormal protection function.

[0114] In summary, the adjustment control unit can also obtain the cache waterline position (such as the total message size of the circuit simulation messages in the cache unit). When the total message size is greater than the first threshold (indicating that the cache waterline is too high), the third phase adjustment value is determined. The third phase adjustment value can be negative and can be a pre-configured value, and there is no limit to this third phase adjustment value, such as -1, -2, -3, etc. Then, the adjustment control unit sends a third adjustment signal to each frequency divider, and the third adjustment signal can include the third phase adjustment value. For each frequency divider, if the frequency divider receives the third adjustment signal and the third adjustment signal includes the third phase adjustment value, the initial clock phase value is adjusted based on the third phase adjustment value to obtain the target clock phase value, and the target clock phase value is less than the initial clock phase value. Then, the initial clock signal is divided based on the target clock phase value to obtain the target clock signal, and the target clock signal is input to the clock selection unit.

[0115] Alternatively, when the total message size of the circuit simulation messages in the cache unit is less than the second threshold (indicating that the cache waterline is too low), and the second threshold is less than the first threshold, the adjustment control unit determines the fourth phase adjustment value. The fourth phase adjustment value can be positive and can be a pre-configured value, and there is no limit to this fourth phase adjustment value, such as +1, +2, +3, etc. Then, the adjustment control unit sends a fourth adjustment signal to each frequency divider, and the fourth adjustment signal can include the fourth phase adjustment value. For each frequency divider, if the frequency divider receives the fourth adjustment signal and the fourth adjustment signal includes the fourth phase adjustment value, the initial clock phase value is adjusted based on the fourth phase adjustment value to obtain the target clock phase value, and the target clock phase value is greater than the initial clock phase value. Then, the initial clock signal is divided based on the target clock phase value to obtain the target clock signal, and the target clock signal is input to the clock selection unit.

[0116] For example, when the total message size is greater than the first threshold, the adjustment control unit can also determine the fifth phase adjustment value. The fifth phase adjustment value can be negative and can be a pre-configured value, such as -1, -2, -3, etc., taking -C as an example. Then, the adjustment control unit sends a fifth adjustment signal to the clock selection unit, and the fifth adjustment signal can include the fifth phase adjustment value. After receiving the fifth adjustment signal, the clock selection unit adjusts the current phase W based on the fifth phase adjustment value to obtain the target phase (i.e., W - C), and selects the target clock signal corresponding to the frequency divider (W - C) corresponding to the target phase.

[0117] For example, when the total size of the message is less than the second threshold, the adjustment control unit can also determine a sixth phase adjustment value. The sixth phase adjustment value can be a positive value and can be a pre-configured value, such as +1, +2, +3, etc. Taking +C as an example. Then, the adjustment control unit sends a sixth adjustment signal to the clock selection unit, and the sixth adjustment signal can include the sixth phase adjustment value. After receiving the sixth adjustment signal, the clock selection unit adjusts the current phase W based on the sixth phase adjustment value to obtain a target phase (i.e., W + C), and selects the target clock signal corresponding to the frequency divider (W + C) of the target phase.

[0118] In one example, the adjustment control unit has a clock holdover function. It can record the clock adjustment data for a period of time during normal operation through the adjustment control unit or the clock information storage unit. In the case of a source-side link interruption (i.e., this network device does not receive the circuit emulation message), the clock is continuously generated by reading the stored clock adjustment data to achieve the holdover function. The performance of clock holdover depends on the amount of clock adjustment data. The more clock adjustment data there is, the better the holdover performance.

[0119] In summary, the adjustment control unit can store multiple historical phase adjustment values within a historical time, or the clock information storage unit can store multiple historical phase adjustment values within a historical time. Among them, the multiple historical phase adjustment values are the first phase adjustment values sent by the adjustment calculation unit within the historical time (i.e., a period of time before the current time). For example, if it is necessary to store M historical phase adjustment values, each time the first phase adjustment value sent by the adjustment calculation unit is received, the first phase adjustment value is updated to the clock information storage unit as a historical phase adjustment value. When the number of stored historical phase adjustment values exceeds M, the historical phase adjustment value with the earliest storage time can also be deleted to maintain the storage of M historical phase adjustment values.

[0120] On this basis, if the adjustment control unit does not receive the first phase adjustment value sent by the adjustment calculation unit at the current time (the time interval between the current time and the time when the first phase adjustment value was last received is the adjustment unit period), the first phase adjustment value is determined based on the stored multiple historical phase adjustment values (such as the average value of the multiple historical phase adjustment values as the first phase adjustment value, or the maximum value of the multiple historical phase adjustment values as the first phase adjustment value, or the minimum value of the multiple historical phase adjustment values as the first phase adjustment value, or any value among the multiple historical phase adjustment values as the first phase adjustment value).

[0121] Then, the adjustment control unit sends a first adjustment signal to each frequency divider. The first adjustment signal includes the first phase adjustment value, so that each frequency divider adjusts the initial clock phase value based on the first phase adjustment value to obtain a target clock phase value. The adjustment process can refer to the above embodiments and will not be elaborated here.

[0122] In addition, the adjustment control unit can also store multiple reference phase adjustment values within a historical time, or the clock information storage unit can store multiple reference phase adjustment values within a historical time. Among them, the multiple reference phase adjustment values are the second phase adjustment values sent by the adjustment calculation unit within the historical time. On this basis, if the adjustment control unit does not receive the second phase adjustment value sent by the adjustment calculation unit at the current time, the second phase adjustment value is determined based on the stored multiple reference phase adjustment values (such as the average value of the multiple reference phase adjustment values as the second phase adjustment value, or the maximum value of the multiple reference phase adjustment values as the second phase adjustment value, or the minimum value of the multiple reference phase adjustment values as the second phase adjustment value, or any value among the multiple reference phase adjustment values as the second phase adjustment value). Then, the adjustment control unit sends a second adjustment signal to the clock selection unit. The second adjustment signal includes the second phase adjustment value, so that the clock selection unit adjusts the current phase W based on the second phase adjustment value to obtain a target phase, and selects the target clock signal corresponding to the frequency divider corresponding to the target phase.

[0123] As can be seen from the above technical solutions, in the embodiments of the present application, by performing phase adjustment on the local reference clock signal, N initial clock signals with different phases are obtained. The N initial clock signals are input into N frequency dividers, and the target clock signals are obtained by dividing the initial clock signals by the N frequency dividers. One target clock signal is selected from the target clock signals corresponding to all the frequency dividers. In this way, the influence of packet delay jitter on the generated clock is reduced by the N frequency dividers, the quality of the generated clock is improved, the recovered clock has good quality, and the adaptive recovery of the clock is realized. The network device has a holdover function and can maintain a long-term clock output after the circuit emulation packet is interrupted. The clock generation method is universal and can be extended to other scenarios that require synchronized clocks, such as 1588 ACR and other application scenarios.

[0124] Based on the same application concept as the above solution, an adaptive clock recovery method is proposed in the embodiments of the present application. This method can be applied to network devices (such as routers, switches, etc.). Refer to Figure 6 As shown, it is a schematic flowchart of the adaptive clock recovery method. The method can include:

[0125] Step 601: Phase-modulate the local reference clock signal to obtain N initial clock signals with different phases, and input the N initial clock signals into N frequency dividers, where N is a positive integer greater than 1.

[0126] Step 602: For each frequency divider of the network device, if a first adjustment signal is received through the frequency divider, and the first adjustment signal includes a first phase adjustment value that has been obtained, then adjust the initial clock phase value based on the first phase adjustment value to obtain a target clock phase value, and divide the initial clock signal based on the target clock phase value to obtain a target clock signal. The initial clock phase value is determined based on the ratio relationship between the local reference clock frequency and the configured target clock frequency. If the first interface rate for data transmission of the network device is less than the second interface rate for data reception, the first phase adjustment value is used to make the target clock phase value advance relative to the initial clock phase value; if the first interface rate is greater than the second interface rate, the first phase adjustment value is used to make the target clock phase value lag behind the initial clock phase value.

[0127] Step 603: Select a target clock signal from the target clock signals corresponding to all the frequency dividers based on the obtained target phase, and the target clock signal is used to control the interface rate of data transmission of the network device.

[0128] In one example, the process of obtaining the first phase adjustment value may include: determining the first phase adjustment value based on the obtained target frequency ratio; where the target frequency ratio represents the frequency ratio between the original code stream clock and the local reference clock; if the target frequency ratio represents that the original code stream clock and the local reference clock differ by A integer cycles within the configured adjustment unit period, the first phase adjustment value is A; if the target frequency ratio is greater than 1, the first interface rate is less than the second interface rate, and the first phase adjustment value is negative, if the target frequency ratio is less than 1, the first interface rate is greater than the second interface rate, and the first phase adjustment value is positive.

[0129] In one example, the process of obtaining the target frequency ratio may include, but is not limited to: counting the total size of the circuit emulation packets received by the network device within the reference period, determining the transmission period based on the quotient of the total packet size and the configured original code stream rate, and determining the initial frequency ratio based on the quotient of the transmission period and the reference period. For example, the transmission period may represent the time required to transmit the data of the total packet size. Then, perform a low-pass filtering operation on the initial frequency ratio to obtain the target frequency ratio.

[0130] In one example, the second phase adjustment value may also be determined based on the target frequency ratio. Specifically, if the target frequency ratio indicates that the original code stream clock and the local reference clock differ by B fractional cycles within an adjustment unit period, the second phase adjustment value may be determined based on B and N; if the target frequency ratio is greater than 1, the second phase adjustment value may be negative, and if the target frequency ratio is less than 1, the second phase adjustment value may be positive.

[0131] Based on this, selecting a target clock signal from the target clock signals corresponding to all frequency dividers based on the obtained target phase may include, but is not limited to: adjusting the current phase of the clock selection unit based on the second phase adjustment value to obtain the target phase, and selecting the target clock signal corresponding to the frequency divider corresponding to the target phase.

[0132] In one example, a timing pulse signal corresponding to the reference period may also be generated based on the local reference clock signal, and the time interval between two adjacent timing pulse signals may be determined as the reference period.

[0133] In one example, the circuit emulation packets received by the network device may also be cached by the cache unit. When the total packet size of the circuit emulation packets in the cache unit is greater than the first threshold, the third phase adjustment value may be determined, and the third phase adjustment value may be negative. Based on this, the initial clock phase value may be adjusted based on the third phase adjustment value to obtain the target clock phase value. Alternatively, when the total packet size of the circuit emulation packets in the cache unit is less than the second threshold, the second threshold may be less than the first threshold, the fourth phase adjustment value may be determined, and the fourth phase adjustment value may be positive. Based on this, the initial clock phase value may be adjusted based on the fourth phase adjustment value to obtain the target clock phase value.

[0134] In one example, multiple historical phase adjustment values within a historical time may also be stored; among them, the multiple historical phase adjustment values are the first phase adjustment values generated within the historical time. Based on this, if the first phase adjustment value is not obtained at the current time, the first phase adjustment value is determined based on the stored multiple historical phase adjustment values, and the initial clock phase value is adjusted based on the first phase adjustment value to obtain the target clock phase value.

[0135] Based on the same inventive concept as the above method, an embodiment of the present application proposes a network device. Refer to Figure 7 As shown, the network device includes: a processor 71 and a machine-readable storage medium 72. The machine-readable storage medium 72 stores machine-executable instructions that can be executed by the processor 71; the processor 71 is configured to execute the machine-executable instructions to implement the adaptive clock recovery method disclosed in the above examples of the present application.

[0136] Based on the same application concept as the above method, an embodiment of the present application further provides a machine-readable storage medium, on which a number of computer instructions are stored. When the computer instructions are executed by a processor, the adaptive clock recovery method disclosed in the above examples of the present application can be implemented.

[0137] Among them, the above machine-readable storage medium can be any electronic, magnetic, optical or other physical storage device that can contain or store information, such as executable instructions, data, and so on. For example, the machine-readable storage medium can be: RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, storage drives (such as hard disk drives), solid-state drives, any type of storage disk (such as optical discs, DVDs, etc.), or similar storage media, or a combination thereof.

[0138] Based on the same application concept as the above method, an embodiment of the present application further provides a computer program product, which may include a computer program. When the computer program is executed by a processor, the adaptive clock recovery method disclosed in the above examples of the present application is implemented.

[0139] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0140] The above are only the embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. A network device, characterized in that, The network device includes: A phase modulation unit, configured to perform phase modulation on a local reference clock signal to obtain N initial clock signals with different phases, and input the N initial clock signals into N frequency dividers, where N is a positive integer greater than 1; For each frequency divider, if a first adjustment signal carrying an acquired first phase adjustment value is received, the initial clock phase value is adjusted based on the first phase adjustment value to obtain a target clock phase value, the initial clock signal is frequency-divided based on the target clock phase value to obtain a target clock signal, and the target clock signal is input into a clock selection unit; wherein, the initial clock phase value is determined based on the ratio relationship between the local reference clock frequency and the configured target clock frequency; wherein, if the first interface rate of data transmission of the network device is less than the second interface rate of data reception, the first phase adjustment value is used to make the target clock phase value advance relative to the initial clock phase value; if the first interface rate is greater than the second interface rate, the first phase adjustment value is used to make the target clock phase value lag behind the initial clock phase value; A clock selection unit, configured to select a target clock signal from the target clock signals corresponding to all frequency dividers based on the acquired target phase, and the target clock signal is used to control the interface rate of data transmission of the network device.

2. The device according to claim 1, wherein, The network device further includes: An adjustment calculation unit, configured to determine the first phase adjustment value based on the acquired target frequency ratio, and send the first phase adjustment value to an adjustment control unit; wherein, the target frequency ratio represents the frequency ratio between the original code stream clock and the local reference clock; if the target frequency ratio represents that the original code stream clock and the local reference clock differ by A integer cycles within the configured adjustment unit period, the first phase adjustment value is A; if the target frequency ratio is greater than 1, the first interface rate is less than the second interface rate, and the first phase adjustment value is negative; if the target frequency ratio is less than 1, the first interface rate is greater than the second interface rate, and the first phase adjustment value is positive; An adjustment control unit, configured to obtain the first phase adjustment value from the adjustment calculation unit and send the first adjustment signal carrying the first phase adjustment value to each frequency divider.

3. The device according to claim 2, wherein The adjustment calculation unit is further configured to determine a second phase adjustment value based on the target frequency ratio, and send the second phase adjustment value to the adjustment control unit; wherein, if the target frequency ratio represents that the original code stream clock and the local reference clock differ by B decimal cycles within the adjustment unit period, the second phase adjustment value is determined based on B and N; if the target frequency ratio is greater than 1, the second phase adjustment value is negative; if the target frequency ratio is less than 1, the second phase adjustment value is positive; The adjustment control unit is further configured to send a second adjustment signal carrying the second phase adjustment value to the clock selection unit; When the clock selection unit selects a target clock signal from the target clock signals corresponding to all frequency dividers based on the acquired target phase, it specifically is used for: adjusting the current phase of the clock selection unit based on the second phase adjustment value to obtain the target phase, and selecting the target clock signal corresponding to the frequency divider corresponding to the target phase.

4. The device according to claim 2, characterized in that, The network device further includes: A frequency offset calculation unit, configured to count the total size of circuit simulation packets received by the network device within a reference period, determine a transmission period based on the quotient of the total size of the packets and the configured original code stream rate, and determine an initial frequency ratio based on the quotient of the transmission period and the reference period; Wherein, the transmission period represents the time required to transmit data of the total size of the packets; Wherein, the initial frequency ratio is used to determine the target frequency ratio.

5. The device according to claim 4, wherein The frequency offset calculation unit is further configured to determine the initial frequency ratio as the target frequency ratio and send the target frequency ratio to the adjustment calculation unit; Alternatively, the network device further includes: a low-pass filter; The frequency offset calculation unit is further configured to send the initial frequency ratio to the low-pass filter; The low-pass filter is configured to perform a low-pass filtering operation on the initial frequency ratio to obtain a target frequency ratio and send the target frequency ratio to the adjustment calculation unit.

6. The device according to claim 4, characterized in that, The network device further includes: A timer, configured to generate a timing pulse signal corresponding to the reference period based on a local reference clock signal and send the timing pulse signal to the frequency offset calculation unit; wherein, the time interval between two adjacent timing pulse signals generated by the timer is the reference period; The frequency offset calculation unit is configured to receive the timing pulse signal output by the timer and determine the time interval between two adjacent timing pulse signals as the reference period.

7. The device according to claim 2, characterized in that, The network device further includes: A buffer unit, configured to buffer circuit simulation packets received by the network device; The adjustment control unit is further configured to, when the total size of circuit simulation packets in the buffer unit is greater than a first threshold, determine a third phase adjustment value, where the third phase adjustment value is negative, and send a third adjustment signal carrying the third phase adjustment value to each frequency divider, so that each frequency divider adjusts the initial clock phase value based on the third phase adjustment value to obtain a target clock phase value; When the total size of circuit simulation packets in the buffer unit is less than a second threshold, where the second threshold is less than the first threshold, determine a fourth phase adjustment value, where the fourth phase adjustment value is positive, and send a fourth adjustment signal carrying the fourth phase adjustment value to each frequency divider, so that each frequency divider adjusts the initial clock phase value based on the fourth phase adjustment value to obtain a target clock phase value.

8. The device according to claim 2, characterized in that, The adjustment control unit is further configured to store a plurality of historical phase adjustment values within a historical time; wherein, the plurality of historical phase adjustment values are first phase adjustment values sent by the adjustment calculation unit within the historical time. The adjustment control unit is further configured to, if the first phase adjustment value sent by the adjustment calculation unit is not received at the current time, determine the first phase adjustment value based on a plurality of stored historical phase adjustment values, and send a first adjustment signal carrying the first phase adjustment value to each frequency divider.

9. An adaptive clock recovery method, characterized in that, Applied to a network device, it includes: Phase-adjust the local reference clock signal to obtain N initial clock signals with different phases, and input the N initial clock signals into N frequency dividers, where N is a positive integer greater than 1; For each frequency divider of the network device, if a first adjustment signal carrying the obtained first phase adjustment value is received through the frequency divider, adjust the initial clock phase value based on the first phase adjustment value to obtain a target clock phase value, and divide the initial clock signal based on the target clock phase value to obtain a target clock signal; wherein, the initial clock phase value is determined based on the proportional relationship between the local reference clock frequency and the configured target clock frequency; wherein, if the first interface rate of data transmission of the network device is less than the second interface rate of data reception, the first phase adjustment value is used to make the target clock phase value ahead of the initial clock phase value; if the first interface rate is greater than the second interface rate, the first phase adjustment value is used to make the target clock phase value lag behind the initial clock phase value; Select a target clock signal from the target clock signals corresponding to all frequency dividers based on the obtained target phase, and the target clock signal is used to control the interface rate of data transmission of the network device.

10. The method according to claim 9, characterized in that, The obtaining process of the first phase adjustment value includes: determining the first phase adjustment value based on the obtained target frequency ratio; wherein, the target frequency ratio represents the frequency ratio between the original code stream clock and the local reference clock; if the target frequency ratio represents that the original code stream clock and the local reference clock differ by A integer cycles within the configured adjustment unit period, the first phase adjustment value is A; if the target frequency ratio is greater than 1, the first interface rate is less than the second interface rate, and the first phase adjustment value is negative; if the target frequency ratio is less than 1, the first interface rate is greater than the second interface rate, and the first phase adjustment value is positive; Wherein, the obtaining process of the target frequency ratio includes: counting the total size of circuit emulation packets received by the network device within a reference period, determining the transmission period based on the quotient of the total size of the packets and the configured original code stream rate, and determining the initial frequency ratio based on the quotient of the transmission period and the reference period; the transmission period represents the time required to transmit the data of the total size of the packets; Perform a low-pass filtering operation on the initial frequency ratio to obtain the target frequency ratio.

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