Flash memory and manufacturing method thereof
By using a high selection ratio wet process to protect the width of the first side wall during flash memory production, the problem of inaccurate control gate width caused by wet cleaning is solved, and the yield and process window of wafer acceptance test are improved.
Patent Information
- Application Number
- CN202510396999.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-07-04
AI Technical Summary
During the production process of flash memory, the wet cleaning process causes the side wall to narrow, affecting the width and resistance of the control gate, resulting in the failure of the wafer acceptance test.
The wet process is used to select the high selection ratio of the patterned hard mask layer and the silicon nitride layer of the first side wall to ensure that the width of the first side wall is not etched. By forming a combination of the first oxide layer, the silicon nitride layer and the second oxide layer, the side wall is protected from wet etching and ensuring the accurate width of the control gate.
Improves the yield of wafer acceptance tests, adds process windows, and provides a solution to remake the hard mask layer to ensure accurate resistance of the control gate.
Smart Images
Figure CN120264759A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a flash memory and a manufacturing method thereof. Background Art
[0002] Flash memory has become a research hotspot in non-volatile memories due to its advantages such as convenience, high storage density, and good reliability. With the development of technology and the storage requirements of various electronic products, flash memory is widely used in mobile and communication devices such as mobile phones, laptops, PDAs, and USB flash drives. Flash memory is a non-volatile memory, and its operating principle is to control the on / off of the gate channel by changing the critical voltage of the transistor or memory cell to achieve the purpose of storing data, so that the data stored in the memory will not be lost due to power interruption. Generally speaking, flash memory is of a split-gate structure, a stacked-gate structure, or a combination of the two structures. Due to its special structure, split-gate flash memory shows unique performance advantages during programming and erasing compared with stacked-gate flash memory. Therefore, the split-gate structure is widely used because of its high programming efficiency and the ability of the word line structure to avoid over-erasure.
[0003] Flash memory includes word lines, and sidewalls are distributed on both sides of the word lines. The control gate layer covered by the sidewalls is the width of the finally formed control gate. Therefore, the width of the sidewalls determines the width of the control gate. The hard mask layer covering the sidewall sidewalls is removed by a wet cleaning process. During the process of wet removing the hard mask layer, the sidewalls are also wet cleaned, resulting in the narrowing of the sidewalls, thus causing the shortening of the width of the control gate, an increase in the resistance value of the control gate, and the failure of the control gate-related parameter tests in the wafer acceptance test. Summary of the Invention
[0004] The purpose of the present invention is to provide a flash memory and a manufacturing method thereof, with a high selectivity ratio of the wet process for the patterned hard mask layer and the silicon nitride layer of the first sidewall, and the silicon nitride layer is basically not wet etched, ensuring the width of the first sidewall, and the width of the first sidewall determines the width of the control gate; thus ensuring that the widths of the control gate and the floating gate are more accurate, the resistance value of the control gate is accurate, improving the yield of the wafer acceptance test, and increasing the process window. A solution is provided to re-fabricate the hard mask layer if there are problems with the hard mask layer.
[0005] The present invention provides a manufacturing method of a flash memory, including:
[0006] Step S1, providing a substrate, the substrate including a storage area and a peripheral area; a floating gate layer, a spacer layer, a control gate layer, and a sacrificial layer are sequentially formed on the substrate; an opening is formed in the sacrificial layer, and first sidewalls are formed on both sides of the opening; the first sidewalls include a first oxide layer, a silicon nitride layer, and a second oxide layer sequentially formed on both sides of the opening;
[0007] Step S2: In the storage area, etch the control gate layer, the spacer layer, and the floating gate layer between the two first sidewalls to form an accommodation space, and form a word line in the accommodation space;
[0008] Step S3: Remove the sacrificial layer; remove the floating gate layer, the spacer layer, and the control gate layer from bottom to top in the peripheral area to expose the substrate;
[0009] Step S4: Sequentially form a peripheral oxide layer and a peripheral gate layer on the substrate in the peripheral area;
[0010] Step S5: Form a patterned hard mask layer, and use the patterned hard mask layer as a mask to etch the peripheral gate layer and the peripheral oxide layer to form a peripheral gate;
[0011] Step S6: Remove the patterned hard mask layer by a wet process. The wet process has a high selectivity to the patterned hard mask layer and the silicon nitride layer of the first sidewall to ensure the width of the first sidewall.
[0012] Further, both the first oxide layer and the silicon nitride layer are in an "L" shape.
[0013] Further, an anisotropic dry etching process is used to etch and remove the sacrificial layer, and the first oxide layer is consumed and removed during the process of removing the sacrificial layer.
[0014] Further, the material of the patterned hard mask layer includes: tetraethyl orthosilicate; the patterned hard mask layer is removed by wet etching with HF acid.
[0015] Further, Step S2 specifically includes:
[0016] Use the first sidewall as a mask to dry-etch the control gate layer and the spacer layer to expose the floating gate layer;
[0017] Form a second sidewall that covers the sidewalls of the spacer layer, the sidewalls of the control gate layer, and part of the sidewalls of the first sidewall;
[0018] Use the second sidewall as a mask to etch the floating gate layer to expose the substrate and form the accommodation space.
[0019] Further, after forming the word line in Step S2, it further includes: forming a word line isolation layer covering the word line.
[0020] Further, in Step S5, the peripheral gate is located above the channel region of the substrate and / or above the trench isolation.
[0021] Further, in step S5, after the graphitized hard mask layer is deposited too thinly or becomes too thin due to several wet cleans of other film layers, it can be completely removed and then a graphitized hard mask layer with an appropriate thickness is re-formed.
[0022] Further, after step S6, it further includes: using the first sidewall as a mask to etch the control gate layer, the spacer layer, and the floating gate layer to form a floating gate and a control gate located in the storage area.
[0023] The present invention also provides a flash memory, including:
[0024] A substrate, the substrate includes a storage area and a peripheral area; word lines are formed on the substrate of the storage area, and a floating gate, a spacer layer, a control gate, and a first sidewall are sequentially formed from bottom to top on both sides of the word lines; the first sidewall includes a second oxide layer and a silicon nitride layer sequentially formed on both sides of the word lines;
[0025] A peripheral gate is formed on the substrate of the peripheral area.
[0026] Compared with the prior art, the present invention has the following beneficial effects:
[0027] The present invention provides a flash memory and a manufacturing method thereof, including: providing a substrate, the substrate includes a storage area and a peripheral area; a floating gate layer, a spacer layer, a control gate layer, and a sacrificial layer are sequentially formed on the substrate; an opening is formed in the sacrificial layer, and a first sidewall is formed on both sides of the opening; the first sidewall includes a first oxide layer, a silicon nitride layer, and a second oxide layer sequentially formed on both sides of the opening; in the storage area, the control gate layer, the spacer layer, and the floating gate layer between the two first sidewalls are etched to form an accommodation space, and a word line is formed in the accommodation space; the sacrificial layer is removed; the floating gate layer, the spacer layer, and the control gate layer in the peripheral area from bottom to top are removed to expose the substrate; a peripheral oxide layer and a peripheral gate layer are sequentially formed on the substrate of the peripheral area; a graphitized hard mask layer is formed, and the peripheral gate layer and the peripheral oxide layer are etched using the graphitized hard mask layer as a mask to form a peripheral gate.
[0028] The first sidewall of the present invention includes a first oxide layer, a silicon nitride layer, and a second oxide layer formed in sequence on both sides of the opening. The patterned hard mask layer is removed by a wet process, and the wet process has a high selectivity ratio for the patterned hard mask layer and the silicon nitride layer of the first sidewall. The silicon nitride layer is basically not etched by the wet process, ensuring the width of the first sidewall. The width of the first sidewall determines the width of the final control gate, thereby ensuring that the widths of the control gate and the floating gate are more accurate, the resistance value of the control gate is accurate, improving the yield of wafer acceptance testing and increasing the process window. Moreover, if the hard mask layer is deposited too thin or becomes too thin due to several wet cleanings of other film layers, it can be completely removed by wet cleaning and then a hard mask layer with a suitable thickness can be re-formed. During the process of completely removing the unqualified hard mask layer by wet cleaning, due to the protection of the silicon nitride layer of the first sidewall, the width of the first sidewall is ensured, providing a solution for remaking the hard mask layer if there are problems with the hard mask layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 FIG. is a schematic flow chart of a method for manufacturing a flash memory according to an embodiment of the present invention.
[0030] Figure 2 FIG. is a schematic diagram after forming a sacrificial layer in the method for manufacturing a flash memory according to an embodiment of the present invention.
[0031] Figure 3 FIG. is a schematic diagram after forming a peripheral gate layer in the method for manufacturing a flash memory according to an embodiment of the present invention.
[0032] Figure 4 FIG. is a schematic diagram after forming a hard mask layer in the method for manufacturing a flash memory according to an embodiment of the present invention.
[0033] Figure 5 FIG. is a schematic diagram after forming a peripheral gate in the method for manufacturing a flash memory according to an embodiment of the present invention.
[0034] Figure 6 FIG. is a schematic diagram after forming a floating gate and a control gate in the method for manufacturing a flash memory according to an embodiment of the present invention.
[0035] Among them, the reference numerals are as follows:
[0036] 10 - Substrate; 11 - Gate oxide layer; 12 - Floating gate layer; 120 - Floating gate; 13 - Spacer layer; 14 - Control gate layer; 140 - Control gate; 15 - Sacrificial layer; 16 - First sidewall; 161 - First oxide layer; 162 - Silicon nitride layer; 163 - Second oxide layer; S - Trench isolation; 17 - Second sidewall; 18 - Word line oxide layer; 19 - Word line; 20 - Word line isolation layer; 21 - Peripheral oxide layer; 22 - Peripheral gate layer; 220 - Peripheral gate; 23 - Hard mask layer; I - Storage area; II - Peripheral area. DETAILED DESCRIPTION OF THE INVENTION
[0037] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are in a very simplified form and use non-precise ratios, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention.
[0038] For ease of description, some embodiments of the present application may use spatial relative terms such as "above...", "below...", "top", "bottom", etc. to describe the relationship between one element or component and another (or other) element or component as shown in the respective drawings of the embodiments. It should be understood that in addition to the orientations described in the drawings, spatial relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawing is flipped, an element or component described as "below" or "beneath" other elements or components will subsequently be positioned "above" or "over" other elements or components. The terms "first", "second", etc. in the following text are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It should be understood that these terms can be replaced when appropriate.
[0039] An embodiment of the present invention provides a method for manufacturing a flash memory, as Figure 1 shown, including:
[0040] Step S1: Provide a substrate, the substrate including a storage area and a peripheral area; sequentially form a floating gate layer, a spacer layer, a control gate layer, and a sacrificial layer on the substrate; an opening is formed in the sacrificial layer, and first sidewalls are formed on both sides of the opening; the first sidewalls include a first oxide layer, a silicon nitride layer, and a second oxide layer sequentially formed on both sides of the opening;
[0041] Step S2: In the storage area, etch the control gate layer, the spacer layer, and the floating gate layer between the two first sidewalls to form a receiving space, and form a word line in the receiving space;
[0042] Step S3: Remove the sacrificial layer; remove the floating gate layer, the spacer layer, and the control gate layer from bottom to top in the peripheral area to expose the substrate;
[0043] Step S4: Sequentially form a peripheral oxide layer and a peripheral gate layer on the substrate in the peripheral area;
[0044] Step S5: Form a patterned hard mask layer, and use the patterned hard mask layer as a mask to etch the peripheral gate layer and the peripheral oxide layer to form a peripheral gate;
[0045] Step S6: Remove the patterned hard mask layer by a wet process, and the wet process has a high selectivity to the patterned hard mask layer and the silicon nitride layer of the first sidewall to ensure the width of the first sidewall.
[0046] The following will Figures 2 to 6 detail the steps of the manufacturing method of the flash memory according to the embodiments of the present invention.
[0047] As Figure 2 shown, in step S1, a substrate 10 is provided, and the substrate 10 includes a storage region I and a peripheral region II; a gate oxide layer 11, a floating gate layer 12, a spacer layer 13, a control gate layer 14, and a sacrificial layer 15 are sequentially formed on the substrate 10; an opening is formed in the sacrificial layer 15, and the opening penetrates the sacrificial layer 15 to expose the control gate layer 14, and first sidewalls 16 are formed on both sides of the opening. The first sidewalls 16 include a first oxide layer 161, a silicon nitride layer 162, and a second oxide layer 163 sequentially formed on the sidewalls of the opening. Both the first oxide layer 161 and the silicon nitride layer 162 are in an "L" shape. The spacer layer 13 is used for electrically isolating the floating gate layer 12 and the control gate layer 14.
[0048] In this embodiment, the material of the substrate 10 may be silicon. In other embodiments, the material of the substrate 10 includes silicon carbide, silicon germanium, a multi-semiconductor material composed of group III-V elements, silicon on insulator, or germanium on insulator. Among them, the multi-semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP. The material of the gate oxide layer 11 includes silicon oxide; the materials of the floating gate layer 12 and the control gate layer 14 both include polysilicon. The processes for forming the floating gate layer 12 and the control gate layer 14 can both be deposition processes, such as plasma enhanced chemical vapor deposition process, low pressure chemical vapor deposition process, or sub-atmospheric chemical vapor deposition process. The spacer layer 13 is, for example, an ONO layer (bottom oxide layer, silicon nitride layer, and top oxide layer). The material of the sacrificial layer 15 includes one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the sacrificial layer 15 includes silicon nitride.
[0049] In step S2, as Figure 3As shown, in the storage region I, the control gate layer 14, the spacer layer 13, and the floating gate layer 12 between the first sidewalls on both sides are etched to form an accommodation space, and polysilicon is filled in the accommodation space to form the word line 19; a word line isolation layer 20 covering the top of the word line 19 is formed. Specifically, the control gate layer 14 and the spacer layer 13 are dry-etched using the first sidewall as a mask to expose the floating gate layer 12. The second sidewall 17 is formed, and the second sidewall 17 covers the sidewalls of the spacer layer 13, the sidewalls of the control gate layer 14, and the sidewalls of a part of the first sidewall 16. The floating gate layer 12 and the floating gate oxide layer 11 are etched using the second sidewall 17 as a mask to expose the substrate 10, and the accommodation space is surrounded by the second sidewalls 17 on both sides, the sidewalls of the etched floating gate layer 12, and the substrate 10; a word line oxide layer 18 is formed, and the word line oxide layer 18 covers the sidewalls of the second sidewall 17, the sidewalls of the floating gate layer 12, and the substrate 10. Polysilicon is filled in the accommodation space after the word line oxide layer 18 is formed to form the word line 19. The second sidewall 17 is used for electrically isolating the word line 19 and the control gate layer 14. A word line isolation layer 20 covering the word line 19 is formed.
[0050] Step S3, as Figure 2 and Figure 3 shown, the sacrificial layer 15 is removed; the floating gate layer 12, the spacer layer 13, and the control gate layer 14 from bottom to top in the peripheral region II are removed to expose the substrate 10. The sacrificial layer 15 can be etched and removed by an anisotropic dry etching process, and the sacrificial layer 15 on the substrate 10 in the storage region I and the peripheral region II is removed. The first sidewall 16 includes a first oxide layer 161, a silicon nitride layer 162, and a second oxide layer 163. The first oxide layer 161 serves as a protective layer, and the first oxide layer 161 is etched and consumed during the process of removing the sacrificial layer 15.
[0051] Step S4, as Figure 3 shown, an outer peripheral oxide layer 21 and an outer peripheral gate layer 22 are sequentially formed on the substrate 10 in the peripheral region II. A trench isolation S can also be formed in the substrate 10 in the peripheral region II.
[0052] Step S5, as Figure 4 and Figure 5As shown, a patterned hard mask layer 23 is formed. Using the patterned hard mask layer 23 as a mask, the peripheral gate layer 22 and the peripheral oxide layer 21 are etched to form a peripheral gate 220. The patterned hard mask layer 23 covers the surface of the control gate layer 14 in the storage region I, the sidewalls of the silicon nitride layer of the first sidewall, and the surface of the word line isolation layer 20; the patterned hard mask layer 23 also covers the region in the peripheral gate layer 22 corresponding to the peripheral gate 220. Windows are formed in the patterned hard mask layer 23, and the windows expose the regions on both sides of the peripheral gate 220 in the peripheral gate layer 22. The patterned hard mask layer 23 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. Using the patterned hard mask layer 23 as a mask, the peripheral gate layer 22 and the peripheral oxide layer 21 exposed by the windows in the peripheral region II are etched away to form a peripheral gate 220. The material of the patterned hard mask layer 23 includes: tetraethyl orthosilicate (TEOS).
[0053] Step S6, as Figure 4 and Figure 5 shown, the patterned hard mask layer 23 is removed by a wet process. The wet process has a high selectivity to the patterned hard mask layer 23 and the silicon nitride layer 162 of the first sidewall to ensure the width of the first sidewall. After the patterned hard mask layer 23 is deposited too thinly or becomes too thin due to several wet cleanings of other film layers and is all removed, a patterned hard mask layer with a suitable thickness is formed again. The patterned hard mask layer 23 can be removed by wet etching with HF acid. During the process of removing the patterned hard mask layer 23 by wet etching, the silicon nitride layer 162 of the first sidewall protects the width of the first sidewall, ensuring that the widths of the control gate and the floating gate are more accurate.
[0054] As Figure 5 and Figure 6 shown, after step S6, it further includes: using the first sidewall as a mask, etching the control gate layer 14, the spacer layer 13, and the floating gate layer 12 to form a floating gate 120 and a control gate 140 in the storage region I.
[0055] The present invention also provides a flash memory, as Figure 6 shown, including:
[0056] A substrate 10, the substrate 10 includes a storage region I and a peripheral region II; a word line 19 is formed on the substrate 10 in the storage region I, and a floating gate 120, a spacer layer, a control gate 140, and a first sidewall are sequentially formed from bottom to top on both sides of the word line 19; the first sidewall includes a second oxide layer and a silicon nitride layer formed on both sides of the word line in sequence;
[0057] A peripheral gate 220 is formed on the substrate in the peripheral region II. The peripheral gate 220 is located above the channel region of the substrate 10 and / or above the trench isolation S.
[0058] In summary, the present invention provides a flash memory and a manufacturing method thereof, including: providing a substrate, the substrate including a storage region and a peripheral region; sequentially forming a floating gate layer, a spacer layer, a control gate layer, and a sacrificial layer on the substrate; forming an opening in the sacrificial layer, and forming first sidewalls on both sides of the opening; the first sidewalls including a first oxide layer, a silicon nitride layer, and a second oxide layer sequentially formed on both sides of the opening; in the storage region, etching the control gate layer, the spacer layer, and the floating gate layer between the two first sidewalls to form a receiving space, and forming a word line in the receiving space; removing the sacrificial layer; removing the floating gate layer, the spacer layer, and the control gate layer from bottom to top in the peripheral region to expose the substrate; sequentially forming a peripheral oxide layer and a peripheral gate layer on the substrate in the peripheral region; forming a patterned hard mask layer, and etching the peripheral gate layer and the peripheral oxide layer using the patterned hard mask layer as a mask to form a peripheral gate.
[0059] The first sidewalls of the present invention include a first oxide layer, a silicon nitride layer, and a second oxide layer sequentially formed on both sides of the opening. The patterned hard mask layer is removed by a wet process, and the wet process has a high selectivity ratio for the patterned hard mask layer and the silicon nitride layer of the first sidewalls. The silicon nitride layer is basically not etched by the wet process, ensuring the width of the first sidewalls. The width of the first sidewalls determines the width of the final control gate; thus ensuring that the widths of the control gate and the floating gate are more accurate, the resistance value of the control gate is accurate, improving the yield of the wafer acceptance test, increasing the process window. Moreover, if the hard mask layer is deposited too thin or becomes too thin due to several wet cleanings of other film layers, it can be completely removed by wet cleaning and then a hard mask layer with a suitable thickness can be re-formed. During the process of completely removing the unqualified hard mask layer by wet cleaning, due to the protection of the silicon nitride layer of the first sidewalls, the width of the first sidewalls is ensured; providing a solution for re-making the hard mask layer if there are problems with the hard mask layer.
[0060] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the methods disclosed in the embodiments, since they correspond to the devices disclosed in the embodiments, the description is relatively simple. For the relevant parts, refer to the description in the method part.
[0061] The above description is only a description of the preferred embodiments of the present invention, and does not limit any scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes, and decorations made to the above embodiments according to the technical essence of the present invention without departing from the technical solutions of the present invention all belong to the protection scope of the technical solutions of the present invention.
Claims
1. A manufacturing method of a flash memory, characterized in that, Including: Step S1: Provide a substrate, the substrate including a storage area and a peripheral area; a floating gate layer, a spacer layer, a control gate layer, and a sacrificial layer are sequentially formed on the substrate; an opening is formed in the sacrificial layer, and first sidewalls are formed on both sides of the opening; the first sidewalls include a first oxide layer, a silicon nitride layer, and a second oxide layer sequentially formed on both sides of the opening. Step S2: In the storage area, etch the control gate layer, the spacer layer, and the floating gate layer between the first sidewalls on both sides to form an accommodation space, and form a word line in the accommodation space. Step S3: Remove the sacrificial layer. Remove the floating gate layer, the spacer layer, and the control gate layer from bottom to top in the peripheral area to expose the substrate. Step S4: Sequentially form a peripheral oxide layer and a peripheral gate layer on the substrate in the peripheral area. Step S5: Form a patterned hard mask layer, and use the patterned hard mask layer as a mask to etch the peripheral gate layer and the peripheral oxide layer to form a peripheral gate. Step S6: Remove the patterned hard mask layer by a wet process, the wet process having a high selectivity to the silicon nitride layer of the patterned hard mask layer and the first sidewalls to ensure the width of the first sidewalls.
2. The method for manufacturing a flash memory according to claim 1, wherein Both the first oxide layer and the silicon nitride layer are in an "L" shape.
3. The method for manufacturing a flash memory according to claim 1, wherein In step S3, an anisotropic dry etching process is used to etch and remove the sacrificial layer, and the first oxide layer is consumed and removed during the process of removing the sacrificial layer.
4. The method for manufacturing a flash memory according to claim 1, wherein The material of the patterned hard mask layer includes: tetraethyl orthosilicate; the patterned hard mask layer is removed by wet etching with HF acid.
5. The method for manufacturing a flash memory according to claim 1, wherein Step S2 specifically includes: Dry-etch the control gate layer and the spacer layer using the first sidewalls as a mask to expose the floating gate layer. Form second sidewalls, the second sidewalls covering the sidewalls of the spacer layer, the sidewalls of the control gate layer, and part of the sidewalls of the first sidewalls. Etch the floating gate layer using the second sidewalls as a mask to expose the substrate and form the accommodation space.
6. The method for manufacturing a flash memory according to claim 1, wherein After forming the word line in step S2, further include: forming a word line isolation layer covering the word line.
7. The method for manufacturing a flash memory according to claim 1, wherein In step S5, the peripheral gate is located above the channel region of the substrate and / or above the trench isolation.
8. The method for manufacturing a flash memory according to claim 1, wherein In step S5, if the patterned hard mask layer is deposited too thinly or becomes too thin due to wet cleaning of several other film layers, it can be completely removed and then a patterned hard mask layer with a suitable thickness is formed again.
9. The method for manufacturing a flash memory according to claim 1, wherein After step S6, it further includes: using the first sidewall as a mask to etch the control gate layer, the spacer layer, and the floating gate layer to form a floating gate and a control gate located in the storage region.
10. A flash memory, characterized in that, It includes: a substrate, the substrate including a storage region and a peripheral region; a word line is formed on the substrate of the storage region, and a floating gate, a spacer layer, a control gate, and a first sidewall are sequentially formed from bottom to top on both sides of the word line; the first sidewall includes a second oxide layer and a silicon nitride layer sequentially formed on both sides of the word line; a peripheral gate is formed on the substrate of the peripheral region.