Method for forming lightly doped drain region

Abstract

The invention provides a method for forming a lightly doped drain region, which comprises the following steps of: forming a hard mask structure on the surface of a semiconductor substrate, defining a doped well region through a selective patterning process, and forming a doped well in the doped well region; forming a first side wall mask on the vertical side wall of the hard mask structure, completing the injection of a lightly doped drain region and forming a self-aligned channel at the same time; a second side wall mask is formed on the side wall, deviating from the hard mask structure, of the first side wall mask, heavily doped drain region injection is completed, and a self-aligned lightly doped drain region is formed at the same time; and removing the hard mask structure, the first side wall mask and the second side wall mask. According to the invention, the requirement on the process capability of photoetching equipment is reduced, the overlay error is avoided, the symmetry of the prepared lightly doped drain region can be ensured, the process complexity is reduced, and the cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor chip manufacturing processes, and particularly relates to a method for forming a lightly doped drain region. Background Art

[0002] With the continuous improvement of the integration level of silicon carbide power chips, reducing the device size of silicon carbide MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors, also known as metal-oxide-semiconductor field-effect transistors, abbreviated as MOS transistors) is an inevitable development trend in the integrated circuit industry. In order to alleviate problems such as short-channel effects caused by the reduction of device size, forming a lightly doped drain region between the source / drain and the channel is an effective solution. However, on the premise of reducing the device size, accurately defining the structure of the lightly doped drain region between the source / drain doping region and the channel region poses great challenges to the minimum exposure size and overlay accuracy of the lithography process.

[0003] In the prior art, in the manufacture of MOS transistors, a doped well is first formed by lithography and ion implantation, and then a lightly doped drain (LDD, Light-Doped Drain) is formed through sidewalls and ion implantation. For the subsequent production of the source / drain regions, another lithography and ion implantation are required. The prior art has the following disadvantages: 1. The source / drain regions are formed by the lithography process. On the one hand, when the size is reduced, a very high requirement is imposed on the exposure line width of the lithography process, increasing the cost of lithography equipment. On the other hand, the lithography process will inevitably bring overlay errors, affecting the symmetry of the source / drain region structure and the electrical performance of the device. 2. Defining the pattern of the lightly doped drain region by the lithography process will require an additional lithography mask, and when the size of the source / drain region needs to be changed, the lithography mask needs to be replaced, increasing the additional cost. 3. The manufacturing method has a cumbersome process. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for forming a lightly doped drain region. The method of the present invention not only reduces the requirements for the process capabilities of lithography equipment, avoids the overlay errors introduced by the lithography process, but also can ensure the symmetry of the prepared lightly doped drain region, avoid affecting the electrical performance of the device, and can also reduce process complexity and cost.

[0005] The present invention provides a method for forming a lightly doped drain region, which is characterized by including the following steps: Step S1, forming a hard mask structure on the surface of the semiconductor substrate, defining a doped well region through a selective patterning process, and forming a doped well in the doped well region; Step S2, form a first sidewall mask on the vertical sidewalls of the hard mask structure, complete the lightly doped drain region implantation and simultaneously form a self-aligned channel; Step S3, form a second sidewall mask on the sidewall of the first sidewall mask facing away from the hard mask structure, complete the heavily doped drain region implantation and simultaneously form a self-aligned lightly doped drain region; Step S4, remove the hard mask structure, the first sidewall mask and the second sidewall mask.

[0006] Further, the specific steps of Step S1 include: Step S1-1, deposit a first hard mask on the surface of the semiconductor substrate, and the first hard mask serves as the hard mask structure; Step S1-2, define a doped well region on the first hard mask through photolithography and dry etching; Step S1-3, perform doping in the doped well region through ion implantation to form a doped well.

[0007] Further, in Step S1-1, before forming the first hard mask on the surface of the semiconductor substrate, first deposit a protective film on the semiconductor surface, and the protective film and the first hard mask serve as the hard mask structure.

[0008] Further, the material of the protective film is silicon dioxide, and the thickness of the protective film is 90 nm - 110 nm.

[0009] Further, the material of the first hard mask is polysilicon.

[0010] Further, the specific steps of Step S2 include: Step S2-1, deposit a second hard mask on the surface of the stacked structure formed in Step S1; Step S2-2, through dry etching of the second hard mask, form a first sidewall mask on the vertical sidewalls of the hard mask structure and define a lightly doped region; Step S2-3, perform light doping in the lightly doped region through ion implantation to form a lightly doped drain region, and simultaneously form a self-aligned channel.

[0011] Further, the specific steps of Step S3 include: Step S3-1, deposit a third hard mask on the surface of the stacked structure formed in Step S2; Step S3-2, through dry etching of the third hard mask, form a second sidewall mask on the sidewall of the first sidewall mask facing away from the hard mask structure and define a source / drain doping region; Step S3-3, perform heavy doping in the source / drain doping region through ion implantation to form a source / drain region, and simultaneously form a self-aligned lightly doped drain region.

[0012] Further, both the first sidewall mask and the second sidewall mask are made of polysilicon.

[0013] Further, the thickness of the second sidewall mask is determined according to the size of the self-aligned lightly doped drain region.

[0014] Further, in step S4, the hard mask structure, the first sidewall mask, and the second sidewall mask are removed by wet etching.

[0015] Advantages of the present invention: In the method for forming a lightly doped drain region of the present invention, a dual self-aligned mask is used to prepare a self-aligned lightly doped drain region, which can ensure the symmetry of the prepared self-aligned lightly doped drain region, avoid affecting the electrical performance of the device, and when the structure design of the self-aligned lightly doped drain region is changed, it is adjusted by changing the thickness of the deposited hard mask, and the process operability is simpler and the cost is lower; since there is no need to use a lithography process to prepare the self-aligned lightly doped drain region, not only the requirement for the process ability of the lithography equipment is reduced, the overlay error introduced by the lithography process is avoided, but also a lithography mask can be saved, saving costs; in addition, all the hard masks only need to be removed in the last step of the process, reducing the process complexity and further reducing the process manufacturing cost. Description of the drawings

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0017] Figure 1 Shows a flowchart of a method for forming a lightly doped drain region in an embodiment of the present invention; Figure 2 Shows a specific flowchart of step S1 in an embodiment of the present invention; Figure 3 Shows a specific flowchart of step S2 in an embodiment of the present invention; Figure 4 Shows a specific flowchart of step S3 in an embodiment of the present invention; Figure 5 Shows a flowchart of a method for forming a lightly doped drain region in an N-type substrate in an embodiment of the present invention; Figure 6 Shows a structural diagram after step 1 is completed in an embodiment of the present invention; Figure 7 Shows a structural diagram after step 2 is completed in an embodiment of the present invention; Figure 8 Shows a structural diagram after step 3 is completed in an embodiment of the present invention; Figure 9 Shows the structural diagram after step 4 is completed in an embodiment of the present invention; Figure 10 Shows the structural diagram after step 5 is completed in an embodiment of the present invention; Figure 11 Shows the structural diagram after step 6 is completed in an embodiment of the present invention; Figure 12 Shows the structural diagram after step 7 is completed in an embodiment of the present invention; Figure 13 Shows the structural diagram after step 8 is completed in an embodiment of the present invention; Figure 14 Shows the structural diagram after step 9 is completed in an embodiment of the present invention; Figure 15 Shows the structural diagram after step 10 is completed in an embodiment of the present invention. Detailed implementation manners

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0019] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and the like used in the specification and claims of the patent application of the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components.

[0020] This embodiment provides a method for forming a lightly doped drain region, including the following steps: Step S1, forming a hard mask structure on the surface of a semiconductor substrate, defining a doped well region through a selective patterning process, and forming a doped well in the doped well region; Step S2, forming a first sidewall mask on the vertical sidewalls of the hard mask structure, completing the lightly doped drain region implantation and simultaneously forming a self-aligned channel; Step S3, forming a second sidewall mask on the sidewall of the first sidewall mask facing away from the hard mask structure, completing the heavily doped drain region implantation and simultaneously forming a self-aligned lightly doped drain region; Step S4, removing the hard mask structure, the first sidewall mask, and the second sidewall mask.

[0021] When forming the lightly doped drain region and the source / drain regions, the present invention adopts a self-alignment process, which can reduce the requirements for the process capabilities of lithography equipment, avoid the overlay error introduced by the lithography process, and the self-alignment sidewall mask has high structural symmetry, which can ensure the symmetry of the prepared self-aligned lightly doped drain region and avoid affecting the electrical performance of the device. Since the dual self-alignment process does not require defining the self-aligned lightly doped drain region pattern through the lithography process, one lithography mask can be saved, thus saving costs. The size of the self-aligned lightly doped drain region can be adjusted by changing the thickness of the deposited hard mask, without the need to adjust the lithography mask size. When there is a structural design change, the process operability is simpler and the cost is lower. And the present invention only needs to remove all hard masks in the last step, reducing the process complexity and further lowering the process manufacturing cost.

[0022] As Figure 1 shown, this embodiment provides a method for forming a lightly doped drain region, including the following steps: Step S1, forming a hard mask structure on the surface of the semiconductor substrate 10, defining a doped well region through a selective patterning process, and forming a doped well in the doped well region.

[0023] In some examples, as Figure 2 shown, step S1 specifically includes: Step S1-1, depositing a first hard mask 20 on the surface of the semiconductor substrate 10, and the first hard mask 20 serves as the hard mask structure.

[0024] In some examples, before depositing a first hard mask 20 on the surface of the semiconductor substrate 10, a protective film 30 is first deposited on the surface of the semiconductor substrate 10, and the protective film 30 and the first hard mask 20 serve as the hard mask structure. The purpose of the protective film 30 is to protect the semiconductor substrate 10 and avoid damaging the surface of the semiconductor substrate 10 during the subsequent dry etching process.

[0025] Specifically, the materials of the protective film 30 and the first hard mask 20 are both silicon dioxide (SiO2) or silicon nitride (Si3N4), or polysilicon. In some examples, the material of the protective film 30 is silicon dioxide and the material of the second hard mask 20 is polysilicon.

[0026] In some examples, the thickness of the second hard mask 20 is greater than the thickness of the protective film 30. Specifically, the thickness of the protective film 30 is 90nm - 110nm, and the optimal value is 100nm. A protective film 30 with a thickness of about 100nm can control the penetration of impurity ions through the protective film 30 and reach the target depth and target doping concentration through the adjustment of dose and energy.

[0027] Specifically, the semiconductor substrate 10 is a P-type substrate or an N-type substrate.

[0028] Specifically, for the second hard mask 20 and the protective mask 30, methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. can be used to deposit a layer of hard mask material on the surface of the semiconductor substrate 10. For example, silicon nitride is deposited using low-pressure chemical vapor deposition (LPCVD) technology.

[0029] Step S1-2: Define the doped well region on the first hard mask 20 through photolithography and dry etching.

[0030] During ion implantation or etching operations, the hard mask structure can prevent damage to the areas that do not need to be processed, ensuring the accuracy of the region where the doped well is prepared.

[0031] In some examples, after step S1-2, it is also necessary to remove the photoresist. For example, after dry etching is completed, methods such as plasma ashing or wet cleaning are used to remove the photoresist. At this time, the pattern of the doped well remains on the first hard mask 20.

[0032] Step S1-3: Perform doping in the doped well region through ion implantation to form a doped well.

[0033] In some examples, in step S1-3, when the semiconductor substrate 10 is a P-type substrate, the doped well is an N well; when the semiconductor substrate 10 is an N-type substrate, the doped well is a P well.

[0034] Specifically, doping is performed in the doped well region through ion implantation to form a doped well. For example, in an N-type substrate, P-type impurities such as boron (B) or aluminum (Al) are implanted. By precisely controlling the dose and energy, they can penetrate the first hard mask 30 and reach the required doping concentration to form a P well. Or in a P-type substrate, N-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As) are implanted. By precisely controlling the dose and energy, they can penetrate the protective mask 30 and reach the required doping concentration to form an N well.

[0035] Step S2: Form a first sidewall mask 41 on the vertical sidewalls of the hard mask structure to complete the lightly doped drain region implantation and simultaneously form a self-aligned channel.

[0036] In some examples, as Figure 3 shown, step S2 specifically includes: Step S2-1: Deposit a second hard mask 40 on the surface of the stacked structure formed in step S1.

[0037] Specifically, deposit a second hard mask 40 on the surface of the stacked structure ( Figure 8 the structure shown) formed in step S1-3.

[0038] Specifically, the thickness of the second hard mask 40 is determined according to the self-aligned channel size. When it is necessary to change the self-aligned channel size, only the thickness of the second hard mask 40 needs to be changed.

[0039] Specifically, the material of the second hard mask 40 is silicon dioxide (SiO2) or silicon nitride (Si3N4), or polysilicon. In some examples, the material of the second hard mask 40 is polysilicon.

[0040] Specifically, methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. can be used to deposit a layer of polysilicon on the surface of the stacked structure formed in step S1-3 ( Figure 8 the structure shown).

[0041] In step S2-2, by dry-etching the second hard mask 40, a first sidewall mask 41 is formed on the vertical sidewalls of the hard mask structure to define the lightly doped region.

[0042] In step S2-3, a lightly doped drain region 60 (LDD, Lightly Doped Drain) is formed by ion implantation in the lightly doped region, and at the same time, a self-aligned channel is formed.

[0043] In some examples, for an N-type MOSFET, LDD usually uses nitrogen (N) or phosphorus (P) as a dopant, while for a P-type MOSFET, aluminum (Al) is used as a dopant. A shallow junction lightly doped drain region is formed in the lightly doped region by low-energy and low-dose ion implantation, and the energy and dose need to meet the requirement of being able to penetrate the first hard mask 30 and reach a predetermined depth and doping concentration.

[0044] In step S3, a second sidewall mask 51 is formed on the sidewall of the first sidewall mask 41 facing away from the hard mask structure 20 (that is, as Figure 13 shown, a second sidewall mask 51 is formed on the outer sidewall of the first sidewall mask 41), completing the heavy-doped drain region implantation and simultaneously forming a self-aligned lightly doped drain region 80.

[0045] In some examples, step S3 specifically includes: In step S3-1, a third hard mask 50 is deposited on the surface of the stacked structure formed in step S2.

[0046] Specifically, a third hard mask 50 is deposited on the surface of the stacked structure formed in step S2-3 ( Figure 11 the structure shown).

[0047] Specifically, the thickness of the third hard mask 50 is determined according to the size of the self-aligned lightly doped drain region 80, that is, the thickness of the third hard mask 50 is the same as the length of the self-aligned lightly doped drain region 80. When it is necessary to change the size of the self-aligned lightly doped drain region 80, only the thickness of the third hard mask 50 needs to be changed, without adjusting by modifying the size of the photomask. Therefore, the process operability is simpler and the cost is lower.

[0048] Specifically, the material of the third hard mask 50 is silicon dioxide (SiO2), silicon nitride (Si3N4), or polysilicon. In some examples, the material of the third hard mask 50 is polysilicon.

[0049] Specifically, methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD) are used to deposit a layer of polysilicon on the surface of the stacked structure ( Figure 11 the structure shown) formed in step S2-3.

[0050] In step S3-2, the third hard mask 50 is dry-etched to form a second sidewall mask 51 on the sidewall of the first sidewall mask 41 facing away from the hard mask structure (that is, as shown in Figure 13 the figure, a second sidewall mask 51 is formed on the outer sidewall of the first sidewall mask 41), defining the source-drain doping region.

[0051] In step S3-3, the source-drain region 70 is heavily doped by ion implantation in the source-drain doping region, and at the same time, the self-aligned lightly doped drain region 80 is formed.

[0052] In some examples, for the N-type source-drain region, N-type doping ions such as nitrogen (N), phosphorus (P), or arsenic (As) are used, and the source-drain region is formed in the source-drain doping region by ion implantation with a certain energy and high dose. For the P-type source-drain region, P-type doping ions such as aluminum (Al) are used to form the source-drain region in the source-drain doping region by ion implantation with a certain energy and high dose.

[0053] In step S4, the hard mask structure, the first sidewall mask 41, and the second sidewall mask 51 are removed.

[0054] In some examples, the hard mask structure, the first sidewall mask 41, and the second sidewall mask 51 are removed by wet etching. Specifically, when the hard mask structure in step S1 only includes the first hard mask 20, the first hard mask 20, the first sidewall mask 41, and the second sidewall mask 51 are removed by wet etching; when the hard mask structure in step S1 includes the first hard mask 20 and the protective film 30, the first hard mask 20, the protective film 30, the first sidewall mask 41, and the second sidewall mask 51 are removed by wet etching. That is, all hard masks are removed by wet etching in step S4. Using wet etching will not damage the surface of the semiconductor substrate.

[0055] Specifically, taking the preparation of SiC NMOSFET as an example, as Figure 5 shown, the specific process of preparing the lightly doped drain region is as follows: Step 1: Using chemical vapor deposition, deposit a 100-nm-thick protective film 30 and a 2000-nm-thick first hard mask 20 on the surface of the N-type substrate 10 in sequence. After completing Step 1, the structure is as Figure 6 shown.

[0056] Step 2: Define the P-well region on the first hard mask 20 through photolithography and dry etching. After the etching is completed, remove the photoresist using methods such as plasma ashing or wet cleaning. At this time, the pattern of the doped well is retained on the first hard mask 20. After completing Step 2, the structure is as Figure 7 shown, and there is still a protective film 30 above the N-type substrate 10 corresponding to the P-well region.

[0057] Step 3: Perform P-type doping on the P-well region by ion implanting aluminum (Al) ions to form the P-well. After completing Step 3, the structure is as Figure 8 shown.

[0058] Step 4: Using chemical vapor deposition, deposit a second hard mask 40 on the surface of the stacked structure formed in Step S3 ( Figure 8 the structure shown). After completing Step 4, the structure is as Figure 9 shown.

[0059] Step 5: Use dry etching to form a first sidewall mask 41 on the second hard mask 40 to define the lightly doped region. After completing Step 5, the structure is as Figure 10 shown, and there is still a protective film 30 above the N-type substrate 10 corresponding to the lightly doped region.

[0060] Step 6: Perform N-type light doping on the lightly doped region by ion implanting nitrogen (N) to form the lightly doped drain region 60, and at the same time form a self-aligned channel. After completing Step 6, the structure is as Figure 11 shown.

[0061] Step 7: Using chemical vapor deposition, deposit a third hard mask 50 on the surface of the stacked structure formed in Step S6 ( Figure 11 the structure shown). After completing Step 7, the structure is as Figure 12 shown.

[0062] Step 8: Use dry etching to form a second sidewall mask 51 on the third hard mask 50 to define the source-drain doping region. After completing Step 8, the structure is as Figure 13 shown, and there is still a first hard mask 30 above the N-type substrate 10 corresponding to the source-drain doping region.

[0063] Step 9: Perform N-type heavy doping on the source / drain doping regions by ion-implanting nitrogen (N) to form the source / drain regions 70, and simultaneously form the self-aligned lightly doped drain regions 80. The structure after completing Step 9 is as shown in Figure 14 shown.

[0064] Step 10: Remove the protective film 30, the first hard mask 20, the first sidewall mask 41, and the second sidewall mask 51 by wet etching. The structure after completing Step 10 is as shown in Figure 15 shown.

[0065] The preparation process of the SiC PMOSFET is similar to that of the SiC NMOSFET, except that a P-type substrate is selected in Step 1, the N-well region is defined in Step 2, the N-well is formed in Step 3, P-type light doping is performed in Step 6, and P-type heavy doping is performed in Step 9.

[0066] Although the present disclosure has been described with exemplary embodiments, various changes and modifications can be suggested to those skilled in the art. The present disclosure is intended to cover such changes and modifications that fall within the scope of the appended claims.

[0067] Any description in the present disclosure should not be construed as implying that any particular element, step, or function is an essential element that must be included within the scope of the claims. The scope of the patent subject matter is defined only by the claims.

Claims

1. A method for forming a lightly doped drain region, characterized in that, It includes the following steps: Step S1: Form a hard mask structure on the surface of a semiconductor substrate, define a doped well region through a selective patterning process, and form a doped well in the doped well region; Step S2: Form a first sidewall mask on the vertical sidewalls of the hard mask structure, complete the lightly doped drain region implantation and simultaneously form a self-aligned channel; Step S3: Form a second sidewall mask on the sidewalls of the first sidewall mask facing away from the hard mask structure, complete the heavily doped drain region implantation and simultaneously form a self-aligned lightly doped drain region; Step S4: Remove the hard mask structure, the first sidewall mask, and the second sidewall mask.

2. The method for forming a lightly doped drain region according to claim 1, wherein: The specific steps of step S1 include: Step S1-1: Deposit a first hard mask on the surface of the semiconductor substrate, and the first hard mask serves as the hard mask structure; Step S1-2: Define the doped well region on the first hard mask through photolithography and dry etching; Step S1-3: Dope the doped well region through ion implantation to form a doped well.

3. The method for forming a lightly doped drain region according to claim 2, wherein: In step S1-1, before forming the first hard mask on the surface of the semiconductor substrate, first deposit a protective film on the semiconductor surface, and the protective film and the first hard mask serve as the hard mask structure.

4. The method for forming a lightly doped drain region according to claim 3, wherein: The material of the protective film is silicon dioxide, and the thickness of the protective film is 90nm - 110nm.

5. The method for forming a lightly doped drain region according to claim 2, wherein: The material of the first hard mask is polysilicon.

6. The method for forming a lightly doped drain region according to claim 1, wherein: The specific steps of step S2 include: Step S2-1: Deposit a second hard mask on the surface of the stacked structure formed in step S1; Step S2-2: Define a lightly doped region by dry etching the second hard mask to form a first sidewall mask on the vertical sidewalls of the hard mask structure; Step S2-3: Perform light doping in the lightly doped region through ion implantation to form a lightly doped drain region and simultaneously form a self-aligned channel.

7. The method for forming a lightly doped drain region according to claim 1, wherein: The specific steps of step S3 include: Step S3-1: Deposit a third hard mask on the surface of the stacked structure formed in step S2; Step S3-2: Define a source / drain doping region by dry etching the third hard mask to form a second sidewall mask on the sidewalls of the first sidewall mask facing away from the hard mask structure; Step S3-3: Perform heavy doping in the source / drain doping region through ion implantation to form a source / drain region and simultaneously form a self-aligned lightly doped drain region.

8. The method for forming a lightly doped drain region according to claim 1, wherein: Both the first sidewall mask and the second sidewall mask are polysilicon.

9. The method for forming a lightly doped drain region according to claim 1, wherein: The thickness of the second sidewall mask is determined according to the size of the self-aligned lightly doped drain region.

10. The method for forming a lightly doped drain region according to claim 1, wherein in the step S4, the hard mask structure, the first sidewall mask, and the second sidewall mask are removed by wet etching.

Images