An LDMOS device with asymmetric stepped field oxide

Abstract

The present invention discloses an LDMOS device with an asymmetric stepped field oxide structure. The field oxide structure of the LDMOS device of the present invention adopts an asymmetric stepped shape to achieve asymmetric coordinated regulation of the STI thickness. The stepped side expands the field oxide boundary by gradient, weakening the electric field concentration at the STI corner, thereby increasing the breakdown voltage. The tilt angle of the non-stepped side retains the thick field oxide region, suppressing the electric field spike on the source side, delaying avalanche breakdown, and reducing the risk of hot carrier injection. This structure takes into account the coordinated optimization of breakdown capability and conduction efficiency, and is particularly suitable for high-voltage BCD platforms that require both low loss and high reliability. It is a structural innovation solution with strong process compatibility and high design flexibility.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to an LDMOS device with asymmetric stepped field oxide. Background Art

[0002] With the development of integrated circuit technology in the post-Moore era, the industry has placed higher demands on system integration, energy efficiency, and chip area. The evolution of integrated circuits has gradually shifted from "miniaturization" to "functional integration." Against this backdrop, power integrated circuits (Power ICs) are widely used in power management, motor drives, automotive electronics, communications terminals, and other fields, becoming the core foundation of modern electronic systems. BCD (Bipolar-CMOS-DMOS) technology, currently the most representative single-chip power system platform, has become a mainstream solution due to its ability to simultaneously integrate bipolar transistors (BJTs), complementary metal-oxide semiconductors (CMOS), and diffused power MOSFETs (DMOS).

[0003] In the BCD process system, the lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) is a typical high-voltage power device structure, featuring high breakdown voltage, low conduction losses, and excellent thermal stability. The LDMOS device forms a channel structure through lateral diffusion, with its source, drain, and gate located on the silicon wafer surface, facilitating coplanar integration with other devices. This device not only has high input impedance, making it suitable for high-current drive applications, but also has a negative temperature coefficient (NTC), which provides excellent current sharing at high temperatures, further enhancing its thermal reliability and service life.

[0004] To further improve the integration density and size control capabilities of power devices, modern BCD platforms widely adopt shallow trench isolation (STI) technology to replace the traditional LOCOS isolation process. The STI structure achieves electrical isolation by deeply etching the trench and filling it with oxide, offering excellent planarization and boundary control capabilities. LDMOS is a key and challenging component of BCD device design, and STI, as a critical isolation process, is widely used in modern BCD platforms. This makes research on developing a stable STILDMOS process highly economical.

[0005] Balancing the off-state breakdown voltage and on-state resistance of LDMOS devices is a challenge in LDMOS device development. Traditional LDMOS structures rely on a low-doped drift region to carry voltage. A lower doping concentration means a decrease in the number of carriers, leading to increased resistivity, increased on-resistance, and reduced on-current. To reduce on-resistance, the drift region doping concentration must be increased, which in turn increases the peak electric field in the device when under voltage in the off-state, reducing the off-state breakdown voltage. Furthermore, the introduction of STI into the LDMOS structure raises a series of key issues:

[0006] The interface structure between STI oxide and silicon is relatively complex, especially at the junction of STI and the drift region or channel region. Due to differences in material dielectric constants and thermal expansion coefficients, the electric field can easily concentrate sharply at the STI corners, forming local high-field regions that seriously affect the breakdown voltage and reliability of the device. At the same time, stress in the STI region can also cause a decrease in channel mobility, leading to an increase in device on-resistance. In addition, the traditional STI structure has a fixed vertical boundary, which is not conducive to lateral buffering and spatial redistribution of the electric field, making local breakdown particularly prone to occur under high-voltage operating conditions.

[0007] Previous studies have attempted to optimize the electric field distribution by introducing field plate structures, segmented doping control, or localized implantation. However, this often results in a significant increase in on-resistance while increasing the breakdown voltage, making it difficult to strike a balance between conduction performance and withstand voltage. Consequently, the on-state on-resistance and off-state breakdown voltage of traditional LDMOS present an irreconcilable conflict, requiring a trade-off during device development. This conflict can only be resolved through the development of novel LDMOS device structures. Summary of the Invention

[0008] The object of the present invention is to overcome the above-mentioned deficiencies in the prior art and to provide an LDMOS device with an asymmetric stepped field oxide structure.

[0009] The LDMOS device of the present invention has an asymmetric stepped field oxide structure, comprising:

[0010] substrate;

[0011] a gate formed above the substrate;

[0012] A drift region and a first well region are formed on both sides of the substrate, respectively, and a distance exists between the first well region and the drift region;

[0013] a second well region formed in the drift region;

[0014] a body region formed in the first well region;

[0015] an asymmetric stepped field oxygen structure formed in the drift region;

[0016] a drain electrode formed in the second well region;

[0017] A source electrode and a body electrode are formed in the body region.

[0018] Preferably, a gate oxide layer is formed between the gate and the substrate; and sidewalls are formed on both sides of the gate.

[0019] Preferably, the doping concentration of the second well region is lower than that of the first well region.

[0020] Preferably, the asymmetric stepped field oxide structure extends to a portion of the top region of the second well region and the non-second well region region.

[0021] Preferably, the drain is close to the asymmetric stepped field oxide structure; the body is located outside the source, and the two are short-circuited.

[0022] Preferably, the side of the asymmetric stepped field oxide structure facing the second well region is an inverted stepped structure, and the side facing the first well region is a non-stepped structure.

[0023] More preferably, the asymmetric stepped field oxide structure has a two-layer stepped structure on the side facing the second well region, and has a top angle less than 90 degrees on the side facing the first well region.

[0024] Preferably, the asymmetric stepped field oxygen structure is an integrally formed structure, including a bottom trapezoidal structure and a top trapezoidal structure configured from bottom to top; the side wall of the bottom trapezoidal structure facing the first well region and the side wall of the top trapezoidal structure facing the first well region are located in the same straight line; the lower end of the top trapezoidal structure is connected to the upper end of the bottom trapezoidal structure, and the length of the lower end of the top trapezoidal structure is greater than the upper end of the bottom trapezoidal structure.

[0025] More preferably, the thickness of the top trapezoidal structure is thicker than the thickness of the bottom trapezoidal structure.

[0026] Preferably, one end of the gate is located above a partial region of the asymmetric stepped field oxide structure, and the other end is located above a partial region of the body region.

[0027] The beneficial effects of the present invention include at least:

[0028] The field oxide structure of the LDMOS device of the present invention adopts an asymmetric stepped shape to achieve asymmetric coordinated control of the STI thickness. The stepped side expands the field oxide boundary through a gradient, weakening the electric field concentration at the STI corner, thereby improving the breakdown voltage (BV). The tilt angle of the non-stepped side retains the thick field oxide region, suppresses the electric field spike on the source side, delays avalanche breakdown, and reduces the risk of hot carrier injection (HCI).

[0029] The present invention realizes uniform distribution of the electric field in the drift region, shortens the conduction path, and improves the power figure of merit through the coordinated design of the field oxygen thickness and the doping concentration.

[0030] This invention introduces a uniformly tilted SSTI (bottom trapezoidal structure) in the thick field oxide region near the first well. This results in a thickened, tilted STI segment near the first well, and a thinner, retained STI segment near the second well. This achieves asymmetric, coordinated control of STI thickness, effectively delaying the location of the high electric field concentration region, achieving a broadened and balanced electric field gradient in the drift region, and significantly suppressing the electric field spike at the source-side STI corner. In terms of device electrical performance, this structure significantly reduces the increase in specific on-resistance (Rsp) caused by thick STI while maintaining or slightly improving the breakdown voltage (BV), thereby improving the device's power performance figure of merit (FOM). This structure balances breakdown capability and conduction efficiency, making it particularly suitable for high-voltage BCD platforms requiring both low loss and high reliability. It offers a structural innovation with strong process compatibility and design flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 FIG. 1 is a schematic structural diagram of an LDMOS device (denoted as leftsti) having an asymmetric stepped field oxide structure provided by an embodiment of the present invention.

[0033] Figure 2 It is a structural diagram of an LDMOS device (denoted as basesti) with a thin trapezoidal field oxide structure.

[0034] Figure 3 It is a structural diagram of an LDMOS device (denoted as basesti1) with a thick trapezoidal field oxide structure.

[0035] Figure 4 It is the preparation process flow of LDMOS device leftsti.

[0036] Figure 5 These are the BV breakdown characteristic curves of three different field oxide structure LDMOS devices (leftsti, basesti, basesti1).

[0037] Figure 6These are the Id–Vds conduction characteristic curves of three different field oxide structure LDMOS devices (leftsti, basesti, basesti1).

[0038] Figure 7 It is the impact ionization rate distribution diagram of LDMOS device (leftsti).

[0039] Figure 8 It is the impact ionization rate distribution diagram of LDMOS device (basesti).

[0040] Figure 9 This is the impact ionization rate distribution diagram of the LDMOS device (basesti1).

[0041] Figure 10 It is the electric field intensity distribution diagram of LDMOS device (leftsti).

[0042] Figure 11 It is the electric field intensity distribution diagram of LDMOS device (basesti).

[0043] Figure 12 It is the electric field intensity distribution diagram of LDMOS device (basesti1).

[0044] Figure 13 This is a schematic diagram of the electric field strength curve of the LDMOS device (leftsti) along the X direction of the device when Y=0.387um is intercepted.

[0045] Figure 14 This is a schematic diagram of the electric field strength curve of the LDMOS device (basesti) along the X direction of the device when Y=0.387um is intercepted.

[0046] Figure 15 This is a schematic diagram of the electric field strength curve of the LDMOS device (basesti1) along the X direction of the device when Y=0.387um is intercepted.

[0047] Figure 16 These are the electric field strength curves along the X direction of three LDMOS devices with different field oxide structures (leftsti, basesti, basesti1) taken at Y=0.387um.

[0048] Markings in the figure: 1. Substrate; 2. Drift region; 3. Asymmetric stepped field oxide structure; 3-1. Top trapezoidal structure; 3-2. Bottom trapezoidal structure; 4. First well region; 5. Second well region; 6. Gate oxide layer; 7. Gate; 8. Body region; 9. Sidewall; 10. Source; 11. Drain; 12. Body. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0050] like Figure 1 As shown, an embodiment of the present invention provides an LDMOS device with an asymmetric stepped field oxide structure, denoted as leftsti, to solve the contradiction that when the STI thickness is increased to increase the off-state breakdown voltage of the STI LDMOS, the on-resistance will be greatly increased. The device includes:

[0051] Substrate 1;

[0052] A gate 7 is formed above the substrate 1, with a gate oxide layer 6 formed between the gate 7 and the substrate 1; sidewalls 9 are formed on both sides of the gate 7;

[0053] A drift region 2 is formed on one side of the substrate 1, and a first well region 4 is formed on the other side, and there is a distance between the first well region 4 and the drift region 2;

[0054] A second well region 5 is formed at the outer end of the drift region 2 , and the doping concentration of the second well region 5 is lower than that of the first well region 4 ;

[0055] A body region is formed at the outer end of the first well region 4;

[0056] An asymmetric stepped field oxide structure 3 is formed on the top of the drift region 2 , and the asymmetric stepped field oxide structure 3 extends to a portion of the top area of ​​the second well region 5 ;

[0057] A drain 11 is provided at the top outer end of the second well region 5;

[0058] A source electrode 10 and a body electrode 12 are further provided on the top of the body region. The body electrode 12 is located outside the source electrode 10 and the two are usually short-circuited.

[0059] In one embodiment, the asymmetric stepped field oxide structure 3 has an inverted stepped structure on the side facing the second well region 5 , and has a non-stepped structure on the side facing the first well region 4 .

[0060] In one embodiment, the asymmetric stepped field oxide structure 3 is a two-layer stepped structure on the side facing the second well region 5 ; and the top angle on the side facing the first well region 4 is less than 90 degrees.

[0061] By way of example, the asymmetric stepped field oxide structure 3 is an integrally formed structure, comprising a bottom trapezoidal structure 3-2 and a top trapezoidal structure 3-1 arranged from bottom to top. The sidewall of the bottom trapezoidal structure 3-2 facing the first well region 4 and the sidewall of the top trapezoidal structure 3-1 facing the first well region 4 are located in the same straight line. The lower end of the top trapezoidal structure 3-1 is connected to the upper end of the bottom trapezoidal structure 3-2, and the length L1 of the lower end of the top trapezoidal structure 3-1 is greater than the upper end L2 of the bottom trapezoidal structure 3-2. For example, L1 = 3.7 μm and L2 = 1.5 μm.

[0062] More specifically, the thickness of the top trapezoidal structure 3-1 is greater than the thickness of the bottom trapezoidal structure 3-2. In one embodiment, the thickness of the top trapezoidal structure 3-1 is about 4:1 to the thickness of the bottom trapezoidal structure 3-2. For example, the thickness of the top trapezoidal structure 3-1 is greater than 0.3 microns.

[0063] In one embodiment, one end of the gate 7 is located above a portion of the asymmetric stepped field oxide structure 3 , and the other end is located above a portion of the body region.

[0064] This embodiment also provides a preparation process of the LDMOS device leftsti, see the attached Figure 4 include:

[0065] 1. Doping the substrate 1;

[0066] 2. Doping the drift region 2 on the doped substrate 1 (e.g., N-type doping to form an N-type drift region 2);

[0067] 3. Etch in two steps to form an asymmetric stepped field oxide structure 3 (i.e. shallow trench isolation):

[0068] The first step is to etch the top trapezoidal structure of the asymmetric stepped field oxide structure, and then further etch the bottom trapezoidal structure through the added SSTI mask.

[0069] 4. Doping is performed to form a first well region 4 (e.g., a P-type Well region) with a slightly higher doping concentration and a second well region 5 (e.g., an N-type Well region with a slightly higher doping concentration);

[0070] 5. Grow gate oxide layer 6;

[0071] 6. Deposit a layer of polysilicon and etch to form gate 7. The raised portion of gate 7 can be smoothed by CMP (chemical mechanical polishing);

[0072] 7. Doping is performed to form a body region 8 (e.g., a P-type body region) with a slightly higher doping concentration;

[0073] 8. Forming side walls 9;

[0074] 9. Doping to form source 10, drain 11 and body 12.

[0075] At the same time, this embodiment also provides a comparative structure: an LDMOS device with a thin trapezoidal field oxide structure, denoted as basesti; an LDMOS device with a thick trapezoidal field oxide structure, denoted as basesti1;

[0076] Compared with the leftsti device of this embodiment, the field oxygen structure of the basesti device adopts an isosceles trapezoidal structure with a thickness h1 of the top trapezoidal structure, see the attached Figure 2 The field oxide structure of the basesti1 device adopts an isosceles trapezoidal structure with a top trapezoidal structure thickness of h1 and a bottom trapezoidal structure thickness of h2. Figure 3 The top angle of the field oxygen structure of the basesti device and the basesti1 device is α, α is less than 90°, and can be 80°.

[0077] Analysis of the breakdown conduction characteristics advantages of three types of devices:

[0078] 1. The breakdown capability of leftisti devices is significantly improved compared to baseisti devices, while the conduction performance is moderately controllable:

[0079] like Figure 5 As shown in the BV curve, under the same doping conditions, the breakdown voltage of leftsti reaches 112 V (red line), which is about 8 V higher than that of basesti (about 104 V (green line). Figure 10 and electric field distribution Figure 11 The comparison shows that the bottom trapezoidal structure of leftsti effectively shifts the electric field concentration area backward, reduces the peak electric field at the gate edge, and thus delays the occurrence of avalanche breakdown. Figure 7 It also shows that the high ionization region of leftsti shifts more significantly to the right, delaying the ionization onset position, which is beneficial to improving the breakdown capability and effectively reducing the risk of hot carrier injection (HCI).

[0080] At the same time, through the Id-Vds curve ( Figure 6 ) It can be seen that under the same drain-source voltage Vds condition, the drain current Ids of leftsti (red line) is lower than that of basesti (green line), indicating a slight increase in on-resistance. However, the significant increase in breakdown voltage BV far outweighs the slight degradation of on-resistance (Rsp), ultimately significantly improving the power figure of merit (FOM) of leftsti from approximately 144.2 to 154.3, achieving an overall performance gain. It can be seen that its comprehensive optimization effect is significant.

[0081] 2. Compared with basesti1 devices, leftsti devices can maintain breakdown voltage while significantly reducing conduction losses:

[0082] See also Figure 5 The breakdown voltages (BV) of leftsti and basesti1 (the red and blue lines essentially overlap) are both around 112V, indicating that even with the same thickness on the left side of the field oxide structure, equivalent breakdown performance can be achieved. This means that the bottom trapezoidal structure alone can meet the electric field suppression requirements, while the right side of the bottom trapezoidal structure contributes only slightly to the breakdown voltage. Compared to basesti1, leftsti retains the thickness and angle structure of the STI on the left side of the bottom trapezoidal structure, effectively controlling the electric field distribution. From the electric field distribution diagram ( Figure 10 、 Figure 12 ) shows that both leftsti and basesti1 have distinct electric field weakening features at the source STI corner. Although the right side of the trapezoidal structure at the bottom of leftsti is missing some SSTI, the left side still retains a thick STI structure with an inclined angle, which is sufficient to control the high electric field region and keep the electric field distribution at a level similar to basesti1, without any significant peaks. Figure 7-Figure 9 This is further supported by the 10-μm CMOS image sensor. The distribution of high ionization rate regions in the breakdown state is nearly identical for both devices (the darker red portion), with comparable ionization intensities in the middle of the drift region and near the source STI corner. This demonstrates that while the LeftSTI structure is geometrically simplified, its electric field control capabilities remain unchanged, maintaining similar breakdown paths and ionization expansion.

[0083] from Figure 6 The Id-Vd curve shows that the Ids current of leftsti is higher than that of basesti1 (the red line is higher than the blue line), indicating a lower on-resistance (Rsp). This is due to the missing part on the right side of the trapezoidal structure at the bottom of leftsti, which shortens the current path when the device is turned on. The electric field intensity distribution curve taken at Y=0.387um ( Figure 16 ) further verifies that the electric field in the missing portion of the SSTI on the right side of the bottom trapezoidal structure of the leftsti drops to roughly the same level as the thinner basesti, significantly reducing the current suppression effect and thus maintaining higher conduction capability. The leftsti also has the same BV as basesti1, but its conduction performance is significantly improved, leaving room for further improvement in the Form of Material (FOM) (BV² / Rsp). Figure 13-15 This is a schematic diagram of the electric field strength curves of three devices, leftsti, basesti, and basesti1, along the X direction of the device when intercepted at Y=0.387um.

[0084] Compared to traditional symmetrical STI structures, leftsti utilizes an asymmetric stepped STI design. While retaining the thickness and angled STI on the left side to ensure electric field relief, it omits the STI portion on the right side to reduce conduction path resistance. Simulation results show that compared to a thinner STI structure (basesti), leftsti effectively suppresses electric field concentration and reduces the impact ionization rate at the drift region tip, increasing the device breakdown voltage by approximately 9V and significantly improving the Form of Material (FOM). Compared to a thicker STI structure (basesti1), leftsti significantly reduces on-resistance while maintaining a similar breakdown voltage, improving conduction efficiency. This structure balances breakdown characteristics with conduction performance while offering improved electric field distribution control, making it suitable for high-voltage BCD platforms where both power device performance and reliability are paramount.

[0085] Table 1: Comparison of characteristics of three types of devices

[0086]

[0087] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. An LDMOS device having an asymmetric stepped field oxide structure, characterized in that: The LDMOS device includes: substrate (1); A gate (7) formed above the substrate (1); A drift region (2) and a first well region (4) are respectively formed on both sides of the substrate (1), and there is a distance between the first well region (4) and the drift region (2); A second well region (5) is formed in the drift region (2); a body region (8) formed in the first well region (4); An asymmetric stepped field oxide structure (3) is formed in the drift region (2); a drain electrode (11) formed in the second well region (5); A source electrode (10) and a body electrode (12) are formed in the body region (8); The asymmetric stepped field oxygen structure (3) is an integrally formed structure, comprising a bottom trapezoidal structure (3-2) and a top trapezoidal structure (3-1) configured from bottom to top; the side wall of the bottom trapezoidal structure (3-2) facing the first well region (4) and the side wall of the top trapezoidal structure (3-1) facing the first well region (4) are located in the same straight line; the lower end of the top trapezoidal structure (3-1) is connected to the upper end of the bottom trapezoidal structure (3-2), and the length of the lower end of the top trapezoidal structure (3-1) is greater than the upper end of the bottom trapezoidal structure (3-2).

2. The LDMOS device according to claim 1, wherein: A gate oxide layer (6) is formed between the gate (7) and the substrate (1); and sidewalls (9) are respectively formed on both sides of the gate (7).

3. The LDMOS device according to claim 1, wherein: The doping concentration of the second well region (5) is lower than that of the first well region (4).

4. The LDMOS device according to claim 1, wherein: The asymmetric stepped field oxygen structure (3) extends to a portion of the top region of the second well region (5) and a region other than the second well region (5).

5. The LDMOS device according to claim 1, wherein: The drain (11) is close to the asymmetric stepped field oxide structure (3); the body (12) is located outside the source (10), and the two are short-circuited.

6. The LDMOS device according to claim 1, wherein: The side of the asymmetric stepped field oxygen structure (3) facing the second well region (5) is an inverted stepped structure, and the side facing the first well region (4) is a non-stepped structure.

7. The LDMOS device according to claim 6, characterized in that: The asymmetric stepped field oxygen structure (3) has a two-layer stepped structure on the side facing the second well region (5); and the top angle on the side facing the first well region (4) is less than 90 degrees.

8. The LDMOS device according to claim 1, wherein: The thickness of the top trapezoidal structure (3-1) is greater than the thickness of the bottom trapezoidal structure (3-2).

9. The LDMOS device according to claim 1, wherein: One end of the gate (7) is located above a partial area of ​​the asymmetric stepped field oxide structure (3), and the other end is located above a partial area of ​​the body region (8).

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