Thin film transistor

Abstract

The invention discloses a thin film transistor which comprises a substrate, a semiconductor pattern, a source electrode, a drain electrode, a grid electrode and an electrode pattern. The semiconductor pattern is disposed on the substrate and has a source region, a drain region and a channel region. The channel region is connected between the source region and the drain region. The source electrode and the drain electrode are arranged on the semiconductor pattern and electrically connected with the source electrode region and the drain electrode region of the semiconductor pattern respectively. The grid electrode is arranged on the semiconductor pattern and is located between the source electrode and the drain electrode. The gate completely overlaps the channel region of the semiconductor pattern. The electrode pattern is disposed between the substrate and the semiconductor pattern and overlaps the semiconductor pattern. The electrode pattern is electrically connected with the grid electrode or the source electrode and does not overlap at least one of the source electrode region and the drain electrode region.

Description

Technical Field

[0001] The present invention relates to a transistor, and more particularly to a thin film transistor. Background Art

[0002] In a current display panel, in order to provide a gate driving signal for turning on a pixel circuit, a gate driving circuit may be further disposed on a pixel substrate. Generally, the gate driving circuit may be composed of a plurality of transistors and at least one capacitor. Among them, the thin film transistor for receiving a clock signal and providing a gate driving signal is likely to cause degradation of operating electrical properties, such as a shift of a threshold voltage (Vth), after a long-time operation of a high-frequency and high-voltage signal. Summary of the Invention

[0003] The present invention provides a thin film transistor that can maintain stable operating electrical properties under a long-time operation of a high-frequency and high-voltage signal.

[0004] The thin film transistor of the present invention includes a substrate, a semiconductor pattern, a source electrode, a drain electrode, a gate electrode, and an electrode pattern. The semiconductor pattern is disposed on the substrate and has a source region, a drain region, and a channel region. The channel region is connected between the source region and the drain region. The source electrode and the drain electrode are disposed on the semiconductor pattern and are electrically connected to the source region and the drain region of the semiconductor pattern, respectively. The gate electrode is disposed on the semiconductor pattern and is located between the source electrode and the drain electrode. The gate electrode completely overlaps the channel region of the semiconductor pattern. The electrode pattern is disposed between the substrate and the semiconductor pattern and overlaps the semiconductor pattern. The electrode pattern is electrically connected to the gate electrode or the source electrode and does not overlap at least one of the source region and the drain region.

[0005] Based on the above, in the thin film transistor according to an embodiment of the present invention, a gate electrode and an electrode pattern are respectively disposed on upper and lower sides of the semiconductor pattern, and the electrode pattern is electrically connected to the gate electrode or the source electrode. Since the electrode pattern does not overlap at least one of the source region and the drain region, the thin film transistor can still maintain stable operating electrical properties under a long-time operation of a high-frequency and high-voltage signal. Brief Description of the Drawings

[0006] Figure 1 is a cross-sectional schematic view of a thin film transistor according to a first embodiment of the present invention.

[0007] Figure 2 is Figure 1 a top view schematic diagram of the thin film transistor.

[0008] Figure 3 is Figure 2 a cross-sectional schematic view of the thin film transistor.

[0009] Figure 4It is a circuit schematic diagram of a gate driving circuit according to an embodiment of the present invention.

[0010] Figure 5 It is a schematic diagram of driving waveforms of a gate driving circuit according to an embodiment of the present invention.

[0011] Figure 6 It is a cross-sectional schematic diagram of a thin-film transistor according to a second embodiment of the present invention.

[0012] Figure 7 It is a top-view schematic diagram of a thin-film transistor according to a third embodiment of the present invention.

[0013] Figure 8 is Figure 7 a cross-sectional schematic diagram of the thin-film transistor.

[0014] Wherein, reference numerals:

[0015] 10: Gate driving circuit

[0016] 11: Input circuit

[0017] 12: First output circuit

[0018] 13: Second output circuit

[0019] 14: First voltage stabilizing circuit

[0020] 15: Second voltage stabilizing circuit

[0021] 16: First pull-down circuit

[0022] 17: Second pull-down circuit

[0023] 100, 100A, 100B: Thin-film transistors

[0024] 101: Substrate

[0025] 101s: Substrate surface

[0026] 110, 120, 130: Insulating layers

[0027] C1, C2: Capacitors

[0028] CK(n), XCK(n): Clock signals

[0029] CR: Channel region

[0030] DE: Drain

[0031] DR: Drain region

[0032] D2U: Second-direction scanning signal

[0033] EP, EP-A, EP-B: Electrode pattern

[0034] EPb, GEb: Bridge

[0035] GE: Gate

[0036] G(n): Gate drive signal

[0037] M1~M15: Transistor

[0038] Q(n), Q1(n): control signal

[0039] Q'(n):Isolated control signal

[0040] S, S1, S2: Spacing

[0041] S(n-1), S(n), S(n+1): timing drive signal

[0042] SC: Semiconductor Pattern

[0043] SE: Source

[0044] SF1, SF2: surface

[0045] SR: Source region

[0046] TH1, TH2, TH3, TH4: through hole

[0047] TP, TP-A: Transfer pattern

[0048] U2D: first direction scanning signal

[0049] VEX: External control signal

[0050] VGL: Gate Low Voltage

[0051] VGL1: Gradient gate low voltage

[0052] Z: Direction

[0053] A-A', B-B': section line DETAILED DESCRIPTION

[0054] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention.

[0055] As used herein, "about", "approximate", "substantially", or "essentially" include the stated value and the average value within an acceptable deviation range of a specific value determined by a person of ordinary skill in the art, taking into account the specific amount of the measurement being discussed and the errors associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or, for example, within ±30%, ±20%, ±15%, ±10%, or ±5%. Further, "about", "approximate", "substantially", or "essentially" as used herein can be selected to have a more acceptable deviation range or standard deviation depending on the nature of the measurement, the nature of the cutting, or other properties, rather than applying a single standard deviation to all properties.

[0056] In the figures, for clarity, the thickness of layers, films, panels, regions, etc. is exaggerated. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, no intervening elements are present. As used herein, "connected" can refer to physical and / or electrical connection. Further, "electrical connection" can be the presence of other elements between two elements.

[0057] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the figures. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is flipped, an element described as being on the "lower" side of another element will be oriented on the "upper" side of the other element. Thus, the exemplary term "lower" can include both the "lower" and "upper" orientations, depending on the specific orientation of the figure. Similarly, if the device in one figure is flipped, an element described as being "beneath" or "below" another element will be oriented as being "above" the other element. Thus, the exemplary terms "above" or "below" can include both the above and below orientations.

[0058] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Accordingly, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments described herein should not be construed as being limited to the specific shapes of regions shown herein, but rather include, for example, shape deviations resulting from manufacturing. For example, regions shown or described as flat will generally have rough and / or non-linear features. In addition, the sharp angles shown may be rounded. Thus, the regions shown in the figures are essentially schematic, and their shapes are not intended to show the exact shape of the region and are not intended to limit the scope of the claims.

[0059] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0060] Figure 1 is a cross-sectional schematic view of a thin film transistor according to a first embodiment of the present invention. Figure 2 is Figure 1 a top view schematic of the thin film transistor. Figure 3 is Figure 2 a cross-sectional schematic of the thin film transistor. Figure 4 is a circuit schematic of a gate driving circuit according to an embodiment of the present invention. Figure 5 is a driving waveform schematic of the gate driving circuit according to an embodiment of the present invention. It should be noted that Figure 2 the illustration of the substrate 101 in Figure 3 is omitted. Figure 3 corresponds to Figure 2 the cross-section line A-A'.

[0061] Please refer to Figure 1 , the thin film transistor 100 includes a substrate 101, an electrode pattern EP, a gate GE, a semiconductor pattern SC, a source SE, and a drain DE. The semiconductor pattern SC is disposed on the substrate 101 and has a source region SR, a drain region DR, and a channel region CR. The channel region CR is connected between the source region SR and the drain region DR. The source SE and the drain DE are disposed on the semiconductor pattern SC and are electrically connected to the source region SR and the drain region DR of the semiconductor pattern SC, respectively. The gate GE is disposed on the semiconductor pattern SC and is located between the source SE and the drain DE.

[0062] For example, in the step of forming the source region SR and the drain region DR of the semiconductor pattern SC, the gate GE located above the semiconductor pattern SC can be used as a hard mask for the doping process. Therefore, the gate GE can define the channel region CR of the semiconductor pattern SC. That is to say, the gate GE completely overlaps the channel region CR along the normal direction (for example, the direction Z) of the substrate surface 101s of the substrate 101. That is, the positive projection of the channel region CR of the semiconductor pattern SC on the substrate surface 101s is located within the positive projection of the gate GE on the substrate surface 101s. In this embodiment, the material of the semiconductor pattern SC includes, for example, indium gallium zinc oxide (IGZO). The source region SR and the drain region DR are, for example, n-type (n+ type) impurity regions, but are not limited thereto.

[0063] The electrode pattern EP is disposed between the substrate 101 and the semiconductor pattern SC and overlaps the semiconductor pattern SC. Accordingly, the semiconductor pattern SC has a surface SF1 that overlaps the electrode pattern EP along the direction Z and a surface SF2 that electrically contacts the source SE and the drain DE, and the surface SF1 is farther from the substrate 101 than the surface SF2. That is to say, in this embodiment, the arrangement of the electrode pattern EP and the film thickness relationship between the electrode pattern EP and the insulating layer 110 cause the semiconductor pattern SC not to be formed on a single plane.

[0064] The thin film transistor 100 further includes an insulating layer 110, an insulating layer 120, and an insulating layer 130. The insulating layer 110 is disposed between the electrode pattern EP and the semiconductor pattern SC. The insulating layer 120 is disposed between the semiconductor pattern SC and the gate GE. The insulating layer 130 is disposed between either the source SE or the drain DE and the gate GE. In this embodiment, the insulating layer 110 and the insulating layer 120 are, for example, gate insulating layers, and the insulating layer 130 is, for example, an interlayer insulating layer, but is not limited thereto. The insulating layer 120 and the insulating layer 130 have a through hole TH1 that overlaps the source region SR and a through hole TH2 that overlaps the drain region DR. The source SE is electrically connected to the source region SR of the semiconductor pattern SC through the through hole TH1. The drain DE is electrically connected to the drain region DR of the semiconductor pattern SC through the through hole TH2.

[0065] In this embodiment, the electrode pattern EP can be electrically connected to the gate GE. That is to say, the thin film transistor 100 of this embodiment is a dual-gate thin film transistor. Please refer to Figure 1 , Figure 2 and Figure 3 , for example, the electrode pattern EP can have a bridging portion EPb that does not overlap the semiconductor pattern SC in the direction Z, and the gate GE can have a bridging portion GEb that does not overlap the semiconductor pattern SC in the direction Z. That is to say, the bridging portion EPb can extend from the portion of the electrode pattern EP that overlaps the semiconductor pattern SC, and the bridging portion GEb can extend from the portion of the gate GE that overlaps the semiconductor pattern SC. The insulating layer 110, the insulating layer 120, and the insulating layer 130 have a through hole TH3 that overlaps the bridging portion EPb. The insulating layer 130 has a through hole TH4 that overlaps the bridging portion GEb. The thin film transistor 100 further has a transfer pattern TP on the insulating layer 130. The transfer pattern TP is electrically connected to the bridging portion EPb through the through hole TH3 and is electrically connected to the bridging portion GEb through the through hole TH4.

[0066] On the other hand, it should be noted that in the normal direction of the substrate surface 101s, the electrode pattern EP does not overlap at least one of the source region SR and the drain region DR of the semiconductor pattern SC. For example, the electrode pattern EP may overlap one of the source region SR and the drain region DR and does not overlap the other of the source region SR and the drain region DR. In this embodiment, the electrode pattern EP may overlap the source region SR and does not overlap the drain region DR. Or rather, the electrode pattern EP is disposed closer to the source SE than the gate GE. Preferably, the distance S between the electrode pattern EP and the drain region DR in a direction parallel to the substrate surface 101s may be greater than or equal to 0.75 micrometers and less than or equal to 3 micrometers.

[0067] Through the above configuration relationship, the operating electrical properties of the thin film transistor 100 will not deteriorate significantly even after the drain DE is applied with a high-frequency and high-voltage signal for a long time, such as the shift of the threshold voltage (Vth). In other words, the stability of the thin film transistor 100 under high-frequency and high-voltage signal operation can be improved.

[0068] Please refer to Figure 1 and Figure 4 , for example, the above thin film transistor 100 can be used in the gate driving circuit 10 of a display panel (such as a liquid crystal display panel, but not limited thereto), especially in a circuit part that needs to receive a high-frequency clock signal. The gate driving circuit 10 can be one stage in multiple stages of a gate driver (not shown) on the display panel (not shown). That is, the gate driver can be formed by connecting multiple gate driving circuits 10 in series. Among them, the gate driver can be implemented by a gate circuit (Gate on Array, GOA) on the pixel array substrate, but the present invention is not limited thereto.

[0069] The gate driving circuit 10 may include an input circuit 11, a first output circuit 12, a second output circuit 13, a first voltage stabilizing circuit 14, a second voltage stabilizing circuit 15, a first pull-down circuit 16, and a second pull-down circuit 17.

[0070] The input circuit 11 receives a first-direction scan signal U2D, a second-direction scan signal D2U, a timing drive signal S(n - 1) (corresponding to a first timing drive signal), and a timing drive signal S(n + 1) (corresponding to a second timing drive signal) to provide a control signal Q(n) (corresponding to a first control signal), where n is an index number. In this embodiment, the input circuit 11 includes a transistor M1 and a transistor M2. The transistor M1 has a first end (e.g., one of a source or a drain) receiving the first-direction scan signal U2D, a control end (e.g., a gate) receiving the timing drive signal S(n - 1), and a second end (e.g., the other of a source or a drain) providing the control signal Q(n). The transistor M2 has a first end coupled to the second end of the transistor M1, a control end receiving the timing drive signal S(n + 1), and a second end receiving the second-direction scan signal D2U. Also, the back control end (e.g., a bottom gate) of the transistor M1 is coupled to the control end of the transistor M1, and the back control end of the transistor M2 is coupled to the control end of the transistor M2.

[0071] The first output circuit 12 receives the control signal Q(n) and a clock signal CK(n) (corresponding to a first clock signal) to provide a timing drive signal S(n) (corresponding to a third timing drive signal) and an isolation control signal Q'(n). The second output circuit 13 receives the isolation control signal Q'(n) and the clock signal CK(n) to provide a gate drive signal G(n), where the gate drive signal G(n) is used to be provided to a display panel (not shown) to drive a corresponding pixel circuit (not shown). In this embodiment, the first output circuit 12 includes a transistor M3 and a transistor M4, and the second output circuit 13 includes a transistor M5 and a capacitor C1.

[0072] The transistor M3 has a first end receiving the control signal Q(n), a control end receiving a gate high voltage VGH, and a second end providing the isolation control signal Q'(n). The transistor M4 has a first end receiving the clock signal CK(n), a control end receiving the isolation control signal Q'(n), and a second end providing the timing drive signal S(n). The back control end of the transistor M3 receives a gate low voltage VGL, and the back control end of the transistor M4 is coupled to the control end of the transistor M4. The transistor M5 has a first end receiving the clock signal CK(n), a control end receiving the isolation control signal Q'(n), and a second end providing the gate drive signal G(n). The capacitor C1 is coupled between the control end and the second end of the transistor M5, and the back control end of the transistor M5 is coupled to the control end of the transistor M5.

[0073] Specifically, since the clock signal CK(n) usually has characteristics of high frequency (e.g., 14.29 kHz) and high voltage variation (e.g., 18.5 V), the transistors M4 and M5 of the gate drive circuit 10 can adoptFigure 1 The thin film transistor 100 shown is used to maintain the electrical stability of transistors M4 and M5 under long-term operation of high-frequency and high-voltage signals.

[0074] For example, the drain DE of the thin film transistor 10 can be used as the first terminal for transistors M4 and M5 to receive the clock signal CK(n) respectively. The source SE of the thin film transistor 10 can be used as the second terminal for transistor M4 to provide the timing drive signal S(n) and the second terminal for transistor M5 to provide the gate drive signal G(n). The gate GE of the thin film transistor 10 can be used as the control terminal for transistor M4 to receive the isolation control signal Q’(n) and the control terminal for transistor M5 to receive the isolation control signal Q’(n). The electrode pattern EP of the thin film transistor 10 can be used as the respective post-control terminal (i.e., bottom gate) for transistors M4 and M5.

[0075] On the other hand, the first voltage stabilizing circuit 14 receives the external control signal VEX and is coupled between the gate low voltage VGL and the control signal Q(n) to stabilize the control signal Q(n) at the disable level (such as the gate low voltage VGL) during the time / cycle when the gate driving circuit 10 is not activated. The first voltage stabilizing circuit 14 includes a transistor M6. Transistor M6 has a first terminal receiving the gate low voltage VGL, a control terminal receiving the external control signal VEX, and a second terminal coupled to the control signal Q(n). The post-control terminal of transistor M6 receives the gate low voltage VGL.

[0076] Similarly, the second voltage stabilizing circuit 15 receives the external control signal VEX and is coupled between the gate low voltage VGL and the timing drive signal S(n) to stabilize the timing drive signal S(n) at the disable level (such as the gate low voltage VGL) during the time / cycle when the gate driving circuit 10 is not activated. The second voltage stabilizing circuit 15 includes a transistor M7. Transistor M7 has a first terminal receiving the gate low voltage VGL, a control terminal receiving the external control signal VEX, and a second terminal coupled to the timing drive signal S(n). The post-control terminal of transistor M7 receives the gate low voltage VGL.

[0077] The first pull-down circuit 16 is coupled between the control signal Q(n), the timing drive signal S(n), and the gradually decreasing gate low voltage VGL1 to stabilize the control signal Q(n) and the timing drive signal S(n) at the gradually decreasing gate low voltage VGL1 during the time / cycle when the gate driving circuit 10 is not activated. The gradually decreasing gate low voltage VGL1 is, for example, independent of the gate low voltage VGL. The gradually decreasing gate low voltage VGL1 can decrease over time to reflect the stress generated by the continuous voltage application of the transistors in the first pull-down circuit 16.

[0078] In this embodiment, the first pull-down circuit 16 may include transistors M8 to M12 and capacitor C2. Transistor M8 has a first terminal for providing a control signal Q1(n), a control terminal for receiving a control signal Q(n), and a second terminal for receiving a gradually decreasing gate low voltage VGL1. Capacitor C2 is coupled between the clock signal CK(n) and the first terminal of transistor M8. Transistor M9 has a first terminal coupled to the control signal Q(n), a control terminal for receiving the control signal Q1(n), and a second terminal for receiving the gradually decreasing gate low voltage VGL1. Transistor M10 has a first terminal for receiving the control signal Q1(n), a control terminal for receiving an external control signal VEX, and a second terminal for receiving the gradually decreasing gate low voltage VGL1. Transistor M11 has a first terminal coupled to the timing drive signal S(n), a control terminal for receiving the control signal Q1(n), and a second terminal for receiving the gradually decreasing gate low voltage VGL1. Transistor M12 has a first terminal coupled to the timing drive signal S(n), a control terminal for receiving the clock signal XCK(n), and a second terminal for receiving the gradually decreasing gate low voltage VGL1. The post-control terminal of transistor M8 is coupled to the control terminal of transistor M8. The post-control terminals of transistors M9 to M12 each receive the gradually decreasing gate low voltage VGL1.

[0079] The second pull-down circuit 17 is coupled between the gate drive signal G(n) and the gate low voltage VGL, so that the gate drive signal G(n) is regulated to the gate low voltage VGL during the time / period when the gate drive circuit 10 is not activated. In this embodiment, the second pull-down circuit 17 may include transistors M13 to M15. Transistor M13 has a first terminal coupled to the gate drive signal G(n), a control terminal for receiving the control signal Q1(n), and a second terminal for receiving the gate low voltage VGL. Transistor M14 has a first terminal coupled to the gate drive signal G(n), a control terminal for receiving the clock signal XCK(n), and a second terminal for receiving the gate low voltage VGL. Transistor M15 has a first terminal coupled to the gate drive signal G(n), a control terminal for receiving the external control signal VEX, and a second terminal for receiving the gate low voltage VGL. The post-control terminals of transistors M13 to M15 each receive the gate low voltage VGL.

[0080] By providing the first voltage regulation circuit 14, the second voltage regulation circuit 15, the first pull-down circuit 16, and the second pull-down circuit 17, during the time / period when the gate drive circuit 10 is not activated, the control signal Q(n), the timing drive signal S(n), and the gate drive signal G(n) can all be regulated to a lower voltage level (i.e., the non-enabled level) to reduce the interference to the pixel voltage.

[0081] In this embodiment, transistors M1 to M15 are taken as N-type transistors as an example, and transistors M1 to M15 can be oxide thin-film transistors (oxide TFTs), and their semiconductor materials include, for example, indium gallium zinc oxide (IGZO), but the present invention is not limited thereto. It should be specifically noted that in this embodiment, transistors M1 to M15 of the gate driving circuit 10 may have different structural designs. For example, transistors M4 and M5 of the output circuit may adopt the structural design shown in the thin-film transistor 100 as Figure 1 , that is, the electrode pattern EP (i.e., the bottom gate) is disposed toward the source SE and does not overlap the drain region DR of the semiconductor pattern SC. The remaining transistors may adopt a structural design in which the electrode pattern overlaps both the source region and the drain region (not shown).

[0082] Please refer to Figure 4 and Figure 5 . The clock signals CK(n) and XCK(n) will be sequentially and alternately enabled. Therefore, the first pull-down circuit 16 and the second pull-down circuit 17 will periodically pull down the timing driving signal S(n) and the gate driving signal G(n) during the time / period when the gate driving circuit 10 is not activated. In addition, during a frame period, the external control signal VEX can be enabled at least once (for example, at a high voltage level) during the time / period other than when the gate driving circuit 10 is activated, so as to pull down the control signal Q(n), the control signal Q1(n), the timing driving signal S(n), and the gate driving signal G(n) through the first voltage stabilizing circuit 14, the second voltage stabilizing circuit 15, the first pull-down circuit 16, and the second pull-down circuit 17.

[0083] Some other embodiments will be listed below to illustrate the present invention in detail. The same components will be labeled with the same symbols, and the description of the same technical content will be omitted. For the omitted part, please refer to the foregoing embodiments and will not be repeated hereinafter.

[0084] Figure 6 is a cross-sectional schematic view of a thin-film transistor according to the second embodiment of the present invention. Please refer to Figure 6 , the thin-film transistor 100A of this embodiment and Figure 1The difference between the thin film transistor 100 is that the arrangement of the electrode patterns is different. Specifically, in the thin film transistor 100A of the present embodiment, the electrode pattern EP-A does not overlap with the source region SR and the drain region DR of the semiconductor pattern SC along the normal direction (e.g., direction Z) of the substrate surface 101s. That is to say, the electrode pattern EP-A is completely retracted under the gate GE. Preferably, the distance S1 between the electrode pattern EP-A and the source region SR along a direction parallel to the substrate surface 101s and the distance S2 between the electrode pattern EP-A and the drain region DR along this direction can be greater than or equal to 0.75 micrometers and less than or equal to 1.25 micrometers.

[0085] Since the electrode pattern EP-A does not overlap with the source region SR and the drain region DR, the thin film transistor 100A can still maintain stable operating electrical properties under long-term operation of high-frequency and high-voltage signals.

[0086] Figure 7 It is a top view schematic diagram of a thin film transistor according to the third embodiment of the present invention. Figure 8 is Figure 7 A cross-sectional schematic diagram of the thin film transistor. It should be noted that Figure 7 the illustration of the substrate 101 in Figure 8 is omitted. Figure 8 Corresponding to Figure 7 the cross-section line B-B'.

[0087] Please refer to Figure 7 and Figure 8 , different from Figure 2 and Figure 3 In the thin film transistor 100, in the thin film transistor 100B of the present embodiment, the electrode pattern EP-B can be electrically connected to the source SE. For example, the electrode pattern EP-B can have a bridging portion EPb that does not overlap with the semiconductor pattern SC in the direction Z. The thin film transistor 100B further has a transfer pattern TP-A on the insulating layer 130. The transfer pattern TP-A can extend from the source SE and be electrically connected to the bridging portion EPb of the electrode pattern EP-B through the through hole TH3 of the insulating layer 110, the insulating layer 120, and the insulating layer 130.

[0088] On the other hand, similar to Figure 6 the thin film transistor 100A, the electrode pattern EP-B of the present embodiment does not overlap with the source region SR and the drain region DR of the semiconductor pattern SC. That is, in Figure 7 the top view direction (e.g., direction Z), the electrode pattern EP-B is retracted relative to the two side edges of the gate GE.

[0089] It should be noted that in Figure 4 the gate driving circuit 10, the transistors M4 and M5 can also adopt Figure 6the thin film transistor 100A or Figure 7 and Figure 8 the structural design of the thin film transistor 100B.

[0090] In summary, in the thin film transistor of an embodiment of the present invention, a gate and an electrode pattern are respectively provided on the upper and lower sides of the semiconductor pattern, and the electrode pattern is electrically connected to the gate or the source. Since the electrode pattern does not overlap at least one of the source region and the drain region, the thin film transistor can still maintain a stable operating electrical property under long-term operation of high-frequency and high-voltage signals.

[0091] Certainly, the present invention may also have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention. However, these corresponding changes and deformations should all fall within the protection scope of the appended claims of the present invention.

Claims

1. A thin film transistor, characterized in that Comprising: A substrate; A semiconductor pattern disposed on the substrate and having a source region, a drain region, and a channel region, the channel region being connected between the source region and the drain region; A source and a drain disposed on the semiconductor pattern and electrically connected to the source region and the drain region of the semiconductor pattern respectively; A gate disposed on the semiconductor pattern and located between the source and the drain, the gate completely overlapping the channel region of the semiconductor pattern; And An electrode pattern disposed between the substrate and the semiconductor pattern and overlapping the semiconductor pattern, wherein the electrode pattern is electrically connected to the gate or the source and does not overlap at least one of the source region and the drain region.

2. The thin film transistor according to claim 1, wherein, Wherein the electrode pattern overlaps one of the source region and the drain region and does not overlap the other of the source region and the drain region.

3. The thin film transistor according to claim 2, wherein, Wherein the electrode pattern overlaps the source region and does not overlap the drain region.

4. The thin film transistor according to claim 2, wherein Wherein the distance between the other of the source region and the drain region and the electrode pattern is greater than or equal to 0.75 micrometers and less than or equal to 3 micrometers.

5. The thin film transistor according to claim 1, wherein Wherein the electrode pattern does not overlap the source region and the drain region.

6. The thin film transistor according to claim 5, wherein, Wherein the distance between each of the source region and the drain region and the electrode pattern is greater than or equal to 0.75 micrometers and less than or equal to 1.25 micrometers.

7. The thin film transistor according to claim 1, characterized in that, Further comprising: A first insulating layer disposed between the electrode pattern and the semiconductor pattern; A second insulating layer disposed between the semiconductor pattern and the gate; A third insulating layer disposed between either the source or the drain and the gate; and An interconnection pattern disposed on the third insulating layer, wherein the electrode pattern has a first bridging portion that does not overlap the semiconductor pattern, the gate has a second bridging portion that does not overlap the semiconductor pattern, and the interconnection pattern is electrically connected to the first bridging portion via a first through hole in the first insulating layer, the second insulating layer, and the third insulating layer, and is electrically connected to the second bridging portion via a second through hole in the third insulating layer.

8. The thin film transistor according to claim 1, wherein Further comprising: A first insulating layer disposed between the electrode pattern and the semiconductor pattern; A second insulating layer disposed between the semiconductor pattern and the gate; A third insulating layer disposed between either the source or the drain and the gate; And An interconnection pattern disposed on the third insulating layer, wherein the electrode pattern has a bridging portion that does not overlap the semiconductor pattern, the interconnection pattern extends from the source and is electrically connected to the bridging portion via a first through hole in the first insulating layer, the second insulating layer, and the third insulating layer, and the source is electrically connected to the semiconductor pattern via a second through hole in the second insulating layer and the third insulating layer.

9. The thin film transistor according to claim 1, wherein Wherein the semiconductor pattern has a first surface overlapping the electrode pattern and a second surface electrically contacting the source or the drain, and the first surface is farther from the substrate than the second surface.

10. The thin film transistor according to claim 1, characterized in that, Applicable to a gate driving circuit, wherein the gate driving circuit includes: An input circuit that receives a first-direction scanning signal, a second-direction scanning signal, a first timing driving signal, and a second timing driving signal to provide a first control signal; A first output circuit, receiving the first control signal and a first clock signal to provide a third timing driving signal and an isolation control signal; and A second output circuit, receiving the isolation control signal and the first clock signal to provide a gate driving signal, wherein the first output circuit and the second output circuit each have a thin film transistor. The source and the gate of the thin film transistor of the first output circuit respectively receive the first clock signal and the isolation control signal, the drain of the thin film transistor of the first output circuit provides the third timing driving signal, the source and the gate of the thin film transistor of the second output circuit respectively receive the first clock signal and the isolation control signal, and the drain of the thin film transistor of the second output circuit provides the gate driving signal.

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