LED chip and preparation method thereof

Abstract

The present invention relates to the technical field of light-emitting diode manufacturing, and in particular to an LED chip and a method for preparing the same. The method for preparing the LED chip comprises: providing an epitaxial wafer; forming an insulating layer and a first insulating layer opening; forming a photoresist layer, etching to form a second insulating layer opening; forming an Ag metal layer and a diffusion barrier layer, corroding and thinning the diffusion barrier layer and etching the sidewalls of the second insulating layer opening to form a third insulating layer opening; forming a protective layer; forming a passivation layer and a passivation layer opening; and forming a pad layer. The width of the protective layer is equal to the width of the diffusion barrier layer, and the distance between the sidewall of the pad layer and the sidewall of the diffusion barrier layer is equal to or greater than 10 μm. The implementation of the present invention can block the diffusion of Ag in the Ag metal layer, prevent it from combining with the pad layer to form an alloy, and greatly improve the reliability of the LED chip.

Description

Technical Field

[0001] The present invention relates to the technical field of light emitting diode manufacturing, and in particular to an LED chip and a preparation method thereof. Background Art

[0002] In the field of LED technology, reflective electrodes play a crucial role in improving the light extraction efficiency of LED chips. Traditional reflective electrode structures, such as Al / Ti / Pt / Au, can improve reflectivity to a certain extent, but they still have some drawbacks. For example, while Al has high reflectivity, its electrochemical properties are unstable and it easily oxidizes in air. This is especially true during the chip electrode fabrication process, where Al comes into contact with large amounts of halogen-containing chemicals, leading to problems such as electrode detachment. Therefore, Ag is often used as a reflective layer instead of Al. It not only offers higher reflectivity but also is more chemically stable than Al. However, Ag is susceptible to metal migration in high-temperature and high-humidity environments, bonding with the pad layer (typically Au), resulting in reduced electrode performance. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an LED chip and a preparation method thereof, which can effectively reduce Ag metal migration and improve the reliability of the LED chip.

[0004] In order to solve the above technical problems, the present invention provides a method for preparing an LED chip, which comprises the following steps:

[0005] S1. Providing an epitaxial wafer, forming an insulating layer on the epitaxial wafer, and forming a first insulating layer opening to obtain a first intermediate;

[0006] S2. forming a photoresist layer on the first intermediate, and forming a photoresist opening exposing the opening of the first insulating layer;

[0007] S3, etching the sidewall of the first insulating layer opening along the photoresist opening to form a second insulating layer opening on top of the first insulating layer opening;

[0008] S4, forming a reflective layer on the photoresist layer and in the photoresist opening to obtain a second intermediate; wherein the reflective layer includes an Ag metal layer and a diffusion barrier layer stacked in sequence; a gap is provided between the reflective layer and the photoresist layer to at least partially expose the sidewall of the opening of the second insulating layer;

[0009] S5. Corroding the second intermediate body with an etching solution to thin the diffusion barrier layer and etching the sidewalls of the second insulating layer opening to form a third insulating layer opening above the thinned diffusion barrier layer;

[0010] S6, forming a protective layer in the photoresist opening and removing the photoresist layer to obtain a third intermediate; the difference between the width of the protective layer and the width of the diffusion barrier layer is greater than or equal to 2 μm;

[0011] S7, forming a passivation layer on the third intermediate, and etching to form a passivation layer opening exposing the protective layer to obtain a fourth intermediate;

[0012] S8. Forming a pad layer on the fourth intermediate body; wherein a distance between a sidewall of the pad layer and a sidewall of the diffusion barrier layer is ≥10 μm.

[0013] As an improvement of the above technical solution, the insulating layer is a SiO2 layer or a silicon nitride layer, and its thickness is 7000Å~20000Å; and / or

[0014] The diffusion barrier layer is a TiW layer, and the thickness of the diffusion barrier layer before thinning is ≥1500Å; and / or

[0015] The etching solution is BOE etching solution.

[0016] As an improvement of the above technical solution, the insulating layer is a SiO2 layer with a thickness of 8000Å~12000Å;

[0017] The diffusion barrier layer is a TiW layer; the thickness of the diffusion barrier layer before thinning is 2000Å~5000Å;

[0018] The etching solution is BOE etching solution.

[0019] As an improvement to the above technical solution, the insulating layer is formed by PECVD, and the volume ratio of N2O to SiH4 gradually decreases during the formation process; and the volume ratio of N2O to SiH4 is between 10:1 and 20:1;

[0020] The content of Ti in the diffusion barrier layer is ≥30wt%;

[0021] The volume ratio of HF solution to NH4F solution in the etching solution is 1:4 to 1:6;

[0022] The distance between the sidewall of the opening of the third insulating layer and the edge of the diffusion barrier layer after etching is 2 μm to 5 μm.

[0023] As an improvement of the above technical solution, the process conditions for forming the insulating layer include: deposition temperature of 200℃~300℃, RF power of 80W~120W, SiH4 flow rate of 100sccm~200sccm, N2O flow rate of 1200sccm~3000sccm, and chamber pressure of 50Pa~100Pa.

[0024] As an improvement to the above technical solution, the protective layer includes a first sublayer and a second sublayer alternately stacked, the number of periods of which is 2 to 5, the first sublayer is a Ti layer or a TiW layer, and the second sublayer is a Pt layer or a Ni layer; the thickness of the first sublayer is 1000Å to 2000Å, and the thickness of the second sublayer is 200Å to 500Å; and / or

[0025] The thickness of the Ag metal layer is 1200Å~2000Å; and / or

[0026] The thickness of the diffusion barrier layer after thinning is 500Å~2000Å; and / or

[0027] The pad layer is an Au metal layer with a thickness of 5000Å~20000Å.

[0028] As an improvement of the above technical solution, the first sub-layer is a TiW layer, and its Ti content is ≤20wt%; the second sub-layer is a Ni layer.

[0029] As an improvement of the above technical solution, the difference between the width of the protective layer and the width of the diffusion barrier layer is 2 μm to 5 μm.

[0030] As an improvement of the above technical solution, the distance between the sidewall of the pad layer and the sidewall of the diffusion barrier layer is 10 μm to 15 μm.

[0031] Correspondingly, the present invention also discloses an LED chip, which is prepared by the above-mentioned method for preparing the LED chip.

[0032] The implementation of the present invention has the following beneficial effects:

[0033] The method for preparing an LED chip in one embodiment of the present invention includes: forming an insulating layer on an epitaxial wafer, etching the insulating layer once to form a first insulating layer opening, etching twice to form a second insulating layer opening on top of the first insulating layer opening, forming a reflective layer (Ag metal layer and diffusion barrier layer), thinning the diffusion barrier layer with an etchant, and etching to form a third insulating layer opening; forming a protective layer and a passivation layer, and forming a solder pad layer on the protective layer after the passivation layer opening. Based on the above preparation method, the width of the third insulating layer opening can be made greater than the width of the second insulating layer opening, and the width of the second insulating layer opening can be made greater than the width of the first insulating layer opening. Furthermore, the width of the protective layer minus the width of the diffusion barrier layer is ≥2μm, and the distance between the sidewalls of the solder pad layer and the sidewalls of the diffusion barrier layer is ≥10μm. This ensures that the protective layer completely covers the reflective layer, preventing the diffusion of Ag in the reflective layer. Moreover, since the distance between the sidewall of the diffusion barrier layer and the sidewall of the pad layer is far, even after Ag diffusion occurs, it is difficult for Ag to combine with the pad layer, thereby greatly improving the reliability of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 2 is a schematic diagram of the structure of the epitaxial wafer after step S12 in one embodiment of the present invention;

[0035] Figure 2 1 is a schematic structural diagram of the first intermediate before removing the first photoresist layer in step S15 in one embodiment of the present invention;

[0036] Figure 3 This is a schematic structural diagram of the first intermediate after step S3 in one embodiment of the present invention;

[0037] Figure 4 This is a schematic structural diagram of the second intermediate after step S4 in one embodiment of the present invention;

[0038] Figure 5 This is a schematic structural diagram of the second intermediate after step S5 in one embodiment of the present invention;

[0039] Figure 6 This is a schematic structural diagram of the third intermediate after step S6 in one embodiment of the present invention;

[0040] Figure 7 This is a schematic structural diagram of the fourth intermediate after step S7 in one embodiment of the present invention;

[0041] Figure 8 1 is a schematic structural diagram of an LED chip in one embodiment of the present invention;

[0042] In the figure, 1 is an epitaxial wafer, 11 is a substrate, 12 is a first semiconductor layer, 13 is an active layer, 14 is a second semiconductor layer, 15 is a conductive step, 16 is an isolation trench, 17 is a transparent conductive layer, 2 is an insulating layer, 211 is an N-type first insulating layer opening, 212 is a P-type first insulating layer opening, 221 is an N-type second insulating layer opening, 222 is a P-type second insulating layer opening, 231 is an N-type third insulating layer opening, 232 is a P-type third insulating layer opening, 3 is a first photoresist layer, 311 is an N-type first photoresist opening, 312 is a P-type first photoresist opening, 4 is a photoresist layer, 41 1 is an N-type photoresist opening, 412 is a P-type photoresist opening, 5 is a reflective layer, 51 is an Ag metal layer, 511 is an N-type Ag metal layer, 512 is a P-type Ag metal layer, 52 is a diffusion barrier layer, 521 is an N-type diffusion barrier layer, 522 is a P-type diffusion barrier layer, 6 is a protective layer, 61 is an N-type protective layer, 62 is a P-type protective layer, 7 is a passivation layer, 711 is an N-type passivation layer opening, 712 is a P-type passivation layer opening, 8 is a second photoresist layer, 811 is an N-type second photoresist opening, 812 is a P-type second photoresist opening, 91 is an N-type pad layer, and 92 is a P-type pad layer. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are merely used to explain the present application and are not intended to limit the present application.

[0044] In the description of this application, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the quantity of the technical features indicated. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more of the aforementioned features.

[0046] The present invention discloses a method for preparing an LED chip, which comprises the following steps:

[0047] S1. Providing an epitaxial wafer, forming an insulating layer on the epitaxial wafer, and forming a first insulating layer opening to obtain a first intermediate;

[0048] Specifically, in some embodiments, step S1 includes:

[0049] S11, providing epitaxial wafers;

[0050] The epitaxial wafer 1 includes a substrate 11 and an epitaxial layer. The epitaxial layer includes a first semiconductor layer 12, an active layer 13, and a second semiconductor layer 14 stacked in sequence on the substrate 11. The substrate 11 is a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited thereto. The first semiconductor layer 12 can be an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but is not limited thereto. The active layer 13 can be an InGaN-GaN type MQW layer, an InGaN-AlGaN type MQW layer, or an AlGaN-AlGaN type MQW layer, but is not limited thereto. The second semiconductor layer 14 can be a P-type GaN layer, a P-type AlGaN layer, or a P-type GaAs layer, but is not limited thereto.

[0051] Preferably, in one embodiment of the present invention, the epitaxial layer may further include one or more of a buffer layer, an intrinsic semiconductor layer, a stress buffer layer, an electron blocking layer, and an ohmic contact layer commonly used in the art, but is not limited thereto.

[0052] S12, etching the epitaxial wafer to form a conductive step exposing the first semiconductor layer;

[0053] Specifically, a mask (photoresist layer, SiO2 layer, etc.) can be first formed on the epitaxial wafer 1, and then the second semiconductor layer 14, the active layer 13 and part of the first semiconductor layer 12 in the preset area are removed by wet etching or dry etching to form a conductive step 15, but is not limited thereto.

[0054] Preferably, in some embodiments, a photoresist layer is first formed on the epitaxial wafer 1, and after being exposed, developed and patterned, an inductively coupled plasma etching process (ICP) is used to etch away the second semiconductor layer 14, the active layer 13 and part of the first semiconductor layer 12 in a predetermined area to form a conductive step 15. Further, in some embodiments, see Figure 1 , continue etching at a preset position until the substrate 11 is exposed to form an isolation groove 16 for isolating multiple LED chips, and finally remove the photoresist layer.

[0055] More preferably, in some embodiments, step S12 includes:

[0056] S121, etching the epitaxial wafer to form a conductive step;

[0057] Specifically, in this step, only the conductive step 15 is formed by etching, but the isolation trench 16 is not formed.

[0058] S122, forming a transparent conductive layer on the epitaxial wafer obtained in step S121;

[0059] The transparent conductive layer 17 may be, but is not limited to, an ITO layer, an IZO layer, an AZO layer, an ATO layer, or an FTO layer commonly used in the art. Preferably, the transparent conductive layer 17 is an ITO layer. The thickness of the transparent conductive layer 17 is 5 nm to 150 nm, preferably 50 nm to 150 nm.

[0060] S123, etching and removing the transparent conductive layer in the preset area, and retaining the transparent conductive layer on the second semiconductor layer;

[0061] Specifically, a mask (photoresist layer, SiO2 layer, etc.) can be first formed on the epitaxial wafer 1 obtained in step S122, and then the transparent conductive layer 17 in the preset area is removed by wet etching or dry etching, leaving only the transparent conductive layer 17 on the second semiconductor layer 14, but not limited to this.

[0062] S124, etching to form an isolation groove;

[0063] Specifically, a mask (photoresist layer, SiO2 layer, etc.) can be formed on the epitaxial wafer 1 obtained in step S123, and then the conductive steps 15 in the preset area are removed by wet etching or dry etching to form isolation trenches 16 that expose the substrate 11, but the present invention is not limited thereto.

[0064] It should be noted that, in some embodiments, before forming the conductive step 15 , a transparent conductive layer 17 is first formed on the epitaxial wafer 1 , and then the transparent conductive layer 17 is patterned, the conductive step 15 is formed, and the isolation trench 16 is formed by photolithography and etching processes.

[0065] S13, forming an insulating layer on the epitaxial wafer obtained in step S12;

[0066] Specifically, the insulating layer 2 is a stacked structure composed of one or at least two of, but not limited to, a SiO2 layer, an Al2O3 layer, a silicon nitride layer, or a silicon oxynitride layer. Preferably, in some embodiments, the insulating layer 2 is a SiO2 layer or a silicon nitride layer. These insulating layers 2 are easily thinned by wet etching to form first, second, and third insulating layer openings of specific morphologies, thereby providing a good foundation for the protective layer 6 to completely cover the reflective layer 5.

[0067] Specifically, the thickness of the insulating layer 2 is ≥ 6500 Å to prevent the sidewalls of the insulating layer 2 from being etched through during the subsequent wet etching process, thereby damaging the first semiconductor layer 12, the active layer 13, and the second semiconductor layer 14. Preferably, the thickness of the insulating layer 2 is 7000 Å to 20000 Å, and illustratively is 8200 Å, 9000 Å, 10000 Å, 12000 Å, 14000 Å, 16000 Å, or 18000 Å, but is not limited thereto. More preferably, the thickness of the insulating layer 2 is 8000 Å to 12000 Å.

[0068] Specifically, the insulating layer 2 can be formed by PECVD, ALD, or MOCVD, but is not limited thereto. The insulating layer 2 is formed on the surface of the epitaxial wafer obtained in step S12, and covers the surface and sidewalls of the first semiconductor layer 12, the surface and sidewalls of the second semiconductor layer 14, and the bottom of the isolation trench 16.

[0069] Preferably, in some embodiments, the insulating layer 2 is a SiO2 layer formed by PECVD. During the formation of the SiO2 layer, the volume ratio of N2O to SiH4 gradually decreases, and the volume ratio of N2O to SiH4 is between 10:1 and 20:1. Based on this process, the insulating layer 2 can present a gradually loosened structure from bottom to top, and then be rapidly corroded during subsequent etching with an etching solution to form a third insulating layer opening with a specific morphology. More preferably, the process conditions for depositing the SiO2 layer include: a deposition temperature of 200°C to 300°C, an RF power of 80W to 120W, a SiH4 flow rate of 100sccm to 200sccm, an N2O flow rate of 1200sccm to 3000sccm, and a chamber pressure of 50Pa to 100Pa.

[0070] S14, forming a first photoresist layer on the epitaxial wafer obtained in step S13, and exposing and developing the layer to form a first photoresist opening exposing the insulating layer;

[0071] Specifically, the first photoresist layer 3 can be formed by coating, baking and curing using a positive photoresist or a negative photoresist commonly used in the art, but is not limited thereto. Preferably, the first photoresist layer 3 is formed using a negative photoresist, which has higher resolution and contrast, and facilitates precise control of the shape and size of the first photoresist opening.

[0072] Specifically, see Figure 2 After exposure and development, a first photoresist opening is formed, exposing the insulating layer 2. The cross-section of the first photoresist opening is circular, square, elliptical, or other polygonal, and may vary depending on the photolithographic pattern. The longitudinal cross-section of the first photoresist opening is wide at the top and narrow at the bottom, which facilitates the smooth entry of the etching solution into the first photoresist opening during the subsequent wet etching process, uniformly etching the insulating layer 2 and ensuring that the morphology and size of the first insulating layer opening, the second insulating layer opening, and the third insulating layer opening are precisely controllable. Specifically, the first photoresist opening includes an N-type first photoresist opening 311 located above the conductive step and a P-type first photoresist opening 312 located above the second semiconductor layer. The opening shape and size of the N-type first photoresist opening 311 and the P-type first photoresist opening 312 are identical.

[0073] S15, etching the insulating layer along the first photoresist opening to form a first insulating layer opening exposing the first semiconductor layer and the second semiconductor layer, and then removing the first photoresist layer to obtain a first intermediate;

[0074] Specifically, the insulating layer 2 can be etched by wet etching or dry etching to form the first insulating layer opening, but is not limited thereto. Preferably, BOE etching solution is used for wet etching. Figure 2After etching, N-type first insulating layer openings 211 exposing the first semiconductor layer 12 and P-type first insulating layer openings 212 exposing the second semiconductor layer 14 or the transparent conductive layer 17 are formed. Specifically, the BOE etching solution in the present invention refers to a mixture of 49wt% HF aqueous solution and 40wt% NH4F aqueous solution mixed in different volume ratios. For example, the volume ratio of HF aqueous solution to NH4F aqueous solution can be 1:4, 1:5, 1:6, 1:7 or 1:8, but is not limited thereto. In addition, the BOE etching solution may also contain some surfactants commonly used in the art, but is not limited thereto.

[0075] Specifically, the cross-section of the first insulating layer opening is circular, square, elliptical, or other polygonal, and may vary depending on the photolithographic pattern. The width of the first insulating layer opening refers to the characteristic length of its cross-sectional shape. For example, if the cross-sectional shape is circular, it is the diameter; if the cross-sectional shape is square, it is the length of the long side; if the cross-sectional shape is elliptical, it is the length of the long axis; if the cross-sectional shape is other polygonal, it is the length of the longest side, and so on. It should be noted that the shapes and sizes of the N-type first insulating layer opening 211 and the P-type first insulating layer opening 212 are the same.

[0076] After the first insulating layer is opened, the first photoresist layer 3 can be removed by etching with an organic solvent or plasma to ensure a clean surface without residue, thereby providing a smooth surface for subsequent processes.

[0077] S2, forming a photoresist layer on the first intermediate, and forming a photoresist opening exposing the opening of the first insulating layer;

[0078] Specifically, the photoresist layer 4 can be formed using a positive photoresist or a negative photoresist through a coating, baking, and curing process, but is not limited thereto. Preferably, the photoresist layer 4 is formed using a negative photoresist, which has higher resolution and contrast, and facilitates precise control of the shape and size of the photoresist openings. This lays a good foundation for the subsequent formation of the second and third insulating layer openings.

[0079] Specifically, the cross-sectional shape of the photoresist opening is the same as that of the first photoresist opening, but the width of the photoresist opening is greater than that of the first photoresist opening, such that the width of the second insulating layer opening is greater than that of the first insulating layer opening. It should be noted that the width of the photoresist opening and the width of the first photoresist opening both refer to the characteristic length of their cross-sectional patterns. When the longitudinal cross-section of the photoresist opening is wide at the top and narrow at the bottom, the width of the first photoresist opening and the width of the photoresist opening both refer to the characteristic length of the cross-sectional pattern of the top surface.

[0080] Specifically, the longitudinal section of the photoresist opening is a structure that is wide at the top and narrow at the bottom, which facilitates the penetration of the etching solution and uniform etching of the insulating layer 2 to form the second insulating layer opening and the third insulating layer opening with specific morphology.

[0081] Specifically, the photoresist openings include N-type photoresist openings 411 and P-type photoresist openings 412, which respectively correspond to N-type first insulating layer openings 211 and P-type first insulating layer openings 212. The N-type photoresist openings 411 and P-type photoresist openings 412 have the same opening shape and size.

[0082] S3, etching the sidewalls of the first insulating layer opening along the second photoresist opening to form a second insulating layer opening on top of the first insulating layer opening;

[0083] Specifically, the sidewalls of the first insulating layer openings can be etched by wet etching or dry etching to form the second insulating layer openings, but the invention is not limited thereto. Preferably, BOE etching solution is used for wet etching. Figure 3 After etching, an N-type second insulating layer opening 221 is formed on the top of the N-type first insulating layer opening 211 , and a P-type second insulating layer opening 222 is formed on the top of the P-type first insulating layer opening 212 .

[0084] Specifically, the cross-sectional shape of the second insulating layer opening is identical to that of the first insulating layer opening, and can be circular, square, elliptical, or other polygonal shapes, but is not limited thereto. The width of the second insulating layer opening is greater than that of the first insulating layer opening to ensure that the subsequently formed protective layer 6 completely covers the reflective layer 5 and prevents Ag metal migration. The opening shape and size of the N-type second insulating layer opening 221 and the P-type second insulating layer opening 222 are identical.

[0085] Preferably, by controlling the width of the second insulating layer opening to be larger than the width of the photoresist opening, and then by jointly controlling the subsequent formation process of the reflective layer 5, a gap can be provided between the reflective layer 5 and the photoresist layer 4, ensuring that the side wall of the second insulating layer opening is subsequently corroded by the etching liquid to form a third insulating layer opening.

[0086] S4, forming a reflective layer on the photoresist layer and in the photoresist opening to obtain a second intermediate;

[0087] Specifically, the reflective layer 5 can be formed by, but is not limited to, PVD or evaporation processes. The reflective layer 5 includes, in a thickness direction, a stacked Ag metal layer 51 and a diffusion barrier layer 52. The diffusion barrier layer 52 not only effectively blocks Ag diffusion but also protects the Ag metal layer 51 during subsequent etching using an etching solution.

[0088] Specifically, in some embodiments, the diffusion barrier layer 52 is a TiW layer, which can not only effectively block the diffusion of Ag atoms and protect the Ag metal layer 51 during the corrosion process, but also have a suitable corrosion rate during the corrosion process, providing a guarantee for forming a third insulating layer opening with a specific morphology.

[0089] Specifically, the thickness of the diffusion barrier layer 52 formed in this step before thinning is ≥ 1200 Å to prevent it from being etched through during the etching process. Preferably, the thickness of the diffusion barrier layer 52 formed in this step before thinning is ≥ 1500 Å to maintain a certain thickness after etching and thinning, and then combine with the protective layer 6 to form a multi-layer protective structure to ensure the stability of the reflective layer 5 in high temperature and corrosive environments. Further preferably, the thickness of the diffusion barrier layer 52 before etching and thinning is 2000 Å to 5000 Å, and more preferably 3000 Å to 4000 Å, to ensure its stability and protective effect during the etching process.

[0090] Specifically, see Figure 4 The overall thickness of the reflective layer 5 is less than the depth of the first insulating layer opening to ensure a gap between it and the photoresist layer 4, thereby ensuring that the sidewalls of the second insulating layer opening can be subsequently etched by an etching solution to form a third insulating layer opening. Specifically, in some embodiments, the thickness of the Ag metal layer 51 is 1200Å to 2000Å, preferably 1500Å to 2000Å, to ensure reflective effect and structural stability.

[0091] Specifically, the Ag metal layer 51 includes an N-type Ag metal layer 511 formed within the N-type photoresist opening 411 and a P-type Ag metal layer 512 formed within the P-type photoresist opening 412. The N-type Ag metal layer 511 and the P-type Ag metal layer 512 have the same composition, thickness, width, and shape. The diffusion barrier layer 52 includes an N-type diffusion barrier layer 521 disposed on the N-type Ag metal layer 511 and a P-type diffusion barrier layer 522 disposed on the P-type Ag metal layer 512. The N-type diffusion barrier layer 521 and the P-type diffusion barrier layer 522 have the same composition, thickness, width, and shape.

[0092] S5. Corroding the second intermediate body with an etching solution to thin the diffusion barrier layer, and etching the sidewalls of the second insulating layer opening to form a third insulating layer opening above the thinned diffusion barrier layer;

[0093] Specifically, in some embodiments, BOE etching solution is used for etching, which can accurately control the etching depth and maintain the integrity of the reflective layer 5.

[0094] Specifically, see Figure 5 By etching with an etching solution, an N-type third insulating layer opening 231 is formed on top of the N-type second insulating layer opening 221; and a P-type third insulating layer opening 232 is formed on top of the P-type second insulating layer opening 222. The opening shape and size of the N-type third insulating layer opening 231 and the P-type third insulating layer opening 232 are identical.

[0095] Specifically, the cross-sectional shape of the third insulating layer opening is the same as that of the second insulating layer opening. The width of the third insulating layer opening is greater than that of the second insulating layer opening to ensure that the subsequently formed protective layer 6 completely covers the reflective layer 5 to prevent Ag migration.

[0096] Specifically, the thickness of the thinned diffusion barrier layer 52 is 300Å~2000Å, preferably 500Å~2000Å.

[0097] Specifically, the BOE etching solution has different etching rates on the diffusion barrier layer 52 and the insulating layer 2, thus affecting the specific morphology of the openings in the third insulating layer. The present invention controls the thickness of the insulating layer 2 to be between 7,000 Å and 20,000 Å, and the thickness of the diffusion barrier layer 52 to be ≥1,500 Å, to ensure the formation of openings in the third insulating layer with a low aspect ratio. Preferably, in some embodiments, the preparation conditions of the insulating layer 2 (SiO2 layer) are controlled to achieve a gradually loose structure; the Ti content in the diffusion barrier layer 52 (TiW layer) is controlled to be ≥30 wt%; and the volume fraction of the HF solution in the etching solution (BOE etching solution) is controlled to be ≥15 vol%. Through these controls, the BOE etching solution can achieve an appropriate etching rate for the diffusion barrier layer 52 (TiW layer) and the insulating layer 2 (SiO2 layer), thereby reducing the aspect ratio of the openings in the third insulating layer and forming a protective layer 6 with better encapsulation properties to prevent Ag metal migration. In addition, by controlling the Ti content in the diffusion barrier layer 52 (TiW layer) to ≥30wt%, its adhesion performance can be improved, which can effectively prevent the subsequent Ag metal layer 51 from warping and falling off due to agglomeration during high-temperature use, further improving the reliability of the LED chip.

[0098] More preferably, in some embodiments, when preparing the insulating layer 2 (SiO2 layer), the volume ratio of N2O to SiH4 is gradually reduced from 12:1 to 20:1; the Ti content in the diffusion barrier layer 52 (TiW layer) is controlled to be 32wt%~40wt%; and the volume ratio of the HF solution to the NH4F solution in the etching solution (BOE etching solution) is controlled to be 1:(4~6); through the above control, the distance between the sidewall of the opening of the third insulating layer after etching and the edge of the diffusion barrier layer 52 can be made to be 2μm~5μm, that is, the width (L1) of the protective layer 6 minus the width (L2) of the diffusion barrier layer 52 after thinning = 2μm~5μm (see Figure 6 ), thereby significantly reducing Ag migration and improving the reliability of the LED chip. It should be noted that the width of the protective layer 6 and the width of the diffusion barrier layer 52 (before and after thinning) are both the widths of their top surfaces.

[0099] S6, forming a protective layer in the photoresist opening, and removing the photoresist layer to obtain a third intermediate;

[0100] Specifically, a protective layer 6 can be formed in the photoresist opening and on the photoresist layer 4 by PVD or evaporation process, and then the photoresist layer 4 and the reflective layer 5 and protective layer 6 thereon are removed, but the present invention is not limited thereto. Figure 6 The protective layer 6 covers the reflective layer 5, and its width (L1) minus the width (L2) of the thinned diffusion barrier layer 52 is ≥ 2μm, so that it can further prevent the migration of the Ag metal layer 51 in the reflective layer 5. In addition, it should be noted that L1 and L2 correspond to the N-type protective layer 61 and the N-type diffusion barrier layer 521, and the P-type protective layer 62 and the P-type diffusion barrier layer 522, respectively. That is, the width of the N-type protective layer 61 minus the width of the thinned N-type diffusion barrier layer 521 is ≥ 2μm, and the width of the P-type protective layer 62 minus the width of the thinned P-type diffusion barrier layer 522 is ≥ 2μm.

[0101] Specifically, the protective layer 6 may be a Pt layer, an Au layer, a Ti layer, or a TiW layer, but is not limited thereto. Figure 6 The protective layer 6 includes an N-type protective layer 61 formed on the N-type diffusion barrier layer 521 and a P-type protective layer 62 formed on the P-type diffusion barrier layer 522 , and the composition, shape, width, and thickness of the two layers are the same.

[0102] Preferably, in some embodiments, the protective layer 6 comprises alternating first and second sublayers along its thickness, with a period of 2 to 5. The first sublayer is a Ti layer or a TiW layer, and the second sublayer is a Pt layer or a Ni layer. The thickness of the first sublayer is 1000 Å to 2000 Å, and the thickness of the second sublayer is 200 Å to 500 Å. This protective layer 6 further prevents Ag migration. More preferably, the first sublayer is a TiW layer, and the second sublayer is a Ni layer. The Ti content in the first sublayer is ≤ 20 wt%, as such a TiW layer provides a stronger barrier effect. More preferably, the Ti content in the first sublayer is 8 wt% to 12 wt%. It should be noted that the diffusion barrier layer 52 in the present invention utilizes a TiW layer with a high Ti content primarily to increase the etching rate of the etching solution and, in conjunction with the insulating layer 2 (SiO2 layer), form the third insulating layer openings with a specific morphology. However, a high Ti content has a low melting point, resulting in a weaker barrier effect against Ag diffusion. To this end, the present invention uses a first sub-layer with a low Ti content in the protective layer 6 to enhance the barrier effect against Ag diffusion.

[0103] S7, forming a passivation layer on the third intermediate, and etching to form a passivation layer opening exposing the protective layer to obtain a fourth intermediate;

[0104] Specifically, in some embodiments, step S7 includes:

[0105] S71, forming a passivation layer on the third intermediate;

[0106] Specifically, the passivation layer 7 is a stacked structure composed of one or more of a SiO2 layer, an Al2O3 layer, a silicon nitride layer, and a silicon oxynitride layer, but is not limited thereto. Preferably, in some embodiments, the passivation layer 7 is a SiO2 layer or an Al2O3 layer. Specifically, the thickness of the passivation layer 7 is 1000 Å to 3000 Å, preferably 1000 Å to 1500 Å.

[0107] Specifically, the passivation layer 7 can be formed by PECVD, ALD or MOCVD, but is not limited thereto. Preferably, a SiO2 layer is formed by PECVD as the passivation layer 7.

[0108] S72, forming a second photoresist layer on the third intermediate obtained in step S71, and exposing and developing the layer to form a second photoresist opening exposing the passivation layer;

[0109] Specifically, the second photoresist layer 8 can be formed by coating, baking and curing using a positive photoresist or a negative photoresist commonly used in the art, but is not limited thereto. Preferably, the second photoresist layer 8 is formed using a negative photoresist, which has higher resolution and contrast, and facilitates precise control of the shape and size of the second photoresist opening. Specifically, the second photoresist opening includes an N-type second photoresist opening 811 provided above the N-type protective layer 61 and a P-type second photoresist opening 812 provided on the P-type protective layer 62. The opening shape and size of the N-type second photoresist opening 811 and the P-type second photoresist opening 812 are the same.

[0110] Specifically, after exposure and development, a second photoresist opening is formed to expose the passivation layer 7, and its cross-section is circular, square, elliptical or other polygonal, but not limited thereto. Specifically, the width of the second photoresist opening is smaller than the width of the photoresist opening, so that the width of the subsequently formed passivation layer opening is smaller than the width of the second insulating layer opening, thereby making the distance L3 between the sidewall of the subsequently formed pad layer and the sidewall of the diffusion barrier layer 52 (see FIG. 1 ) smaller than the width of the second photoresist opening. Figure 8 ) ≥ 10μm. Even after Ag migration in the Ag metal layer 51, it is unlikely to form an alloy with the pad layer, thereby improving the reliability of the LED chip. Furthermore, it should be noted that L3 corresponds to the N-type pad layer 91 and the N-type diffusion barrier layer 521, and the P-type pad layer 92 and the P-type diffusion barrier layer 522, respectively. Specifically, the distance between the sidewalls of the N-type pad layer 91 and the N-type diffusion barrier layer 521 is ≥ 10μm, and the distance between the sidewalls of the P-type pad layer 92 and the P-type diffusion barrier layer 522 is ≥ 10μm.

[0111] Preferably, in some embodiments, the cross-sections of the first photoresist opening, the photoresist opening, and the second photoresist opening are all circular, and their projections on the surface of the substrate 11 are concentric circles; and the diameter of the photoresist opening - the diameter of the second photoresist opening is ≥2 μm, so as to further regulate the distance between the side wall of the passivation layer opening and the side wall of the diffusion barrier layer 52, so that the distance between the side wall of the subsequent pad layer and the side wall of the diffusion barrier layer 52 is 10 μm~15 μm, further improving the reliability of the LED chip.

[0112] S73, etching the passivation layer along the second photoresist opening to form a passivation layer opening exposing the protective layer, to obtain a fourth intermediate;

[0113] Specifically, the passivation layer 7 can be etched by wet etching or dry etching process to form, but is not limited thereto. Preferably, BOE etching solution is used for wet etching. Figure 7 After etching, an N-type passivation layer opening 711 exposing the N-type protective layer 61 and a P-type passivation layer opening 712 exposing the P-type protective layer 62 are formed. The opening shape and size of the N-type passivation layer opening 711 and the P-type passivation layer opening 712 are the same.

[0114] Specifically, the cross-section of the opening of the passivation layer is circular, square, elliptical or other polygonal, which may vary depending on the different photolithography patterns.

[0115] S8, forming a pad layer on the fourth intermediate;

[0116] Specifically, in some embodiments, step S8 includes:

[0117] S81, forming a pad layer on the second photoresist layer and in the second photoresist opening;

[0118] Specifically, a pad layer can be formed on the second photoresist layer 8 and within the second photoresist opening by PVD or evaporation, but is not limited thereto. The pad layer can be, but is not limited to, an Au layer or a Pt layer. Preferably, the pad layer is an Au metal layer with a thickness of 5000 Å to 20000 Å.

[0119] Specifically, see Figure 8 The pad layer includes an N-type pad layer 91 disposed above the N-type protective layer 61 and a P-type pad layer 92 disposed above the P-type protective layer 62. The N-type pad layer 91 is connected to the N-type protective layer 61 through the N-type passivation layer opening 711, and the P-type pad layer 92 is connected to the P-type protective layer 62 through the P-type passivation layer opening 712. The N-type pad layer 91 and the P-type pad layer 92 have the same composition, thickness, width, and shape.

[0120] S82, removing the second photoresist layer and the pad layer thereon to obtain a finished LED chip.

[0121] Specifically, the second photoresist layer 8 may be removed by using an organic solvent or plasma etching method to ensure a clean surface without residue, thereby providing a smooth surface for subsequent processes.

[0122] In summary, the preparation method of the LED chip in this embodiment includes: forming an insulating layer 2 on the epitaxial wafer, etching the insulating layer 2 once to form a first insulating layer opening, etching a second insulating layer opening on top of the first insulating layer opening to form a reflective layer 5 (Ag metal layer 51 and diffusion barrier layer 52), corroding and thinning the reflective layer 5 with a corrosive solution and etching to form a third insulating layer opening to form a protective layer 6 and a passivation layer 7, and forming a solder pad layer on the protective layer 6 after the passivation layer opening. Specifically, the width of the third insulating layer opening is greater than the width of the second insulating layer opening, so that the width of the protective layer 6 minus the width of the diffusion barrier layer 52 is ≥2μm, that is, the protective layer 6 completely covers the reflective layer 5, blocking the diffusion of Ag in the reflective layer 5. In addition, this embodiment also controls the distance between the side wall of the solder pad layer and the side wall of the diffusion barrier layer 52 (that is, Figure 8 L3) ≥ 10μm, which ensures that the pad layer is not easily combined with the diffused Ag, greatly improving the reliability of the LED chip. Specifically, the aging time of the LED chip obtained by the preparation method of this embodiment can reach 960h~1200h, while the aging time of the traditional LED chip based on the Ag reflective layer is only 360h~408h. The aging experiment process is as follows: the LED chip is subjected to an aging experiment under the conditions of 85℃ and 85%RH, and the LED chip is tested with a reverse voltage of -10V every 24h to obtain the reverse leakage current value. This reverse leakage current value is recorded. When this value is greater than 0.5μA, it means that the LED chip has failed, and the current time node is recorded as the aging time.

[0123] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0124] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing an LED chip, characterized in that: The following steps are involved: S1. Providing an epitaxial wafer, forming an insulating layer on the epitaxial wafer, and forming a first insulating layer opening to obtain a first intermediate; S2. forming a photoresist layer on the first intermediate, and forming a photoresist opening exposing the opening of the first insulating layer; S3, etching the sidewall of the first insulating layer opening along the photoresist opening to form a second insulating layer opening on top of the first insulating layer opening; S4, forming a reflective layer on the photoresist layer and in the photoresist opening to obtain a second intermediate; wherein the reflective layer includes an Ag metal layer and a diffusion barrier layer stacked in sequence; a gap is provided between the reflective layer and the photoresist layer to at least partially expose the sidewall of the opening of the second insulating layer; S5. Corroding the second intermediate body with an etching solution to thin the diffusion barrier layer and etching the sidewalls of the second insulating layer opening to form a third insulating layer opening above the thinned diffusion barrier layer; S6, forming a protective layer in the photoresist opening and removing the photoresist layer to obtain a third intermediate; the difference between the width of the protective layer and the width of the diffusion barrier layer is greater than or equal to 2 μm; S7, forming a passivation layer on the third intermediate, and etching to form a passivation layer opening exposing the protective layer to obtain a fourth intermediate; S8. Forming a pad layer on the fourth intermediate body; wherein a distance between a sidewall of the pad layer and a sidewall of the diffusion barrier layer is ≥10 μm.

2. The method for preparing an LED chip according to claim 1, wherein: The insulating layer is a SiO2 layer or a silicon nitride layer, and its thickness is 7000Å~20000Å; and / or The diffusion barrier layer is a TiW layer, and the thickness of the diffusion barrier layer before thinning is ≥1500Å; and / or The etching solution is BOE etching solution.

3. The method for preparing an LED chip according to claim 1, wherein: The insulating layer is a SiO2 layer with a thickness of 8000Å~12000Å; The diffusion barrier layer is a TiW layer; the thickness of the diffusion barrier layer before thinning is 2000Å~5000Å; The etching solution is BOE etching solution.

4. The method for preparing an LED chip according to claim 3, wherein: The insulating layer is formed by PECVD, and the volume ratio of N2O to SiH4 gradually decreases during the formation process; and the volume ratio of N2O to SiH4 is between 10:1 and 20:1; The content of Ti in the diffusion barrier layer is ≥30wt%; The volume ratio of HF solution to NH4F solution in the etching solution is 1:4 to 1:6; The distance between the sidewall of the opening of the third insulating layer and the edge of the diffusion barrier layer after etching is 2 μm to 5 μm.

5. The method for preparing an LED chip according to claim 3, wherein: The process conditions for forming the insulating layer include: a deposition temperature of 200° C. to 300° C., a radio frequency power of 80W to 120W, a SiH 4 flow rate of 100 sccm to 200 sccm, a N 2 O flow rate of 1200 sccm to 3000 sccm, and a chamber pressure of 50 Pa to 100 Pa.

6. The method for preparing an LED chip according to claim 1, wherein: The protective layer comprises a first sublayer and a second sublayer alternately stacked, the number of cycles of which is 2 to 5, the first sublayer is a Ti layer or a TiW layer, and the second sublayer is a Pt layer or a Ni layer; the thickness of the first sublayer is 1000Å to 2000Å, and the thickness of the second sublayer is 200Å to 500Å; and / or The thickness of the Ag metal layer is 1200Å~2000Å; and / or The thickness of the diffusion barrier layer after thinning is 500Å~2000Å; and / or The pad layer is an Au metal layer with a thickness of 5000Å~20000Å.

7. The method for preparing an LED chip according to claim 6, wherein: The first sub-layer is a TiW layer, and the Ti content thereof is ≤20wt%; the second sub-layer is a Ni layer.

8. The method for preparing an LED chip according to claim 1, wherein: The difference between the width of the protective layer and the width of the diffusion barrier layer is 2 μm to 5 μm.

9. The method for preparing an LED chip according to claim 1, wherein: The distance between the sidewall of the pad layer and the sidewall of the diffusion barrier layer is 10 μm to 15 μm.

10. An LED chip, characterized in that: The LED chip is prepared by the method for preparing the LED chip according to any one of claims 1 to 9.

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