Semiconductor package manufacturing method

Abstract

According to the invention, the warping of the wafer is inhibited in a semiconductor packaging production process using the underlying filler. In the filling step, a photosensitive resin is filled as a first underfill along a periphery of each of a plurality of integrated circuits that have been bonded to a wafer. In the exposure process, the first underlying filler is cured by exposure. In the sealing step, the plurality of integrated circuits and the first underfill are sealed with a sealant. In the dicing step, the wafer is divided into a predetermined number of semiconductor chips.

Description

Technical Field

[0001] The present technology relates to a method for manufacturing a semiconductor package. Specifically, the present technology relates to a method for manufacturing a semiconductor package including a wafer-level process. Background Art

[0002] In the prior art, in the manufacturing process before dicing, an underfill is used to suppress warping of a wafer. For example, a manufacturing method has been proposed in which, after die bonding, dams are formed between chips, the peripheral portion of the wafer is filled with an underfill, and then the dams are removed (for example, see Patent Document 1).

[0003] Citation List

[0004] Patent Document

[0005] Patent Document 1: Specification of U.S. Patent No. 10504824 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] In the above technique of the prior art, warping of the wafer due to subsequent heat treatment is suppressed by filling the peripheral portion of the wafer with an underfill. However, in the case where a stress greater than a desired stress is generated on the wafer, the wafer warps.

[0008] In view of this situation, the present technology has been made, and an object of the present technology is to suppress warping of a wafer in a semiconductor package manufacturing process using an underfill.

[0009] Solutions to the Problems

[0010] The present technology has been made to solve the above problems, and a first aspect of the present technology is a method for manufacturing a semiconductor package, including: a filling step of filling a portion along the periphery of each of a plurality of integrated circuits bonded to a wafer with a photosensitive resin as a first underfill; an exposure step of curing the first underfill by exposure; a sealing step of sealing the plurality of integrated circuits and the first underfill with a sealing material; and a dicing step of dividing the wafer into a predetermined number of semiconductor chips. This brings an effect of suppressing warping of the wafer.

[0011] Furthermore, in the first aspect, the method for manufacturing a semiconductor package may further include: a patterning step of forming a grid-like dam pattern on the wafer before the filling step. This brings an effect of separating each integrated circuit.

[0012] Furthermore, in the first aspect, laser processing and surface modification may be performed in the patterning step. This brings an effect of suppressing warping.

[0013] In addition, in the first aspect, the patterning process may include: a process of forming a resist with a predetermined gap between multiple integrated circuits, and a process of forming dams through plasma treatment. This brings the effect of suppressing warping.

[0014] In addition, in the first aspect, the patterning process may include: a process of forming a resist on the entire surface of the wafer; and a process of removing the resist while leaving a grid-like portion through lithography. This brings the effect of suppressing warping.

[0015] In addition, in the first aspect, the ratio of the thickness of the sealing material to the thickness of the integrated circuit may be not less than 0.5. This brings the effect of suppressing warping.

[0016] In addition, in the first aspect, in the filling process, the first underfill may be used for filling such that when viewed from a direction parallel to the substrate plane of the wafer, the first underfill has a rounded corner shape. This brings the effect of improving the warping suppression effect.

[0017] In addition, in the first aspect, the multiple integrated circuits may include external integrated circuits adjacent to the periphery of the wafer and internal integrated circuits not corresponding to the external integrated circuits, and in the filling process, the portions along the inner side of the external integrated circuits and the periphery of the internal integrated circuits may be filled with the first underfill. This brings the effect of improving the warping suppression effect.

[0018] In addition, in the first aspect, in the filling process, the portions along the partial periphery of each of the multiple integrated circuits may be filled with the first underfill. This brings the effect of improving the warping suppression effect.

[0019] In addition, in the first aspect, the contact angle of the portion of the first underfill in contact with the wafer may be any one of 30°, 45°, and 60°. This brings the effect of improving the warping suppression effect.

[0020] In addition, in the first aspect, a part of the first underfill may be in contact with the sidewall of the integrated circuit. This brings the effect of improving the warping suppression effect.

[0021] In addition, in the first aspect, the semiconductor package manufacturing method may further include: a patterning process of forming a grid-like dam on the wafer before the filling process, when viewed from a direction perpendicular to the substrate, each integrated circuit may have a rectangular shape; when viewed from a direction perpendicular to the substrate, the region surrounded by the dam may have a rectangular shape, and when viewed from a direction perpendicular to the substrate, the distance from one side of the four sides of each integrated circuit to the inner wall of the dam may be greater than the distances from the remaining three sides to the inner wall of the dam. This brings the effect of facilitating filling with the underfill.

[0022] In addition, in the first aspect, the semiconductor package manufacturing method may further include: a patterning process of forming a grid-shaped dam in the wafer before the filling process, and when viewed from a direction perpendicular to the substrate, an outwardly protruding U-shaped recess may be formed in the area surrounded by the dam. This brings the effect of facilitating the filling with underfill.

[0023] In addition, in the first aspect, the semiconductor package manufacturing method may further include: a patterning process of forming a grid-shaped dam on the wafer before the filling process, and some of the dams may have steps. This brings the effect of facilitating the filling with underfill.

[0024] In addition, in the first aspect, the semiconductor package manufacturing method may further include: a patterning process of forming a grid-shaped dam on the wafer before the filling process, and some of the dams may have inclined surfaces. This brings the effect of facilitating the filling with underfill.

[0025] In addition, in the first aspect, the semiconductor package manufacturing method may further include: a patterning process of forming a grid-shaped dam on the wafer before the filling process, and a predetermined number of slits may be formed in some of the dams. This brings the effect of facilitating the filling with underfill.

[0026] In addition, in the first aspect, a predetermined number of trenches may be formed in the wafer. This brings the effect of facilitating the filling with underfill.

[0027] In addition, in the first aspect, the semiconductor package manufacturing method may further include: a process of mounting a semiconductor chip on a substrate, a process of arranging passive components around the semiconductor chip, a process of sealing the passive components with a molding resin, and a process of performing filling with a second underfill. This brings the effect of reducing man-hours.

[0028] In addition, in the first aspect, the semiconductor package manufacturing method may further include: a process of mounting a semiconductor chip in a cavity provided in a substrate, a process of filling the cavity with a second underfill, and a process of arranging passive components around the cavity. This brings the effect of reducing man-hours.

[0029] In addition, in the first aspect, the semiconductor package manufacturing method may further include: a process of mounting a semiconductor chip on a substrate, a process of arranging passive components around the semiconductor chip, a process of sealing the passive components with a substrate material, a process of performing filling with a second underfill, and a process of setting surface mount technology components on the substrate material. This brings the effect of reducing the coverage area. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a view for explaining the die bonding process in the first embodiment of the present technology.

[0031] Figure 2 It is a view for explaining the patterning process in the first embodiment of the present technology.

[0032] Figure 3 It is a view for explaining the underfill filling process in the first embodiment of the present technology.

[0033] Figure 4 It is a view for explaining the underfill removal process in the first embodiment of the present technology.

[0034] Figure 5 It is a view for explaining the sealing process in the first embodiment of the present technology.

[0035] Figure 6 It is a flowchart showing an example of the manufacturing method in the first embodiment of the present technology.

[0036] Figure 7 It is a view showing an example of a plan view and a cross-sectional view of a wafer when forming an underfill in a comparative example.

[0037] Figure 8 It is a view for explaining the resist film formation process in the first modification of the first embodiment of the present technology.

[0038] Figure 9 It is a view for explaining the process up to resist removal in the first modification of the first embodiment of the present technology.

[0039] Figure 10 It is a view for explaining the resist film formation process in the second modification of the first embodiment of the present technology.

[0040] Figure 11 It is a view for explaining the lithography process in the second modification of the first embodiment of the present technology.

[0041] Figure 12 It is a view comparing the corresponding characteristics of the first embodiment, each modification, and the comparative example of the present technology.

[0042] Figure 13 It is a view for explaining the underfill filling process in the second embodiment of the present technology.

[0043] Figure 14 It is a view for explaining the sealing process in the second embodiment of the present technology.

[0044] Figure 15 It is a flowchart showing an example of the manufacturing method in the second embodiment of the present technology.

[0045] Figure 16It is a view for comparing the corresponding characteristics of the second embodiment of the present technology and each comparative example.

[0046] Figure 17 It is a view of an example showing a plan view and a cross-sectional view of a wafer when forming an underfill in the third embodiment of the present technology.

[0047] Figure 18 It is a view of an example showing a cross-sectional view of a wafer when forming an underfill in the first modification of the third embodiment of the present technology.

[0048] Figure 19 It is a view of an example showing a cross-sectional view of a wafer when forming an underfill in the second modification of the third embodiment of the present technology.

[0049] Figure 20 It is a view of an example showing a plan view and a cross-sectional view of a wafer when forming an underfill in the third modification of the third embodiment of the present technology.

[0050] Figure 21 It is a view of an example showing a cross-sectional view of a wafer when forming an underfill in the fourth modification of the third embodiment of the present technology.

[0051] Figure 22 It is a view of an example showing a cross-sectional view of a wafer when forming an underfill in the fifth modification of the third embodiment of the present technology.

[0052] Figure 23 It is a view for comparing the corresponding characteristics of the third embodiment of the present technology, each modification, and each comparative example.

[0053] Figure 24 It is a view of an example showing a plan view and a cross-sectional view of a wafer during patterning in the fourth embodiment of the present technology.

[0054] Figure 25 It is a view of an example showing a plan view of a dam in the first modification of the fourth embodiment of the present technology.

[0055] Figure 26 It is a view of an example showing a wafer and a dam in the second modification of the fourth embodiment of the present technology.

[0056] Figure 27 It is a view of an example showing a wafer and a dam in the third modification of the fourth embodiment of the present technology.

[0057] Figure 28 It is a view of an example showing a top view and a cross-sectional view of a wafer filled with an underfill in the fourth modification of the fourth embodiment of the present technology.

[0058] Figure 29 It is a view showing another embodiment of the trench and the dam in the fourth modification of the fourth embodiment of the present technology.

[0059] Figure 30 It is a view for explaining the die bonding process in the fifth embodiment of the present technology.

[0060] Figure 31 It is a view for explaining the component arrangement process in the fifth embodiment of the present technology.

[0061] Figure 32 It is a view for explaining the sealing process in the fifth embodiment of the present technology.

[0062] Figure 33 It is a view for explaining the underfill filling process in the fifth embodiment of the present technology.

[0063] Figure 34 It is a flowchart showing an example of the manufacturing method in the fifth embodiment of the present technology.

[0064] Figure 35 It is a cross-sectional view showing an example of the semiconductor package in the comparative example.

[0065] Figure 36 It is a view for explaining the die bonding process in the first modification of the fifth embodiment of the present technology.

[0066] Figure 37 It is a view for explaining the underfill filling process in the first modification of the fifth embodiment of the present technology.

[0067] Figure 38 It is a view for explaining the component arrangement process in the first modification of the fifth embodiment of the present technology.

[0068] Figure 39 It is a view for explaining the die bonding process in the second modification of the fifth embodiment of the present technology.

[0069] Figure 40 It is a view for explaining the lower component arrangement process in the second modification of the fifth embodiment of the present technology.

[0070] Figure 41 It is a view for explaining the sealing process in the second modification of the fifth embodiment of the present technology.

[0071] Figure 42 It is a view for explaining the underfill filling process in the second modification of the fifth embodiment of the present technology.

[0072] Figure 43It is a view for explaining the upper component arrangement process in the second modification of the fifth embodiment of the present technology.

[0073] Figure 44 It is a block diagram showing a schematic configuration example of a vehicle control system.

[0074] Figure 45 It is an explanatory diagram showing an example of the installation position of an imaging unit. Detailed implementation manners

[0075] The modes for implementing the present technology (hereinafter referred to as embodiments) will be described below. The description will be given in the following order.

[0076] 1. First Embodiment (Example of filling with an underfill after patterning)

[0077] 2. Second Embodiment (Example of filling with an underfill without patterning)

[0078] 3. Third Embodiment (Example of filling with an underfill to have a filler shape)

[0079] 4. Fourth Embodiment (Example of filling with an underfill after patterning with a changed shape)

[0080] 5. Fifth Embodiment (Example of filling with an underfill after patterning and mounting on a substrate after cutting)

[0081] 6. Application examples of mobile bodies

[0082] <1. First Embodiment>

[0083] [Method for manufacturing a semiconductor package]

[0084] Reference will be made to Figures 1 to 5 to describe the method for manufacturing a semiconductor package in the first embodiment.

[0085] First, as Figure 1 shown, a plurality of integrated circuits are bonded (i.e., die bonding) to a wafer 130. In the drawings, a is an example of a plan view of the wafer 130, and b is an example of a cross-sectional view taken along a line X1-X2 in a of the drawings.

[0086] The thick-frame rectangle in a of the drawings represents an integrated circuit 110 adjacent to the periphery of the wafer 130. The other rectangles represent integrated circuits 111 inside the integrated circuit 110. In addition, a predetermined axis parallel to the substrate plane of the wafer 130 is set as the "X-axis", and an axis perpendicular to the substrate plane is set as the "Z-axis". An axis perpendicular to the X-axis and the Z-axis is set as the "Y-axis".

[0087] In the drawings, b is a cross-sectional view when observed from the Y-axis direction. In b of the drawings, only the right ends of a plurality of internal integrated circuits 111 are shown, and the rest is omitted. Further, the integrated circuits 110 and 111 are joined to the wafer 130 through a plurality of electrodes 140, and the wafer-circuit distance from the substrate plane of the wafer 130 to the lower end of the integrated circuit 110, etc. is H0.

[0088] When observed from the Z-axis direction, the wafer 130 has a grid shape, and when observed from the X-axis direction or the Y-axis direction, portions protruding from the substrate plane are formed by laser processing. Each of the integrated circuits 110 and 111 is arranged in each region surrounded by the grid-like portions.

[0089] Next, as Figure 2 shown, surface modification for imparting hydrophobicity to the grid-like portions is performed. The portions subjected to the surface modification are referred to as dams 131. In the drawings, a is an embodiment of a plan view of the wafer 130, and b is an embodiment of a cross-sectional view taken along the line segment X1-X2 in a of the drawings.

[0090] Subsequently, as Figure 3 shown, portions along the periphery of each of the integrated circuits 110 and 111 are filled with a photosensitive resin (such as an ultraviolet curable resin) as an underfill 120. In the drawings, a is an embodiment of a plan view of the wafer 130, and b is an embodiment of a cross-sectional view taken along the line segment X1-X2 in a of the drawings.

[0091] For example, an acrylic resin, an epoxy resin, a silicone resin, an epoxy resin containing an inorganic filler, etc. are used as the underfill 120. The regions filled with the underfill 120 are separated for each integrated circuit by the grid-like dams 131, and thus, each region can be uniformly filled with the underfill 120.

[0092] Then, the underfill 120 is cured by ultraviolet irradiation or the like.

[0093] Next, as Figure 4 shown, the dams 131 are removed by laser processing or the like. Then, in various processes (such as processes for forming circuits or solder balls on the wafer 130), heat treatment is performed on the wafer 130. Further, the wafer 130 can be ground to be very thin. The underfill 120 can sufficiently suppress warping of the wafer 130 during the heat treatment or grinding.

[0094] Subsequently, as Figure 5As shown, the portion between the integrated circuits is sealed by a sealing material 150. In the drawings, a is an embodiment of a plan view of a wafer 130, and b is an embodiment of a cross-sectional view taken along line segment X1-X2 in a of the drawings. Note that although only the portion between the integrated circuits is filled with the sealing material 150, the entire surface of the wafer 130 including the upper portions of each integrated circuit (except for the portion between the integrated circuits) may be covered by the sealing material 150.

[0095] Then, the wafer 130 is divided into a predetermined number of semiconductor chips by dicing. Each semiconductor chip is mounted on a substrate. Thus, a semiconductor package is manufactured.

[0096] Figure 6 is a flowchart showing an embodiment of a manufacturing method in the first embodiment of the present technology. A plurality of integrated circuits are bonded (i.e., die bonding) to the wafer 130 (step S901). Next, a dam 131 is formed (step S902), and filling is performed using an underfill 120 (step S903). Then, the underfill 120 is cured by exposure (step S904). Subsequently, the dam 131 is removed (step S905), and various heat treatments are performed (step S906). Then, the portion between the integrated circuits is sealed with the sealing material 150 (step S907), and dicing is performed (step S908). After dicing, various processes (such as the process of mounting on a substrate) are performed to manufacture a semiconductor package.

[0097] Here, as described in Patent Document 1, a manufacturing method in which the underfill 120 is formed only on the peripheral portion of the wafer 130 is assumed as a comparative example.

[0098] Figure 7 is a view showing an embodiment of a plan view and a cross-sectional view of the wafer 130 when the underfill is formed in the comparative example. In the drawings, a is an embodiment of a plan view of the wafer 130, and b is an embodiment of a cross-sectional view taken along line segment X1-X2 in a of the drawings.

[0099] In the case where the underfill 120 has a relatively high viscosity, the underfill 120 is less likely to penetrate under the integrated circuit, and if the underfill 120 is applied to the entire surface, unevenness will occur. In this case, as shown in the drawings, only the peripheral portion of the wafer 130 (more specifically, the region along the periphery of each external integrated circuit 110 and its lower portion) is filled with the underfill 120. On the other hand, the periphery and lower portion of each internal integrated circuit 110 are not filled with the underfill 120.

[0100] In the comparative example, when a stress greater than the desired stress is applied during heat treatment or polishing in a subsequent stage, the wafer 130 may warp. Such warping may reduce the yield of semiconductor packages.

[0101] On the other hand, in the first embodiment, the underfill 120 is filled not only in the portions around each external integrated circuit 110 but also in the portions around each internal integrated circuit 111, and thus, warping of the wafer 130 can be sufficiently suppressed. In addition, the respective integrated circuits are separated by the hydrophobic dams 131, and thus, even the underfill 120 having a relatively low viscosity can be uniformly filled.

[0102] As described above, according to the first embodiment of the present technology, the underfill 120 is filled in the portions around each of the integrated circuits 110 and 111, so that warping of the wafer 130 can be sufficiently suppressed.

[0103] [First Modification Example]

[0104] In the above-described first embodiment, the grid-like patterning is performed by laser processing and surface modification, but the patterning process is not limited to this method. The manufacturing method in the first modification example of the first embodiment is different from the manufacturing method of the first embodiment in that patterning is performed by resist film formation and plasma processing.

[0105] Reference will be made to Figure 8 and Figure 9 to describe the patterning process in the first modification example of the first embodiment.

[0106] As Figure 8 shown, after die bonding, a resist 200 for protecting against plasma is formed between the integrated circuits 110 and 111 while leaving grid-like gaps. In the drawing, a is an example of a plan view of the wafer 130, and b is an example of a cross-sectional view taken along the line X1-X2 in a of the drawing.

[0107] Next, as Figure 9 shown in a, dams 210 are formed in the grid-like regions without the resist 200 by plasma processing. Then, as shown in b of the drawing, the resist 200 is removed. Then, each process after filling with the underfill 120 is performed in a manner similar to the first embodiment.

[0108] As described above, according to the first modification example of the first embodiment of the present technology, patterning can be performed by resist film formation and plasma processing.

[0109] [Second Modification Example]

[0110] In the first embodiment described above, patterning is performed by laser processing and surface modification, but the patterning process is not limited to this method. The manufacturing method in the second modification of the first embodiment differs from the manufacturing method of the first embodiment in that patterning is performed by resist and photolithography.

[0111] Reference will be made to Figure 10 and Figure 11 to describe the patterning process in the second modification of the first embodiment.

[0112] As Figure 10 shown, after die bonding, a photosensitive resist 220 is formed on the entire surface of the wafer 130. In the drawings, a is an example of a plan view of the wafer 130, and b is an example of a cross-sectional view taken along the line X1-X2 in a of the drawings.

[0113] Then, as Figure 11 shown, the resist 220 is removed by photolithography, leaving only the grid-like portion. The remaining portion serves as a dam 221. When the resist 220 is negative, a mask with grid-like gaps is used. On the other hand, when the resist 220 is positive, a grid-like mask is used. In the drawings, a is an example of a plan view of the wafer 130, and b is an example of a cross-sectional view taken along the line X1-X2 in a of the drawings. Then, in a manner similar to the first embodiment, each process after filling with the underfill 120 is performed.

[0114] As described above, according to the second modification of the first embodiment of the present technology, patterning can be performed by resist film formation and photolithography.

[0115] Figure 12 is a view comparing the first embodiment, each modification, and the comparative example of the present technology.

[0116] In the drawings, the warpage and internal stress of the wafer 130 are measured. The degree of warpage is evaluated at four stages A, B, C, and D. In a 300-millimeter (mm) wafer 130, warpage less than 50 micrometers (μm) is evaluated as "A", and warpage equal to or greater than 50 micrometers (μm) and less than 100 micrometers (μm) is evaluated as "B". Warpage equal to or greater than 100 micrometers (μm) and less than 250 micrometers (μm) is evaluated as "C", and warpage equal to or greater than 250 micrometers (μm) is evaluated as "D".

[0117] In addition, internal stress is also evaluated in four stages A, B, C, and D. In a 300-millimeter (mm) wafer 130, an internal stress less than 5 megapascals (MPa) is evaluated as "A", and an internal stress equal to or greater than 5 megapascals (MPa) and less than 10 megapascals (MPa) is evaluated as "B". An internal stress equal to or greater than 10 megapascals (MPa) and less than 20 megapascals (MPa) is evaluated as "C", and an internal stress equal to or greater than 20 megapascals (MPa) is evaluated as "D".

[0118] In the first embodiment where patterning is performed by laser processing and surface modification, the warpage in this case is evaluated as "C", and the internal stress is evaluated as "C". In addition, in the first modification of the first embodiment where patterning is performed by resist film formation and plasma processing, the warpage in this case is evaluated as "B", and the internal stress is evaluated as "B". In addition, in the second modification of the first embodiment where patterning is performed by resist film formation and lithography, the warpage in this case is evaluated as "A", and the internal stress is evaluated as "B".

[0119] On the other hand, in the comparative example where patterning is performed by capillary action, the warpage in this case is evaluated as "D", and the internal stress is evaluated as "B".

[0120] As shown in the drawings, compared with the comparative example, warpage can be suppressed according to the first embodiment and its first and second modifications. In addition, the internal stress can be suppressed below the internal stress of the comparative example.

[0121] <2. Second Embodiment>

[0122] In the above first embodiment, the grid-shaped dam 131 is formed, but this configuration requires a patterning process and a process for removing the dam 131. The manufacturing method of the second embodiment is different from the manufacturing method of the first embodiment in that the entire surface of the wafer 130 is filled with the underfill 120.

[0123] Reference will be made to Figure 13 and Figure 14 to describe the manufacturing method in the second embodiment.

[0124] As Figure 13 shown, after die bonding, the entire surface of the wafer 130 is filled with the underfill 120. The upper surface of the underfill 120 is flat. In the drawings, a is an example of a plan view of the wafer 130, and b is an example of a cross-sectional view taken along the line X1-X2 in a of the drawings. Then, the underfill 120 is cured by exposure.

[0125] Then, as Figure 14As shown, the entire surface is sealed with a sealing material 150. Here, the height (in other words, the thickness) from the lower surface to the upper surface of each of the integrated circuits 110 and 111 is defined as H2. The height (in other words, the thickness) from the lower surface to the upper surface of the sealing material 150 is defined as H3. The ratio H3 / H2 of the height (thickness) H3 of the sealing material 150 to the height (thickness) H2 of the integrated circuit is preferably not less than 0.5.

[0126] Figure 15 is a flowchart showing an example of a manufacturing method in the second embodiment of the present technology. A wafer 130 is bonded to a plurality of integrated circuit dies (step S901), and filling is performed using an underfill 120 (step S903). Then, the underfill 120 is cured by exposure (step S904). Subsequently, various heat treatments are performed (step S906). Then, the portion between the integrated circuits is sealed with a sealing material 150 (step S907), and dicing is performed (step S908).

[0127] As shown in the drawings, when the entire surface of the wafer 130 is filled with the underfill 120, it is not necessary to form and remove the dam 131.

[0128] Figure 16 is a view comparing the corresponding characteristics between the second embodiment of the present technology and each comparative example. In the drawings, in a manner similar to the first embodiment, the warpage and internal stress of the wafer 130 are evaluated at four stages A, B, C, and D.

[0129] In the second embodiment, the entire surface of the wafer 130 is filled with the underfill 120, and H3 / H2, which is the ratio of the height (thickness) H3 of the sealing material 150 to the height (thickness) H2 of the integrated circuit, is set to be equal to or higher than 0.5. In the first setting example of the second embodiment, H3 / H2 is set to 2, and in the second setting example, H3 / H2 is set to 1. In addition, in the third setting example of the second embodiment, H3 / H2 is set to 0.6, and in the fourth setting example, H3 / H2 is set to 0.5.

[0130] Here, the portion between the integrated circuits is not filled with the underfill 120, and the case where H3 / H2 is set to 1 is defined as the first comparative example. In addition, the case where the entire surface of the wafer 130 is filled with the underfill 120 and H3 / H2 is set to 0.4 is defined as the second comparative example.

[0131] In the first setting example, the warpage is evaluated as "C", and the internal stress is evaluated as "C". In the second setting example, the warpage is evaluated as "B", and the internal stress is evaluated as "B". In the third setting example, the warpage is evaluated as "A", and the internal stress is evaluated as "A". In the fourth setting example, the warpage is evaluated as "B", and the internal stress is evaluated as "A".

[0132] On the other hand, in the first comparative example and the second comparative example, the warpage is evaluated as "D", and the internal stress is evaluated as "A".

[0133] As shown in the drawings, compared with the first comparative example and the second comparative example, by filling the entire surface of the wafer 130 with the underfill 120 and setting H3 / H2 to be equal to or higher than 0.5, warpage can be suppressed.

[0134] <3. Third Embodiment>

[0135] In the second embodiment in which the entire surface of the wafer 130 is filled with the underfill 120, the cross-sectional shape of the underfill 120 is preferably made into a rounded shape. The manufacturing method in the third embodiment is different from the manufacturing method in the second embodiment in that the cross-sectional shape of the underfill 120 is made into a rounded shape.

[0136] Figure 17 It is a view showing an example of a plan view and a cross-sectional view of the wafer 130 when forming the underfill in the third embodiment of the present technology. In the drawings, a is an example of a plan view of the wafer 130, and b is an example of a cross-sectional view taken along the line X1-X2 in a of the drawings.

[0137] As shown in a of the drawings, in the third embodiment, the entire surface of the wafer 130 is filled with the underfill 120. In addition, as shown in b of the drawings, when viewed from the X-axis direction or the Y-axis direction, the underfill 120 near the periphery of each of the integrated circuits 110 and 111 has a cross-sectional shape that expands like a tube (in other words, a rounded shape). For example, the contact angle between the inclined surface of the underfill 120 and the substrate plane of the wafer 130 is adjusted to about 45°. As a result of the rounded shape, the effect of suppressing warpage can also be improved compared with the second embodiment.

[0138] In addition, if the height of the underfill 120 from the substrate plane of the wafer 130 is defined as H1, the height H1 is adjusted to be substantially equal to the wafer-circuit distance H0. Therefore, the underfill 120 does not adhere tightly to the side walls of the integrated circuits 110 and 111.

[0139] Note that in the third embodiment, the entire surface of the wafer 130 is filled with the underfill 120 without patterning, but patterning can be performed as in the first embodiment.

[0140] As described above, according to the third embodiment of the present technology, the cross-sectional shape of the underfill 120 is made into a rounded shape, so that the effect of suppressing warping can also be improved.

[0141] [First Variation]

[0142] In the above third embodiment, the portion along the periphery of the integrated circuit is filled with the underfill 120, but a method in which the portion along a part of the periphery is filled with the underfill 120 can also be used. The manufacturing method in the first variation of the third embodiment is different from the manufacturing method of the third embodiment in that the portion along a part of the periphery of the integrated circuit is filled with the underfill 120.

[0143] Figure 18 It is a view of an example showing a cross-sectional view of the wafer 130 when the underfill 120 is formed in the first variation of the third embodiment of the present technology. As shown in the drawing, in the first variation of the third embodiment, the portion along the peripheral portion (for example, three of the four sides) of the integrated circuit is filled with the underfill 120. For example, the right side of the leftmost integrated circuit 110 is not filled with the underfill 120, and the left side of the rightmost integrated circuit 110 is not filled with the underfill 120. Therefore, compared with the third embodiment, the internal stress can be reduced.

[0144] As described above, according to the first variation of the third embodiment of the present technology, the portion along a part of the periphery of the integrated circuit is filled with the underfill 120, so that the internal stress can be reduced compared with the third embodiment.

[0145] [Second Variation]

[0146] In the above third embodiment, the outside of the integrated circuit 110 adjacent to the periphery of the wafer 130 is also filled with the underfill 120, but a method in which the outside is not filled with the underfill 120 can also be used. The manufacturing method in the second variation of the third embodiment is different from the manufacturing method of the third embodiment in that the outside of the integrated circuit 110 is not filled with the underfill 120.

[0147] Figure 19It is a view showing an example of a cross-sectional view of a wafer 130 when forming an underfill 120 in a second modification of the third embodiment of the present technology. As shown in the drawings, in the second modification of the third embodiment, the periphery of the internal integrated circuit 111 and the inside of the integrated circuit 110 adjacent to the periphery of the wafer 130 are filled with the underfill 120. On the other hand, the outside of the integrated circuit 110 is not filled with the underfill 120. For example, the left side of the leftmost integrated circuit 110 and the right side of the rightmost integrated circuit 110 are not filled with the underfill 120. Therefore, compared with the third embodiment, the internal stress can be reduced.

[0148] Note that the integrated circuit 110 is an example of the internal integrated circuit described in the claims, and the integrated circuit 111 is an example of the external integrated circuit described in the claims.

[0149] As described above, according to the second modification of the third embodiment of the present technology, the outside of the integrated circuit 110 is not filled with the underfill 120, so that the internal stress can be reduced compared with the third embodiment.

[0150] [Third Modification]

[0151] In the above third embodiment, the contact angle is set to 45°, but the present invention is not limited to this angle. The manufacturing method in the third modification of the third embodiment is different from the manufacturing method of the third embodiment in that the contact angle is changed.

[0152] Figure 20 It is a view showing an example of a plan view and a cross-sectional view of a wafer when forming an underfill 120 in a third modification of the third embodiment of the present technology. In the drawings, a is an example of a plan view of the wafer 130, and b is an example of a cross-sectional view taken along the line X1-X2 in a of the drawings.

[0153] As shown in a of the drawings, in the third modification of the third embodiment, the portion other than the grid-like gaps is filled with the underfill 120 by patterning. In addition, for example, as shown in b of the drawings, the contact angle is adjusted to about 60°.

[0154] In the patterning process, the area to be filled with the underfill 120 is separated for each integrated circuit by a grid-like dam 131 so that each area can be uniformly filled with the underfill 120.

[0155] As described above, according to the third modification of the third embodiment of the present technology, the contact angle is set to 60°, so that patterning can be performed. Therefore, the filling can be uniformly performed with the underfill 120.

[0156] [Fourth Modification]

[0157] In the above-described third embodiment, the contact angle is set to 45°, but the present invention is not limited to this angle. The manufacturing method in the fourth modification of the third embodiment is different from the manufacturing method of the third embodiment in that the contact angle is changed.

[0158] Figure 21 It is a view showing an example of a cross-sectional view of the wafer 130 when the underfill 120 is formed in the fourth modification of the third embodiment of the present technology. As shown in the drawings, in the fourth modification of the third embodiment, the contact angle is adjusted to about 30°. Therefore, compared with the case of 45°, the effect of suppressing warping can be improved.

[0159] As described above, according to the fourth modification of the third embodiment of the present technology, the contact angle is adjusted to about 30°, so that the effect of suppressing warping can be improved.

[0160] [Fifth Modification]

[0161] In the above-described third embodiment, the underfill 120 is filled so that the underfill 120 does not tightly adhere to the side surfaces of the integrated circuits 110 and 111, but the underfill 120 can tightly adhere to a part of the side walls. The manufacturing method in the fifth modification of the third embodiment is different from the manufacturing method of the third embodiment in that the underfill 120 tightly adheres to a part of the side walls of the integrated circuit 110 or 111.

[0162] Figure 22 It is a view showing an example of a cross-sectional view of the wafer 130 when the underfill 120 is formed in the fifth modification of the third embodiment of the present technology. As shown in the drawings, in the fifth modification of the third embodiment, the contact angle is adjusted to about 30°.

[0163] In addition, it is assumed that the height H1 of the vertex of the rounded corner shape of the underfill 120 is higher than the wafer-circuit distance H0. Therefore, the underfill 120 tightly adheres to a part of the side walls of the integrated circuit 110 or 111. Therefore, compared with the case where the underfill 120 does not tightly adhere to the side walls, the effect of suppressing warping can be improved.

[0164] As described above, according to the fifth modification of the third embodiment of the present technology, the underfill 120 tightly adheres to a part of the side walls of the integrated circuit 110 or 111, so that the effect of suppressing warping can be improved.

[0165] Figure 23 It is a view comparing the corresponding characteristics between the third embodiment of the present technology and each comparative example. In the drawings, in a manner similar to the first embodiment, the warping and internal stress of the wafer 130 are evaluated at four stages A, B, C, and D.

[0166] In addition, the cross-section of the underfill 120 has a rounded corner shape with a contact angle of 45°, and the case where only the peripheral portion of the wafer 130 is filled with the underfill 120 is defined as the first comparative example. In addition, the contact angle of the underfill 120 is set to 90° (in other words, no rounded corner shape is formed), and the case where only the peripheral portion of the wafer 130 is filled with the underfill 120 is defined as the second comparative example.

[0167] In the third embodiment, the warpage is evaluated as "B", and the internal stress is evaluated as "C". In the first modification of the third embodiment, the warpage is evaluated as "C", and the internal stress is evaluated as "A". In the second modification of the third embodiment, the warpage is evaluated as "B", and the internal stress is evaluated as "B". In the third modification of the third embodiment, the warpage is evaluated as "C", and the internal stress is evaluated as "C". In the fourth modification of the third embodiment, the warpage is evaluated as "A", and the internal stress is evaluated as "C". In the fifth modification of the third embodiment, the warpage is evaluated as "A", and the internal stress is evaluated as "C".

[0168] On the other hand, in the first comparative example, the warpage is evaluated as "D", and the internal stress is evaluated as "B". In addition, in the second comparative example, the warpage is evaluated as "D", and the internal stress is evaluated as "A".

[0169] As shown in the drawings, by filling the portion along the periphery of each integrated circuit with the underfill 120 having a rounded corner shape, warpage can be suppressed as compared with the first and second comparative examples.

[0170] <4. Fourth Embodiment>

[0171] In the first embodiment, filling is performed using the underfill 120 after patterning, but if the injection position of the underfill 120 is narrow, it may be difficult to perform filling using the underfill 120. The manufacturing method in the fourth embodiment is different from the manufacturing method in the first embodiment in that it is easier to fill with the underfill 120.

[0172] Figure 24 Views are views showing an example of a plan view and a cross-sectional view of the wafer 130 during patterning in the fourth embodiment of the present technology. In the drawings, a is an example of a plan view of the wafer 130, and b is an example of a cross-sectional view taken along the line X1-X2 in a of the drawings.

[0173] In subsequent processing, when performing filling using the underfill 120 while tilting the right end of the wafer 130 lower than the left end, the underfill 120 is injected from above the left end of the wafer 130. Note that filling can be performed using the underfill 120 from the central portion of the wafer 130, and the underfill 120 can be dispersed by centrifugal force by rotating the wafer 130. In this case, the central portion is the injection position.

[0174] The black circle at the left end in the drawing indicates the injection position of the underfill 120. In the row of integrated circuits 110 and 111 arranged in the X-axis direction, filling is performed using the underfill 120 starting from the left side of the leftmost integrated circuit 110. When viewed from the Z-axis direction, each integrated circuit 110 has a rectangular shape, and the region surrounded by the dam 131 also has a rectangular shape. Patterning is performed such that the distance dX1 from the left side among the four sides of the leftmost integrated circuit 110 to the inner wall of the dam 131 becomes longer than the distances dX2 and dY from the remaining three sides to the inner wall of the dam 131. On the other hand, in integrated circuits other than the leftmost integrated circuit, patterning is performed such that the distances from the four sides to the inner wall of the dam 131 are substantially the same.

[0175] In addition, in b of the drawing, the arrow indicates the direction of injecting the underfill 120. Patterning is performed such that H3, which is the height of the left end and the right end of the dam 131, becomes higher than H4, which is the height of the dam 131 inside.

[0176] As shown in the drawing, since the distance from the side corresponding to the injection position to the inner wall of the dam 131 becomes longer, the injection position of the underfill 120 can be widened. In addition, since the height of the left end and the right end of the dam 131 increases, outflow of the underfill 120 to unnecessary parts can be prevented, and filling to the right end far from the injection position can be promoted.

[0177] Note that each modification of the first embodiment, the third embodiment, and each modification of the third embodiment can be applied to the fourth embodiment. A similar situation applies to each modification of the fourth embodiment described later.

[0178] In addition, the same material as the sealing material 150 can be used as the material of the dam. This eliminates the need for a process to remove the dam. A similar situation applies to the modification of the fourth embodiment described later.

[0179] As described above, according to the fourth embodiment of the present technology, making the distance from the side corresponding to the injection position to the inner wall of the dam 131 longer enables easy injection of the underfill 120.

[0180] [First Modification Example]

[0181] In the above-described fourth embodiment, the distance from the side surface corresponding to the injection position to the inner wall of the dam 131 is made longer, but a U-shaped recess may be formed at the injection position. The manufacturing method in the first modification of the fourth embodiment differs from the manufacturing method in the fourth embodiment in that the planar shape of the dam 131 is changed.

[0182] Figure 25 It is a view showing an example of a plan view of the dam 131 in the first modification of the fourth embodiment of the present technology.

[0183] As shown in a of the drawing, in the first modification of the fourth embodiment, when viewed from the Z-axis direction, a U-shaped recess protruding outward is provided in a partial side surface of one of the four side surfaces of the region surrounded by the dam 131. The portion surrounded by the dotted line in a of the drawing indicates the U-shaped recess. The bottom filler 120 is injected into this recess.

[0184] Note that, as shown in b of the drawing, the U-shaped recess may be formed in the corner.

[0185] As described above, according to the first modification of the fourth embodiment of the present technology, a U-shaped recess is formed in the region surrounded by the dam 131, so that the bottom filler 120 can be easily injected.

[0186] [Second Modification]

[0187] In the above-described fourth embodiment, the distance from the side surface corresponding to the injection position to the inner wall of the dam 131 is made longer, but a step may be provided in a part of the dam 131. The manufacturing method in the second modification of the fourth embodiment differs from the manufacturing method in the fourth embodiment in that a step is provided in the dam 131.

[0188] Figure 26 It is a view showing an example of the wafer 130 and the dam 131 in the second modification of the fourth embodiment of the present technology. In the drawing, a shows a cross-sectional view of the left end of the wafer 130. b and c in the drawing are perspective views of the left end of the dam 131.

[0189] As shown in a of the drawing, in the second modification of the fourth embodiment, a step is formed near the left end of the dam 131. For example, the height of the region from the left end coordinate X3 to the inner coordinate X4 is H3, and the height of the region from the coordinate X4 to the inner coordinate X5 is h3 which is lower than H3. Filling is performed with the bottom filler 120 starting from this step.

[0190] As shown in b of the drawing, a predetermined number of slits may be formed in the step portion along the direction allowing the bottom filler 120 to penetrate.

[0191] In addition, as shown in c of the drawings, a U-shaped recess when viewed from the Z-axis direction can be formed in the dam 131, and a step can be provided in a part of the recess.

[0192] Note that in b and c of the drawings, slits are formed in the dam 131, but a shape without slits can be used.

[0193] As described above, according to the second modification of the fourth embodiment of the present technology, steps are provided in a part of the dam 131 so that the filling of the underlying filler 120 can be promoted.

[0194] [Third Modification]

[0195] In the above fourth embodiment, the distance from the side surface corresponding to the injection position to the inner wall of the dam 131 is made longer, but an inclined surface can be formed in a part of the dam 131. The manufacturing method in the third modification of the fourth embodiment is different from the manufacturing method in the fourth embodiment in that an inclined surface is formed in the dam 131.

[0196] Figure 27 It is a view showing an example of the wafer 130 and the dam 131 in the third modification of the fourth embodiment of the present technology. In the drawings, a shows a cross-sectional view of the left end of the wafer 130. b and c in the drawings are perspective views of the left end of the dam 131.

[0197] As shown in a of the drawings, in the third modification of the fourth embodiment, an inclined surface is formed near the left end of the dam 131. For example, the height of the region from the coordinate X3 at the left end to the inner coordinate X4 is H3, and the height at the inner coordinate X5 is h3 which is lower than H3. The height of the region from the coordinate X3 to the coordinate X4 gradually changes to form an inclined surface. This inclined surface is filled with the underlying filler 120.

[0198] As shown in b of the drawings, a predetermined number of slits can be formed in the inclined surface portion along the direction allowing the underlying filler 120 to penetrate.

[0199] In addition, as shown in c of the drawings, a U-shaped recess when viewed from the Z-axis direction can be formed in the dam 131, and an inclined surface can be provided in a part of the recess.

[0200] Note that in b and c of the drawings, slits are formed in the dam 131, but a shape without slits can be used.

[0201] As described above, according to the third modification of the fourth embodiment of the present technology, an inclined surface is provided in a part of the dam 131 so that the filling of the underlying filler 120 can be promoted.

[0202] [Fourth Modification]

[0203] In the above-described fourth embodiment, the distance from the side surface corresponding to the injection position to the inner wall of the dam 131 is made longer, but a trench can be formed in the wafer 130. The manufacturing method in the fourth modification of the fourth embodiment is different from the manufacturing method of the fourth embodiment in that a trench is formed in the wafer 130.

[0204] Figure 28 FIGS. are views of an embodiment showing a plan view and a cross-sectional view of the wafer 130 filled with the underfill 120 in the fourth modification of the fourth embodiment of the present technology.

[0205] In the drawings, a represents an area around one integrated circuit on the upper surface of the wafer 130. In this plan view, the integrated circuit is omitted. A U-shaped recess is formed in a part of the dam 131, and a trench 130-1 is formed on the upper surface of the wafer 130. The dashed line in the figure represents the contour of the trench. The line segment Y1-Y2 in a of the drawing does not pass through the trench 130-1, and the line segment Y3-Y4 passes through the trench 130-1.

[0206] In the drawings, b shows a cross-sectional view when the wafer 130 is cut along the line segment Y1-Y2 in a of the drawing. In the drawings, c shows a cross-sectional view when the wafer 130 is cut along the line segment Y3-Y4 in a of the drawing.

[0207] As shown in c of the drawings, the trench 130-1 is directly formed under the integrated circuit 111. The trench 130-1 is formed along the filling direction of the underfill 120, and a part thereof branches into a branched shape. The filling with the underfill 120 is promoted by such a trench 130-1.

[0208] Note that, as Figure 29 shown in a of, the number of branches of the trench 130-1 can be increased, or the trench 130-1 can be formed to surround the electrode 140.

[0209] In addition, as shown in b of the drawings, the second modification of the fourth embodiment can also be applied.

[0210] As described above, according to the fourth embodiment of the present technology, a trench is formed in the wafer 130 so that the filling with the underfill 120 can be promoted.

[0211] <5. Fifth Embodiment>

[0212] In the above-described first embodiment, the wafer 130 is divided into a predetermined number of semiconductor chips. A semiconductor package is obtained by mounting these semiconductor chips on a substrate. In the manufacturing method of the fifth embodiment, the semiconductor chips manufactured in the first embodiment are mounted on a substrate.

[0213] Reference will be made to Figures 30 to 33Describe the manufacturing method after cutting of the fifth embodiment.

[0214] As Figure 30 shown, the semiconductor chip 310 obtained by cutting is mounted on the substrate 320 in a fiber-up manner. In the drawing, a shows a plan view of the substrate 320, and b shows a cross-sectional view of the substrate 320 taken along the line X6-X7 in the drawing.

[0215] As shown in b of the drawing, the semiconductor chip 310 is bonded to the upper surface of the substrate 320 by solder balls 311. In addition, a predetermined number of solder balls 321 are formed on the lower surface of the substrate 320.

[0216] Next, as Figure 31 shown, a predetermined number of passive components 330 are arranged and mounted around the semiconductor chip 310. In the drawing, a shows a plan view of the substrate 320, and b shows a cross-sectional view of the substrate 320 taken along the line X6-X7 in the drawing.

[0217] Then, as Figure 32 shown, a molding resin 340 is formed around the semiconductor chip 310, and the passive components 330 are sealed by the molding resin 340. In the drawing, a shows a plan view of the substrate 320, and b shows a cross-sectional view of the substrate 320 taken along the line X6-X7 in the drawing.

[0218] Next, as Figure 33 shown, the portion between the molding resin 340 and the semiconductor chip 310 is filled with an underfill 350. Thus, a semiconductor package is manufactured. In the drawing, a shows a plan view of the substrate 320, and b shows a cross-sectional view of the substrate 320 taken along the line X6-X7 in the drawing.

[0219] As shown in b of the drawing, the underfill 350 climbs up the inner wall of the mold resin 340 and has a rounded cross-sectional shape.

[0220] Figure 34 is a flowchart showing an example of the manufacturing method in the fifth embodiment of the present technology. In the fifth embodiment, steps S901 to S908 are similar to the steps in the first embodiment.

[0221] After cutting (step S908), the semiconductor chip 310 is mounted on the substrate 320 (step S909). Then, the passive components 330 are arranged (step S910), and these components are sealed with the molding resin 340 (step S911). Subsequently, underfill 120 is used for filling (step S912). Through these steps, a semiconductor package is manufactured. Note that the underfill 120 used in step S903 is an embodiment of the first underfill recited in the claims, while the underfill 350 used in step S912 is an embodiment of the second underfill recited in the claims.

[0222] Here, a manufacturing method is assumed as a comparative example in which the passive components 330 are not sealed with the molding resin 340 and the molding resin 340 is disposed between the semiconductor chip 310 and the passive components 330.

[0223] Figure 35 is a cross-sectional view showing an embodiment of the semiconductor package in the comparative example. In the comparative example shown in the drawing, after filling with the underfill 120, it is necessary to remove the molding resin 340 with potassium hydroxide (KOH) or the like. In this case, the underfill 350 will be damaged. In addition, the man-hours increase by an amount corresponding to the process of removing the molding resin 340. Further, it is necessary to apply the molding resin 340 to a narrow area, which reduces the productivity.

[0224] On the other hand, in the case where the passive components 330 are sealed with the molding resin 340, different from the comparative example, the process of removing the molding resin 340 is unnecessary, and the man-hours can be reduced. In addition, sealing is performed by the molding resin 340, and thus, the underfill 350 does not contact the passive components 330, and the height of the rounded-corner shape of the underfill 120 can be increased to the same extent as in the comparative example. Further, it is not necessary to form the molding resin 340 in a narrow area, thereby improving the productivity.

[0225] Note that the second embodiment, the third embodiment, and the fourth embodiment, as well as the respective modified examples of the first embodiment to the fourth embodiment, can be applied to the fifth embodiment. A similar situation applies to each modified example of the fifth embodiment described later.

[0226] As described above, according to the fifth embodiment of the present technology, the passive components 330 are sealed with the molding resin 340, so that the man-hours can be reduced and the productivity can be improved.

[0227] [First Modified Example]

[0228] In the above-described fifth embodiment, the passive component 330 is sealed with the molding resin 340, but it is difficult to further reduce the man-hours. The manufacturing method in the first modification of the fifth embodiment is different from the manufacturing method of the fifth embodiment in that a substrate 320 having a cavity structure is used.

[0229] Reference will be made Figures 36 to 38 to the manufacturing method after cutting in the first modification of the fifth embodiment.

[0230] As Figure 36 shown, the semiconductor chip 310 obtained by cutting is mounted in the cavity of the substrate 320 with the surface facing upward. In the drawings, a shows a plan view of the substrate 320, and b shows a cross-sectional view of the substrate 320 taken along the line X6-X7 in the drawings.

[0231] As shown in a and b of the drawings, a cavity 322 having a concave cross-sectional shape is formed on the upper surface of the substrate 320. The semiconductor chip 310 is mounted inside the cavity 322.

[0232] Next, as Figure 37 shown, the portion between the semiconductor chip 310 and the inner wall of the cavity 322 is filled with an underfill 350. In the drawings, a shows a plan view of the substrate 320, and b shows a cross-sectional view of the substrate 320 taken along the line X6-X7 in the drawings.

[0233] Then, as Figure 38 shown, a predetermined number of passive components 330 are arranged around the cavity 322 on the upper surface of the substrate 320. In the drawings, a shows a plan view of the substrate 320, and b shows a cross-sectional view of the substrate 320 taken along the line X6-X7 in the drawings.

[0234] For example, it is possible to ensure that the width around the cavity 322 is equal to or greater than 1 millimeter (mm). Therefore, for example, passive components 330 having a 0603 size of 0.6 × 0.6 millimeters (mm) can be mounted.

[0235] As described above, according to the first modification of the fifth embodiment of the present technology, by using the substrate 320 having a cavity structure, the process of forming the molding resin 340 becomes unnecessary.

[0236] [Second Modification]

[0237] In the above-described fifth embodiment, the passive component 330 is sealed with the molding resin 340, but components that cannot be combined cannot be further mounted. The manufacturing method in the second modification of the fifth embodiment is different from the manufacturing method of the fifth embodiment in that components are combined in the substrate and components that cannot be combined in the substrate are further mounted on the surface.

[0238] will refer to Figures 39 to 43 describe the manufacturing method after cutting in the second modification of the fifth embodiment.

[0239] As Figure 39 shown, the semiconductor chip 310 obtained by cutting is mounted on the substrate 320 in a fiber-up manner. In the drawings, a shows a plan view of the substrate 320, and b shows a cross-sectional view of the substrate 320 taken along the line segment X6-X7 in the drawings.

[0240] As shown in b of the drawings, a printed component 323 (such as a capacitor or an inductor) is formed by printing and incorporated in the substrate 320.

[0241] Next, as Figure 40 shown, a predetermined number of passive components 330 are arranged around the semiconductor chip 310. In the drawings, a shows a plan view of the substrate 320, and b shows a cross-sectional view of the substrate 320 taken along the line segment X6-X7 in the drawings.

[0242] Then, as Figure 41 shown, the passive components 330 are sealed with a substrate material. In the drawings, a shows a plan view of the substrate 320, and b shows a cross-sectional view of the substrate 320 taken along the line segment X6-X7 in the drawings.

[0243] The portion from Z1 to Z2 in b of the drawings is the portion sealed with the substrate material, and this portion is called a dam. In addition, pillars 324 formed of copper (Cu) or the like are formed on the passive components 330.

[0244] Next, as Figure 42 shown, the portion between the inner wall of the dam and the semiconductor chip 310 is filled with an underfill 350. In the drawings, a shows a plan view of the substrate 320, and b shows a cross-sectional view of the substrate 320 taken along the line segment X6-X7 in the drawings.

[0245] Then, as Figure 43 shown, surface mount technology (SMT) components 360 are arranged on the passive components 330. The surface mount technology components 360 are connected to the passive components 330 via the pillars 324. In the drawings, a shows a plan view of the substrate 320, and b shows a cross-sectional view of the substrate 320 taken along the line segment X6-X7 in the drawings. Thus, a semiconductor package is manufactured.

[0246] Components that cannot be combined are preferably surface-mounted as surface-mounted technology components 360 on the upper surface of the dam. On the other hand, by combining the passive components 330 and the printed components 323, the upper surface of the dam can be effectively utilized. In addition, since the passive components 330 and the printed components 323 are combined, the surface-mounted technology components 360 can be reduced, and for example, the mounting area can be reduced by about 20%.

[0247] In addition, by combining a noise source as the passive component 330 or the printed component 323, it is easy to design for noise suppression. For example, when electromagnetic interference (EMI) occurs, a decoupling capacitor can be arranged as the printed component 323 in the substrate 320 directly below the semiconductor chip 310. Therefore, the feedback current loop length can be shortened, and EMI can be suppressed. In this case, compared with surface mounting, the inductance of the substrate 320 is reduced to about 1 / 10.

[0248] As described above, according to the second modification of the fifth embodiment of the present technology, the surface-mounted technology components 360 are surface-mounted on the upper surface of the dam, and the passive components 330 and the printed components 323 are combined so that the upper surface of the dam can be effectively utilized.

[0249] <6. Application Examples of Moving Bodies>

[0250] The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented in the form of a device mounted on any kind of moving body (such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility vehicle, an airplane, a drone, a ship, or a robot).

[0251] Figure 44 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0252] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In Figure 44 the illustrated embodiment, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are depicted as functional components of the integrated control unit 12050.

[0253] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 serves as a control device for a driving force generation device (such as an internal combustion engine, a drive motor, etc.) that generates the vehicle's driving force, a driving force transmission mechanism that transmits the driving force to the wheels, a steering mechanism that adjusts the steering angle of the vehicle, a braking device that generates the vehicle's braking force, and so on.

[0254] The body system control unit 12020 controls the operation of various devices provided on the vehicle according to various programs. For example, the body system control unit 12020 serves as a control device for a keyless entry system, a smart key system, an electric window device, or various lights such as headlights, rear lights, brake lights, turn signals, fog lights, etc. In this case, radio waves or signals from various switches sent from a mobile device as a substitute for a key can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door lock device, electric window device, lights, etc.

[0255] The outside vehicle information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the outside vehicle information detection unit 12030 is connected to the imaging unit 12031. The outside vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The outside vehicle information detection unit 12030 can perform processing to detect objects such as people, vehicles, obstacles, signs, symbols on the road surface, or processing to detect their distances based on the received image.

[0256] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of the received light. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 can be visible light, or can be invisible light such as infrared light.

[0257] The inside vehicle information detection unit 12040 detects information about the inside of the vehicle. The inside vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the state of the driver. For example, the driver state detection unit 12041 includes a camera that captures the driver. Based on the detection information input from the driver state detection unit 12041, the inside vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0258] The microcomputer 12051 can calculate the control target values of the driving force generation device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can execute cooperative control for realizing the functions of an advanced driver assistance system (ADAS), which includes functions such as anti-collision or shock absorption for the vehicle, following driving based on the following distance, maintaining the vehicle speed during driving, warning of vehicle collision, warning of deviation of the vehicle from the lane, etc.

[0259] In addition, the microcomputer 12051 can execute cooperative control for autonomous driving by controlling the driving force generation device, the steering mechanism, the braking device, etc. based on the information about the outside or inside of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, which enables the vehicle to automatically drive without relying on the driver's operation, etc.

[0260] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 according to the outside vehicle information obtained by the outside vehicle information detection unit 12030. For example, the microcomputer 12051 can execute cooperative control for preventing glare by controlling the headlamp to change from high beam to low beam according to the positions of the vehicle ahead or the oncoming vehicle detected by the outside vehicle information detection unit 12030.

[0261] The sound / image output unit 12052 sends the output signal of at least one of sound and image to an output device that can visually or auditorily notify information to the vehicle occupants or outside the vehicle. In Figure 44 the embodiment, the audio speaker 12061, the display unit 12062, and the instrument panel 12063 are shown as embodiments of the output device. For example, the display unit 12062 can include at least one of an in-vehicle display and a head-up display.

[0262] Figure 45 is a view showing an embodiment of the installation position of the imaging unit 12031.

[0263] In Figure 45 it, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0264] For example, imaging units 12101, 12102, 12103, 12104, and 12105 are disposed at positions such as the front nose, side mirrors, rear bumper, rear door, and upper portion of the windshield inside the vehicle 12100. The imaging unit 12101 disposed at the front nose inside the vehicle and the imaging unit 12105 disposed at the upper portion of the windshield mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 disposed on the side mirrors mainly obtain images on the sides of the vehicle 12100. The imaging unit 12104 disposed on the rear bumper or rear door mainly obtains images behind the vehicle 12100. The imaging unit 12105 disposed at the upper portion of the windshield inside the vehicle is mainly used to detect preceding vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0265] Note that Figure 45 An embodiment showing the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 disposed on the front nose. The imaging ranges 12112 and 12113 represent the imaging ranges of the imaging units 12102 and 12103 disposed on the side mirrors, respectively. The imaging range 12114 represents the imaging range of the imaging unit 12104 disposed on the rear bumper or rear door. For example, a bird's-eye view image of the vehicle 12100 observed from above is obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0266] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0267] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object traveling on the travel path of the vehicle 12100 in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h) as the preceding vehicle. In addition, the microcomputer 12051 can preset a following distance to maintain in front of the preceding vehicle and perform automatic braking control (including following stop control), automatic acceleration control (including following start control), etc. Therefore, it is possible to perform coordinated control for autonomous driving that enables the vehicle to automatically travel without relying on the driver's operation or the like.

[0268] For example, the microcomputer 12051 can classify three-dimensional object data regarding a three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than a set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid a collision.

[0269] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. For example, such identification of a pedestrian is performed by a process of extracting feature points in the imaging images of the imaging units 12101 to 12104 that are infrared cameras, and a process of performing pattern matching processing on a series of feature points representing the contour of the object to determine whether it is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the imaging images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 such that a square contour line for emphasis is displayed to be superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 such that an icon representing the pedestrian or the like is displayed at a desired position.

[0270] Embodiments of a vehicle control system to which the technology according to the present disclosure can be applied have been described above. For example, in the above configuration, the technology according to the present disclosure can be applied to the imaging unit 12031. Specifically, a semiconductor package manufactured using Figure 6 the manufacturing process in can be applied to the imaging unit 12031. Applying the technology according to the present disclosure to the imaging unit 12031 can suppress warping during manufacturing and improve the reliability of the system.

[0271] Note that the above embodiments represent examples for embodying the present technology, and the corresponding contents in the embodiments and the corresponding contents specifying the present invention in the claims have a corresponding relationship. Similarly, the contents specifying the present invention in the claims and the contents with the same names in the embodiments of the present technology have corresponding relationships respectively. However, the present technology is not limited to the embodiments, and various modifications can be applied to the embodiments to embody it without departing from the scope of the present technology.

[0272] Note that the effects described in this specification are only examples and are not limited, and other effects can also be achieved.

[0273] Note that the present technology may also have the following configurations.

[0274] (1) A method for manufacturing a semiconductor package, comprising:

[0275] A filling process of filling a portion along the periphery of each of a plurality of integrated circuits bonded to a wafer using a photosensitive resin as a first underfill;

[0276] An exposure process of curing the first underfill by exposure;

[0277] A sealing process of sealing the plurality of integrated circuits and the first underfill with a sealing material; and

[0278] A dicing process of dividing the wafer into a predetermined number of semiconductor chips.

[0279] (2) The method for manufacturing a semiconductor package according to (1), further comprising: a patterning process of forming a grid-shaped dam on the wafer before the filling process.

[0280] (3) The method for manufacturing a semiconductor package according to (2), wherein

[0281] in the patterning process, laser processing and surface modification are performed.

[0282] (4) The method for manufacturing a semiconductor package according to (2), wherein

[0283] the patterning process includes:

[0284] a process of forming a resist with a predetermined gap between the plurality of integrated circuits; and a process of forming a dam by plasma processing.

[0285] (5) The method for manufacturing a semiconductor package according to (2), wherein

[0286] the patterning process includes:

[0287] a process of forming a resist on the entire surface of the wafer; and

[0288] A process of removing a resist while leaving a grid-like portion by lithography.

[0289] (6) The semiconductor package manufacturing method according to any one of (1) to (5), wherein

[0290] The ratio of the thickness of the sealing material to the thickness of the integrated circuit is not less than 0.5.

[0291] (7) The semiconductor package manufacturing method according to (1), wherein

[0292] In the filling process, the first underfill is used for filling such that when viewed from a direction parallel to the substrate plane of the wafer, the first underfill has a rounded corner shape.

[0293] (8) The semiconductor package manufacturing method according to (7), wherein

[0294] The plurality of integrated circuits include external integrated circuits adjacent to the periphery of the wafer and internal integrated circuits not corresponding to the external integrated circuits, and

[0295] In the filling process, the portions along the inner side of the external integrated circuits and the periphery of the internal integrated circuits are filled with the first underfill.

[0296] (9) The semiconductor package manufacturing method according to (7), wherein

[0297] In the filling process, the portions along the partial peripheries of each of the plurality of integrated circuits are filled with the first underfill.

[0298] (10) The semiconductor package manufacturing method according to any one of (7) to (9), wherein

[0299] The contact angle of the portion where the first underfill contacts the wafer is any one of 30°, 45°, and 60°.

[0300] (11) The semiconductor package manufacturing method according to (7), wherein

[0301] Part of the first underfill contacts the sidewalls of the integrated circuit.

[0302] (12) The semiconductor package manufacturing method according to (1), further comprising: a patterning process of forming a grid-like dam on the wafer before the filling process, wherein

[0303] When viewed from a direction perpendicular to the substrate, each integrated circuit has a rectangular shape,

[0304] When viewed from a direction perpendicular to the substrate, the region surrounded by the dam has a rectangular shape, and

[0305] When viewed from a direction perpendicular to the substrate, the distance from one side of each integrated circuit to the inner wall of the dam is greater than the distances from the remaining three sides to the inner wall of the dam.

[0306] (13) The method for manufacturing a semiconductor package according to (1) further includes: a patterning step of forming a grid-shaped dam on the wafer before the filling step, wherein,

[0307] When viewed from a direction perpendicular to the substrate, an outwardly protruding U-shaped recess is formed in the region surrounded by the dam.

[0308] (14) The method for manufacturing a semiconductor package according to (1) further includes: a patterning step of forming a grid-shaped dam on the wafer before the filling step, wherein,

[0309] Part of the dam has a step.

[0310] (15) The method for manufacturing a semiconductor package according to (1) further includes: a patterning step of forming a grid-shaped dam on the wafer before the filling step, wherein,

[0311] Part of the dam has an inclined surface.

[0312] (16) The method for manufacturing a semiconductor package according to (1) further includes: a patterning step of forming a grid-shaped dam on the wafer before the filling step, wherein,

[0313] A predetermined number of slits are formed in part of the dam.

[0314] (17) The method for manufacturing a semiconductor package according to (1), wherein,

[0315] A predetermined number of grooves are formed in the wafer.

[0316] (18) The method for manufacturing a semiconductor package according to any one of (1) to (17) further includes:

[0317] A step of mounting a semiconductor chip on a substrate;

[0318] A step of arranging passive components around the semiconductor chip;

[0319] A step of sealing the passive components by molding resin; and

[0320] A step of performing filling using a second underfill.

[0321] (19) The method for manufacturing a semiconductor package according to any one of (1) to (17) further includes:

[0322] A step of mounting a semiconductor chip in a cavity provided in a substrate;

[0323] The step of filling the cavity with a second underfill; and

[0324] The step of arranging passive components around the cavity.

[0325] (20) The semiconductor package manufacturing method according to any one of (1) to (17) further includes:

[0326] The step of mounting a semiconductor chip on a substrate;

[0327] The step of arranging passive components around the semiconductor chip;

[0328] The step of sealing the passive components with a substrate material;

[0329] The step of performing filling with a second underfill; and

[0330] The step of disposing surface mount technology components on the substrate material.

[0331] List of reference signs

[0332] 110, 111 Integrated circuit

[0333] 120 Underfill

[0334] 130 Wafer

[0335] 130-1 Trench

[0336] 131, 210, 221 Dam

[0337] 140 Electrode

[0338] 150 Sealing material

[0339] 200, 220 Resist

[0340] 310 Semiconductor chip

[0341] 311, 321 Solder ball

[0342] 320 Substrate

[0343] 322 Cavity

[0344] 323 Printed component

[0345] 324 Post

[0346] 330 Passive component

[0347] 340 Molding resin

[0348] 350 Underfill

[0349] 360 Surface mount technology component

[0350] 12031 Imaging unit.

Claims

1. A method for manufacturing a semiconductor package, comprising: A filling process of filling a portion along the periphery of each of a plurality of integrated circuits bonded to a wafer using a photosensitive resin as a first underfill; An exposure process of curing the first underfill by exposure; A sealing process of sealing the plurality of integrated circuits and the first underfill with a sealing material; And A dicing process of dividing the wafer into a predetermined number of semiconductor chips.

2. The semiconductor package manufacturing method according to claim 1 further includes: A patterning process of forming a grid-shaped dam on the wafer before the filling process.

3. The method for manufacturing a semiconductor package according to claim 2, wherein, Laser processing and surface modification are performed in the patterning process.

4. The method for manufacturing a semiconductor package according to claim 2, wherein, The patterning process includes: A process of forming a resist with a predetermined gap between the plurality of integrated circuits; and A process of forming the dam by plasma processing.

5. The method for manufacturing a semiconductor package according to claim 2, wherein, The patterning process includes: A process of forming a resist on the entire surface of the wafer; and A process of removing the resist while leaving a grid-shaped portion by photolithography.

6. The method for manufacturing a semiconductor package according to claim 1, wherein, The ratio of the thickness of the sealing material to the thickness of the integrated circuit is not less than 0.

5.

7. The method for manufacturing a semiconductor package according to claim 1, wherein, In the filling process, filling is performed using the first underfill such that when viewed from a direction parallel to the substrate plane of the wafer, the first underfill has a rounded corner shape.

8. The method for manufacturing a semiconductor package according to claim 7, wherein, The plurality of integrated circuits include external integrated circuits adjacent to the periphery of the wafer and internal integrated circuits not corresponding to the external integrated circuits, and In the filling process, the portion along the inner side of the external integrated circuits and the periphery of the internal integrated circuits is filled with the first underfill.

9. The method for manufacturing a semiconductor package according to claim 7, wherein, In the filling process, the portion along a partial periphery of each of the plurality of integrated circuits is filled with the first underfill.

10. The method for manufacturing a semiconductor package according to claim 7, wherein, The contact angle of the portion of the first underfill in contact with the wafer is any one of 30°, 45°, and 60°.

11. The method for manufacturing a semiconductor package according to claim 7, wherein, A part of the first underfill is in contact with the sidewall of the integrated circuit.

12. The semiconductor package manufacturing method according to claim 1 further includes: A patterning process of forming a grid-shaped dam on the wafer before the filling process, wherein, When viewed from a direction perpendicular to the substrate, each integrated circuit has a rectangular shape, When viewed from a direction perpendicular to the substrate, the region surrounded by the dam has a rectangular shape, and When viewed from a direction perpendicular to the substrate, the distance from one side of each integrated circuit to the inner wall of the dam is greater than the distances from the remaining three sides to the inner wall of the dam.

13. The semiconductor package manufacturing method according to claim 1 further includes: A dam patterning process for forming a grid-shaped dam on the wafer before the filling process, wherein, When viewed from a direction perpendicular to the substrate, an outwardly protruding U-shaped recess is formed in the region surrounded by the dam.

14. The semiconductor package manufacturing method according to claim 1 further includes: A dam patterning process for forming a grid-shaped dam on the wafer before the filling process, wherein, Part of the dam has steps.

15. The semiconductor package manufacturing method according to claim 1 further includes: A dam patterning process for forming a grid-shaped dam on the wafer before the filling process, wherein, Part of the dam has an inclined surface.

16. The semiconductor package manufacturing method according to claim 1 further includes: A dam patterning process for forming a grid-shaped dam on the wafer before the filling process, wherein, A predetermined number of slits are formed in part of the dam.

17. The method for manufacturing a semiconductor package according to claim 1, wherein, A predetermined number of trenches are formed in the wafer.

18. The method for manufacturing a semiconductor package according to claim 1, further comprising: A process of mounting the semiconductor chip on a substrate; A process of arranging passive components around the semiconductor chip; A process of sealing the passive components with a molding resin; and A process of performing filling with a second underfill.

19. The method for manufacturing a semiconductor package according to claim 1, further comprising: A process of mounting the semiconductor chip in a cavity provided in a substrate; A process of filling the cavity with a second underfill; And A process of arranging passive components around the cavity.

20. The method for manufacturing a semiconductor package according to claim 1, further comprising: A process of mounting the semiconductor chip on a substrate; A process of arranging passive components around the semiconductor chip; A process of sealing the passive components with a substrate material; A process of performing filling with a second underfill; and A process of setting surface mount technology components on the substrate material.

Images