Modeling method of semiconductor device
By subdividing the device capacitance into multiple components, building a capacitance relationship and conducting S-parameter testing, the problems of long modeling cycles and process dependence in the existing technology are solved, and efficient modeling and accurate design are achieved.
Patent Information
- Application Number
- CN202311837359.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-28
- Publication Date
- 2025-07-08
AI Technical Summary
When modeling semiconductor devices, the prior art requires a lot of testing and parameter extraction, resulting in a long modeling cycle and relying on process accuracy, making it difficult to effectively eliminate process fluctuations and affect the accuracy of the model.
The device capacitance is subdivided into multiple components, a capacitance relationship is constructed, and the S parameter test is performed under the set bias conditions. By constructing the full rank equation, the device capacitance changes with the gate finger and gate width are obtained, reducing the number of tests.
Shorten the modeling cycle, improve modeling efficiency, be able to identify process or test errors, provide targeted improvements in design, and improve model accuracy.
Smart Images
Figure CN120278100A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic technology, and in particular to a method for modeling a semiconductor device. Background Art
[0002] In recent years, due to the advantages of high electron mobility (HEMT) devices based on the third-generation semiconductor gallium nitride (GaN), such as high bandgap width, high output power, and high-frequency characteristics, they are widely used in amplifier circuits and have been widely applied in military communication, civilian commercial communication, and other fields.
[0003] The device model is the key to establishing a connection between the foundry and the design company. Circuit designers rely heavily on the accuracy of the device model. It can be said that the accuracy of the device model is the key to the success or failure of tape-out. From the perspective of circuit design, based on the bandwidth matching theory, the amplifier circuit topology design is generally divided into reactive and distributed designs. The former can obtain better output power and efficiency, but is suitable for narrowband design; while the latter can obtain a wider bandwidth, but has a lower power gain. Whether it is reactive or distributed design, it is necessary to accurately predict the input impedance and output impedance of the semiconductor device in the large-signal state. Among them, the imaginary part of the input impedance is related to the input capacitance, and the imaginary part of the output impedance is related to the output capacitance. Since different biases affect the depletion layer width and thus cause changes in the sizes of the input capacitance and output capacitance (collectively referred to as device capacitance), a large number of tests and parameter extraction work are required. This not only lengthens the modeling cycle but also depends on the process accuracy and parameter extraction accuracy of each single cell, otherwise it will affect the final model scaling result. Therefore, it is extremely meaningful to study and establish a modeling method that can reduce the test modeling cycle, eliminate process fluctuations, and improve parameter extraction accuracy. Summary of the Invention
[0004] The present invention provides a method for modeling a semiconductor device to improve the modeling efficiency and shorten the modeling cycle.
[0005] The method for modeling the semiconductor device includes:
[0006] Constructing a capacitance relational expression regarding multiple components affecting device capacitance, the gate fingers, and the gate width;
[0007] Under set bias conditions, testing the S-parameters of the device to be tested and extracting the value of the device capacitance;
[0008] For different devices to be tested, repeating the step of testing the S-parameters of the device to be tested and extracting the value of the device capacitance;
[0009] Substitute the values of the device capacitance, the number of gate fingers, and the gate width corresponding to different devices to be tested into the capacitance relationship formula to obtain a full-rank equation constructed by at least two capacitance relationship formulas, and calculate the general solution of the device capacitance varying with different gate fingers and gate widths.
[0010] Optionally, the semiconductor device includes a source electrode, a drain electrode, a substrate, as well as a drain bus and / or a field plate; the device capacitance is an output capacitance; the components affecting the output capacitance include: a first interelectrode capacitance, a second interelectrode capacitance, a field plate capacitance, and a substrate capacitance;
[0011] Among them, the first interelectrode capacitance is the capacitance between the drain bus and the source electrode, the second interelectrode capacitance is the capacitance formed by the two-dimensional electron gas between the source electrode and the drain electrode; the field plate capacitance is the capacitance between the field plate and the drain electrode; the substrate capacitance is the capacitance between the substrate and the drain electrode.
[0012] Optionally, the semiconductor device further includes a back gold; the substrate capacitance includes: a first substrate capacitance and a second substrate capacitance;
[0013] Among them, the first substrate capacitance is the capacitance between the drain bus and the back gold; the second substrate capacitance is the capacitance between the back gold and the drain electrode.
[0014] Optionally, the first substrate capacitance includes: a first A substrate capacitance and a first B substrate capacitance;
[0015] The first A substrate capacitance is the capacitance between the first part of the drain bus and the back gold, and the first part is the part of the drain bus in direct contact with the drain electrode; the first B substrate capacitance is the capacitance between the second part of the drain bus and the back gold, and the second part is the other part of the drain bus except the first part.
[0016] Optionally, the semiconductor device further includes a connection bridge; the multiple components affecting the output capacitance further include: a connection bridge capacitance; the connection bridge capacitance is the capacitance formed by the connection bridge and the drain electrode.
[0017] Optionally, in the step of repeatedly performing the test on the S parameters of the device to be tested for different devices to be tested, at least three different devices to be tested are tested;
[0018] In the step of obtaining a full-rank equation constructed by at least two capacitance relationship formulas, a 3-order full-rank equation is constructed.
[0019] Optionally, the semiconductor device includes a gate electrode and a source electrode; the device capacitance is an input capacitance; the multiple components affecting the input capacitance include: an intrinsic region capacitance and a parasitic capacitance;
[0020] Wherein, the intrinsic region capacitance is the capacitance formed by the gate and the two-dimensional electron gas under the source.
[0021] Optionally, the semiconductor device further includes a field plate and a gate bus; the parasitic capacitance includes: a first parasitic capacitance and a second parasitic capacitance;
[0022] Wherein, the first parasitic capacitance is the capacitance between the gate and the field plate; the second parasitic capacitance is the capacitance between the gate bus and the source.
[0023] Optionally, in the step of repeatedly performing the test on the S parameters of the device under test for different devices under test, at least two different devices under test are tested;
[0024] In the step of obtaining the full-rank equation constructed by at least two of the capacitance relationships, a second-order full-rank equation is constructed.
[0025] Optionally, the proportion of the plurality of components in the capacitance relationship is determined by the device structure.
[0026] In the embodiment of the present invention, the device capacitance is subdivided into multiple components, and capacitance relationships regarding multiple components affecting the device capacitance, gate fingers, and gate widths are constructed; then, under set bias conditions, the S parameters of different devices under test are tested, and the values of the extracted device capacitance are substituted into the capacitance relationships; at least two obtained capacitance relationships are constructed into a full-rank equation to obtain the general solution of the device capacitance varying with different gate fingers and gate widths. In this way, due to the use of region-based scaling, only the data of at least two specific groups of devices need to be tested to obtain the entire scaling formula, resulting in less testing and shortening the modeling cycle. Therefore, compared with the prior art that requires a large number of tests during modeling or device testing, the embodiment of the present invention only needs to test a smaller number of devices to complete the modeling. After the modeling is completed, if the device capacitance of a certain device is desired, only the gate fingers and gate widths of the device need to be substituted into the general solution, and there is no need to test the device again.
[0027] In addition, through region-based division, the embodiment of the present invention can obtain the data of each component varying with gate fingers and gate widths. When there is a deviation between the production finished product and the modeling data, it can be determined that there are errors in the process or testing, thereby providing a reference for the process and testing. Moreover, during device design, the device capacitance can be improved by improving each component, and the design improvement is more targeted, which is of certain significance for device design improvement.
[0028] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0030] Figure 1 Schematic flow chart of a method for modeling a semiconductor device provided by an embodiment of the present invention;
[0031] Figure 2 Schematic three-dimensional structure diagram of a semiconductor device model provided by an embodiment of the present invention;
[0032] Figure 3 Schematic plan view structure diagram of a semiconductor device model provided by an embodiment of the present invention;
[0033] Figure 4 Schematic diagram of the film layer structure of a semiconductor device provided by an embodiment of the present invention;
[0034] Figure 5 Schematic enlarged structure diagram of a semiconductor device provided by an embodiment of the present invention;
[0035] Figure 6 Schematic top view structure diagram of another semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0036] In order to enable those skilled in the art to better understand the solutions of the present invention, the following clearly and completely describes the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
[0037] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of the present invention are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.
[0038] Figure 1 Schematic flow diagram of a method for modeling a semiconductor device provided by an embodiment of the present invention. Refer to Figure 1 , the modeling method includes the following steps:
[0039] S110. Construct a capacitance relationship formula regarding multiple components, gate fingers and gate widths that affect the device capacitance.
[0040] To clearly illustrate the embodiments of the present invention, the semiconductor device model will be described first. Figure 2 Schematic three-dimensional structure diagram of a semiconductor device model provided by an embodiment of the present invention, Figure 3 Schematic plan view of a semiconductor device model provided by an embodiment of the present invention. Refer to Figure 2 and Figure 3 , the device model includes a gate G, a drain D and a source S, includes a gate resistance Rg, a gate capacitance Cpg and a gate inductance Lg, includes a drain resistance Rd, a drain capacitance Cpd and a drain inductance Ld, includes a source resistance Rs and a source inductance Ls, includes a capacitance Cpgd characterizing the inter-pole coupling characteristic, includes capacitances Cgs and Cgd under the gate G, includes a drain-source capacitance Cds, a channel resistance Ri, a drain-source current Ids and an output conductance Gds.
[0041] Among them, the device capacitance includes an input capacitance and an output capacitance. The input impedance is composed of an input resistance Rg (real part) and an input capacitance (imaginary part), and the output impedance is composed of an output resistance (real part) and an output capacitance (imaginary part). Among them, the input resistance is the gate resistance Rg, so the gate resistance Rg can also be called the input resistance Rg. The input capacitance is related to the capacitance Cgs under the gate G, so the capacitance Cgs under the gate G can also be called the input capacitance Cgs; the output resistance is the drain resistance Rd, so the drain resistance Rd can also be called the output resistance Rd. The output capacitance is related to the drain-source capacitance Cds, so the drain-source capacitance Cds can also be called the output capacitance Cds.
[0042] For the input resistance Rg and the output resistance Rd, the "Cold FET" method can be directly used to obtain them. For the input capacitance Cgs and the output capacitance Cds, different bias conditions affect the depletion layer width, thereby causing changes in the magnitudes of the input capacitance Cgs and the output capacitance Cds. The inventor analyzed the components of the input capacitance Cgs and the output capacitance Cds of the semiconductor device, and performed physically meaningful scaling on multiple components, and was able to obtain the relationship formula (i.e., the scaling formula) of the device capacitance (including the input capacitance Cgs and the output capacitance Cds).
[0043] S120. Under the set bias conditions, test the S-parameters of the device to be tested, and extract the device capacitance.
[0044] Among them, the device to be tested refers to the device used for semiconductor device modeling. The device to be tested can be any semiconductor device as long as its S-parameters can be tested. The S-parameters of the present invention are professional terms in the field of radio frequency and microwave. Since different bias conditions affect the depletion layer width, thereby causing changes in the magnitudes of the device capacitance (including the input capacitance Cgs and the output capacitance Cds), it is necessary to determine the set bias conditions. The set bias conditions are fixed bias conditions, and during the process of calculating the general solution of the device capacitance varying with different gate fingers and gate widths once, the fixed bias conditions remain unchanged. Optionally, test the S-parameters of the device to be tested, and extract the device capacitance (including the input capacitance Cgs and the output capacitance Cds) based on the "Cold FET" method and the "Cold Pinch-off" method. It can be understood that if the device to be tested only includes a single cell, the extracted device capacitance is the capacitance of the single cell; if the device to be tested includes multiple single cells, the extracted device capacitance is the capacitance of the multiple single cells as a whole. In practical applications, a single-cell device can be selected as the device to be tested to facilitate reducing the calculation difficulty.
[0045] S130. For different devices to be tested, repeat the steps of testing the S-parameters of the device to be tested and extracting the device capacitance.
[0046] Among them, the steps of testing the S-parameters of the device to be tested and extracting the device capacitance are S120. The set bias conditions of different devices to be tested are the same, while the gate fingers and / or gate widths are different. The general solution of the device capacitance varying with different gate fingers and gate widths obtained thereby is the general solution under the set bias conditions. In practical applications, the bias conditions can be set according to customer requirements to obtain the general solution of the device capacitance varying with different gate fingers and gate widths under customer requirements.
[0047] The number of devices to be tested is determined by the number of multiple components that affect the device capacitance. The more the number of components, the more unknowns in the relational expression of the device capacitance, and the more devices to be tested are required; the fewer the number of components, the fewer unknowns in the relational expression of the device capacitance, and the fewer devices to be tested are required. The coefficients of the respective unknowns are composed of the gate fingers and / or the gate width.
[0048] S140. Substitute the values of the device capacitance, the number of gate fingers, and the value of the gate width corresponding to different devices to be tested into the capacitance relational expression, and construct a full-rank equation from at least two obtained capacitance relational expressions, and calculate the general solution of the device capacitance varying with different gate fingers and gate widths.
[0049] Among them, substitute the value of the device capacitance, the number of gate fingers, and the value of the gate width corresponding to one device to be tested into the capacitance relational expression to obtain one equation in the full-rank equation. In this equation, multiple components that affect the device capacitance are unknowns; repeat this process to obtain all the equations in the full-rank equation. The order of this full-rank equation is determined by the number of unknowns in the relational expression of the device capacitance. Solving this full-rank equation can obtain the general solution of the device capacitance varying with different gate widths and gate fingers. In order to obtain a full-rank equation, the coefficients in each capacitance relational expression should not be enlarged in equal proportion. Therefore, when selecting the devices to be tested, the situation where the coefficients in each capacitance relational expression are enlarged in equal proportion should be avoided, which is beneficial to reducing the number of devices to be tested in the process of constructing the full-rank equation.
[0050] In the embodiment of the present invention, the device capacitance is subdivided into multiple components, and a capacitance relational expression regarding multiple components, gate fingers, and gate widths that affect the device capacitance is constructed; then, under the set bias conditions, S-parameter tests are performed on different devices to be tested, and the extracted values of the device capacitance are substituted into the capacitance relational expression; at least two obtained capacitance relational expressions are constructed into a full-rank equation to obtain the general solution of the device capacitance varying with different gate fingers and gate widths. In this way, due to the use of region scaling, only the data of at least two specific groups of devices need to be tested to obtain the entire scaling formula, resulting in a small test volume and shortening the modeling cycle. Therefore, compared with the prior art that requires a large number of tests during modeling or during device testing, the embodiment of the present invention only needs to test a small number of devices to complete the modeling. After the modeling is completed, if you want to obtain the device capacitance of a certain device, just substitute the gate fingers and gate width of this device into this general solution, and there is no need to test this device again.
[0051] In addition, through regional division, the embodiments of the present invention can obtain data of each component that varies with the gate fingers and gate widths. When there is a deviation between the production finished product and the modeling data, it can be determined that there are errors in the process or testing, thereby providing a reference for the process and testing. Moreover, when designing a device, the device capacitance can be improved by improving each component, and the design improvement is more targeted, thus having a certain significance for improving the device design.
[0052] To clearly illustrate the multiple components that affect the device capacitance provided by the embodiments of the present invention, the structure of the semiconductor device will be further described below.
[0053] Figure 4 It is a schematic diagram of the film layer structure of a semiconductor device provided by an embodiment of the present invention. Refer to Figure 4 , in one embodiment, optionally, the semiconductor device includes a back gold 10, a substrate 20, a channel layer 30, a barrier layer 50, and a cap layer 60 that are stacked. A two-dimensional electron gas 40 is formed between the channel layer 30 and the barrier layer 50. Optionally, the back gold 10 is electrically connected to the source electrode S.
[0054] Optionally, the semiconductor device may further include a nucleation layer, a buffer layer, or other film layers, which are not limited in the present invention.
[0055] The semiconductor device may include an active region and a passive region. The active region can be understood as the region where there is a two-dimensional electron gas, electrons, or holes below it, and its working state and characteristics are affected by the external circuit, which is the active working region of the semiconductor device. The passive region participates in the operation of the semiconductor device, but its working state is not affected by the external circuit. For example, an extraction structure such as an electrode bus of the active region can be provided in the passive region, and the passive region can be arranged around the active region.
[0056] Figure 5 It is a schematic diagram of an enlarged structure of a semiconductor device provided by an embodiment of the present invention. Refer to Figure 5 , in one embodiment, optionally, the semiconductor device further includes a field plate 70. In this embodiment, the source field plate 70 is taken as an example, and the field plate 70 is electrically connected to the source electrode S.
[0057] Connection bridge Figure 6 It is a schematic diagram of a top view structure of another semiconductor device provided by an embodiment of the present invention. Refer to Figure 6 , in one embodiment, optionally, the semiconductor device is a three-gate finger device, multiple drain electrodes D are connected to the drain bus 80, multiple active region gates are connected to the passive region gate bus 90, and multiple source electrodes S are connected to the source bus ( Figure 6(not shown in the figure). The drain bus 80 includes a first portion 81 and a second portion 82. The first portion 81 is the portion of the drain bus 80 that is in direct contact with the drain D, and the second portion 82 is the other portion of the drain bus 80 except the first portion 81.
[0058] See Figures 4 - 6 , based on the above embodiments, optionally, the device capacitance is the output capacitance; the components affecting the output capacitance include the inter-electrode capacitance; wherein, the inter-electrode capacitance includes a first inter-electrode capacitance Cds_1 and a second inter-electrode capacitance Cds_2; wherein, the first inter-electrode capacitance Cds_1 is the capacitance between the drain bus 80 and the source S, and the second inter-electrode capacitance Cds_2 is the capacitance formed by the two-dimensional electron gas 40 between the source S and the drain D.
[0059] Continue to refer to Figures 4 - 6 , based on the above embodiments, optionally, the device capacitance is the output capacitance; the multiple components affecting the output capacitance include the substrate capacitance; the substrate capacitance is the capacitance between the substrate and the drain. Optionally, the substrate capacitance includes: a first substrate capacitance Cds_sub1 and a second substrate capacitance Cds_sub2; wherein, the first substrate capacitance Cds_sub1 is the capacitance between the drain bus 80 and the back metal 10; the second substrate capacitance Cds_sub2 is the capacitance between the back metal and the active region drain D.
[0060] Continue to refer to Figures 4 - 6 , based on the above embodiments, optionally, the first substrate capacitance Cds_sub1 includes: a first methyl substrate capacitance Cds_sub3 and a first ethyl substrate capacitance Cds_sub4; wherein, the first methyl substrate capacitance Cds_sub3 is the capacitance between the first portion 81 of the drain bus 80 and the back metal 10; the first ethyl substrate capacitance Cds_sub4 is the capacitance between the second portion 82 of the drain bus 80 and the back metal 10.
[0061] Continue to refer to Figures 4 - 6 , based on the above embodiments, optionally, when the semiconductor device further includes a field plate 70; the multiple components affecting the output capacitance include the field plate capacitance Cds_fp; wherein, the field plate capacitance Cds_fp is the capacitance between the field plate 70 and the drain D.
[0062] Continue to refer to Figures 4 - 6 , based on the above embodiments, optionally, optionally, a connection bridge structure 71 may be formed above the drain D in the active region, which may be a connection bridge structure between the sources or a connection bridge structure between the gates, and is not limited in the present invention as long as it is a connection bridge structure formed across the drain D. As Figure 5As shown, the present invention takes the example of forming a connection bridge structure 71 across the drain D between two source electrodes S. Then, the multiple components affecting the output capacitance further include the connection bridge capacitance Cds_br; the connection bridge capacitance Cds_br is the capacitance formed between the connection bridge and the drain electrode of the active region. The connection bridge capacitance Cds_br can be an air connection bridge capacitance or a dielectric connection bridge capacitance, which is not limited herein.
[0063] Among them, the proportions of the first inter-electrode capacitance Cds_1, the first substrate capacitance Cds_sub3 of type A, the first substrate capacitance Cds_sub4 of type B, the second inter-electrode capacitance Cds_2, the field plate capacitance Cds_fp, and the second substrate capacitance Cds_sub2 in the capacitance relation are determined by the device structure. Specifically, from the perspective of the device structure, the first inter-electrode capacitance Cds_1, the first substrate capacitance Cds_sub3 of type A, and the first substrate capacitance Cds_sub4 of type B are basically of a fixed area, do not change with the gate width, and only change with the gate index. Since there is one first inter-electrode capacitance Cds_1 and one first substrate capacitance Cds_sub3 between two gate fingers, and so on, the proportions of the first inter-electrode capacitance Cds_1 and the first substrate capacitance Cds_sub3 are both multiples of Fnum / 2, and their unit is defined as fF; the second inter-electrode capacitance Cds_2, the field plate capacitance Cds_fp, and the second substrate capacitance Cds_sub2 change with the total gate width. Among them, the second inter-electrode capacitance Cds_2 and the second substrate capacitance Cds_sub2 change with the gate finger (Fnum) and the gate width (Fwidth) as multiples of Fnum / 2*Fwidth, while the field plate capacitance Cds_fp is a multiple of Fnum*Fwidth, and its unit is defined as fF / mm, and its physical meaning is the capacitance per unit gate width; for the connection bridge capacitance Cds_br, in a unit cell containing one gate finger, along the extension direction of the gate finger, the number of connection bridges is N, then when the number of gate fingers is Fnum, the number of connection bridges is N*Fnum, and then the proportion of the capacitance Cds_br is N*Fnum.
[0064] From this, the relationship between the output capacitance Cds and the gate finger and the gate width can be obtained as follows:
[0065] Cds = Cds_1*Fnum / 2 + Cds_2*Fnum*Fwidth + Cds_fp*Fnum*Fwidth + Cds_br*Fnum + Cds_sub2*Fnum / 2*Fwidth + Cds_sub3*Fnum / 2 + Cds_sub4*(Fnum - 2) / 2
[0066] =(Cds_2 + Cds_fp + 1 / 2 * Cds_sub2) * Fnum * Fwidth + (Cds_1 + Cds_sub3 + Cds_sub4 + N * Fnum * Cds_br) * 1 / 2 * Fnum - Cds_sub4
[0067] Wherein, Fnum is the number of finger electrodes, and Fwidth is the value of the finger electrode width.
[0068] In the embodiment of the present invention, the proportion of each component affecting the output capacitance Cds is accurately proposed through the method of region division, making the modeling method more accurate.
[0069] It should be noted that for different types of semiconductor devices, due to their different structures, there may be no one or more of the above capacitors, but the above output capacitance relationship is general. For example, for a device without a connecting bridge, in the modeling process, the connecting bridge capacitance Cds_br in the output capacitance relationship is deleted. Also, with different numbers of finger electrodes, the proportion of each component affecting the output capacitance Cds is somewhat different. Specifically, as Figure 5 shown, in the unit cell corresponding to a single finger electrode, along the extension direction of the finger electrode, the number of connecting bridges should be recorded as 2, and in a device with 2 finger electrodes, along the extension direction of the finger electrode, the number of connecting bridges should be recorded as 4. That is to say, in the whole device, the number of connecting bridges satisfies N * Fnum.
[0070] Based on the above embodiments, optionally, if a full-rank equation of the output capacitance Cds is constructed, in S120 and S130, at least three different devices to be tested are tested; in S140, a 3rd-order full-rank equation is constructed. This is because the number of components affecting the output capacitance Cds is 6, and at least a 3rd-order full-rank equation is required for solution.
[0071] Continue to refer to Figures 4 - 6 , based on the above embodiments, optionally, the device capacitance is the input capacitance Cgs; the multiple components affecting the input capacitance Cgs include the intrinsic region capacitance Cgs_eff. The intrinsic region capacitance Cgs_eff is the capacitance formed by the gate and the two-dimensional electron gas under the source S in the active region.
[0072] Continue to refer to Figures 4 - 6, based on the above embodiments, optionally, the device capacitance is the input capacitance Cgs; the multiple components affecting the input capacitance Cgs include parasitic capacitances. Optionally, the parasitic capacitances include: the first parasitic capacitance Cgs_fp and the second parasitic capacitance Cgs_bus; wherein, the first parasitic capacitance Cgs_fp is the capacitance between the gate G and the field plate 70 (with a dielectric layer in between); the second parasitic capacitance Cgs_bus is the capacitance between the gate bus 90 and the source S.
[0073] Based on the above embodiments, optionally, the proportions of the intrinsic region capacitance Cgs_eff, the first parasitic capacitance Cgs_fp, the second parasitic capacitance Cgs_bus, etc. in the capacitance relation formula are determined by the device structure. Specifically, the intrinsic region capacitance Cgs_eff and the first parasitic capacitance Cgs_fp should be the product of the number of finger gates and the gate width based on the structure, that is, a multiple of Fnum*Fwidth, and its unit is defined as fF / mm, and its physical meaning is the capacitance per unit gate width; while the second parasitic capacitance Cgs_bus should be a multiple of the number of finger gates based on the structure, that is, Fnum, and its unit is defined as fF.
[0074] Thus, the relationship formula between the input capacitance Cgs and the number of finger gates and the gate width can be obtained as follows:
[0075] Cgs = Cgs_eff * Fnum * Fwidth + Cgs_fp * Fnum * Fwidth + Cgs_bus * Fnum
[0076] = (Cgs_eff + Cgs_fp) * Fnum * Fwidth + Cgs_bus * Fnum
[0077] Wherein, Fnum is the number of finger gates, and Fwidth is the value of the gate width.
[0078] The embodiments of the present invention accurately propose the proportion of each component affecting the input capacitance Cgs through the method of region division, making the modeling method more accurate.
[0079] Based on the above embodiments, optionally, if a full-rank equation of the input capacitance Cgs is constructed, in S120 and S130, at least two different devices to be tested are tested; in S140, a second-order full-rank equation is constructed. This is because the number of components affecting the input capacitance Cgs is 3, and at least a second-order full-rank equation is required for solution.
[0080] Based on the above embodiments, optionally, the input capacitance Cgs and the output capacitance Cds can be tested and solved simultaneously. Specifically, in S130, the S-parameters of the device to be tested are measured, and the input capacitance Cgs and the output capacitance Cds are extracted simultaneously based on the "Cold FET" method and the "Cold Pinch-off" method. Such a setting is beneficial to simplifying the modeling steps.
[0081] In summary, the embodiments of the present invention divide the device capacitance into multiple components, and construct capacitance relational expressions regarding multiple components, gate fingers, and gate widths that affect the device capacitance; then, under fixed bias conditions, the S-parameters of different devices to be tested are measured, and the input capacitance value and the output capacitance value are proposed based on the "Cold FET" method and the "Cold Pinch-off" method, and the measured values, corresponding gate widths, and gate fingers are substituted into the capacitance relational expressions; at least two obtained capacitance relational expressions are used to construct a full-rank equation, and the general solution of the device capacitance varying with different gate fingers and gate widths is obtained. Since the use of regional scaling only requires testing the data of at least two specific groups of devices to obtain the entire scaling formula, the test volume is small and the modeling cycle is shortened. In addition, the embodiments of the present invention can obtain the data of each component varying with the gate fingers and gate widths by region division. When there is a deviation between the production finished product and the modeling data, it can be determined that there are errors in the process or testing, thereby providing a reference for the process and testing.
[0082] Moreover, when designing a device, the device capacitance can be improved by improving each component, and the design improvement is more targeted, which is of certain significance for improving the device design. For example, in order to reduce the output capacitance, reducing the width of the source of the active region of the device can affect the first substrate capacitance Cds_sub4 of the first armor; another example is that when reducing the width of the drain of the active region of the device, it not only affects the length of the connection bridge capacitance Cds_br, but also affects the second substrate capacitance Cds_sub2, the first substrate capacitance Cds_sub3 of the first armor, and the first substrate capacitance Cds_sub4 of the first armor.
[0083] The semiconductor devices of the present invention include, but are not limited to: high-power high electron mobility transistors (HEMTs) operating in high-voltage and high-current environments, transistors with a silicon-on-insulator (SOI) structure, gallium arsenide (GaAs)-based transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), metal-insulator-semiconductor heterojunction field-effect transistors (MISHFETs), or other field-effect transistors. The modeling method for the semiconductor devices provided by the embodiments of the present invention can be widely used in the semiconductor device manufacturing fields such as radio frequency and microwave, and power electronics. In particular, it has more obvious advantages for gallium nitride electronic devices with a wide bandgap, high electron mobility, high breakdown field strength, and good thermal conductivity.
[0084] It should be understood that various forms of the processes shown above can be used, and steps can be reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions of the present invention can be achieved. No limitation is imposed herein.
[0085] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.
Claims
1. A modeling method for a semiconductor device, characterized in that, Comprising: Construct a capacitance relation formula for multiple components, gate fingers, and gate widths that affect the device capacitance; Under set bias conditions, test the S-parameters of the device to be tested and extract the value of the device capacitance; For different devices to be tested, repeat the steps of testing the S-parameters of the device to be tested and extracting the value of the device capacitance; Substitute the values of the device capacitance, the number of gate fingers, and the gate width corresponding to different devices to be tested into the capacitance relation formula to obtain a full-rank equation constructed by at least two of the capacitance relation formulas, and calculate the general solution of the device capacitance varying with different gate fingers and gate widths.
2. The modeling method of the semiconductor device according to claim 1, characterized in that, The semiconductor device includes a source electrode, a drain electrode, a substrate, and a drain bus and / or a field plate; The device capacitance is an output capacitance; The components affecting the output capacitance include: a first interelectrode capacitance, a second interelectrode capacitance, a field plate capacitance, and a substrate capacitance; Wherein, the first interelectrode capacitance is the capacitance between the drain bus and the source electrode, the second interelectrode capacitance is the capacitance formed by the two-dimensional electron gas between the source electrode and the drain electrode; the field plate capacitance is the capacitance between the field plate and the drain electrode; the substrate capacitance is the capacitance between the substrate and the drain electrode.
3. The modeling method of the semiconductor device according to claim 2, wherein, The semiconductor device further includes a back gold; the substrate capacitance includes: a first substrate capacitance and a second substrate capacitance; Wherein, the first substrate capacitance is the capacitance between the drain bus and the back gold; the second substrate capacitance is the capacitance between the back gold and the drain electrode.
4. The modeling method of the semiconductor device according to claim 3, characterized in that, The first substrate capacitance includes: a first A substrate capacitance and a first B substrate capacitance; The first A substrate capacitance is the capacitance between the first part of the drain bus and the back gold, and the first part is the part of the drain bus in direct contact with the drain electrode; the first B substrate capacitance is the capacitance between the second part of the drain bus and the back gold, and the second part is the other part of the drain bus except the first part.
5. The modeling method of the semiconductor device according to claim 2, characterized in that, The semiconductor device further includes a connection bridge; the multiple components affecting the output capacitance further include: a connection bridge capacitance; the connection bridge capacitance is the capacitance formed by the connection bridge and the drain electrode.
6. The modeling method of the semiconductor device according to claim 2, wherein, In the step of repeating the test of the S-parameters of the device to be tested for different devices to be tested, test at least three different devices to be tested; In the step of obtaining a full-rank equation constructed by at least two of the capacitance relation formulas, construct a 3-order full-rank equation.
7. The modeling method of the semiconductor device according to claim 1, characterized in that, The semiconductor device includes a gate electrode and a source electrode; the device capacitance is an input capacitance; The multiple components affecting the input capacitance include: an intrinsic region capacitance and a parasitic capacitance; Wherein, the intrinsic region capacitance is the capacitance formed by the gate electrode and the two-dimensional electron gas under the source electrode.
8. The modeling method of the semiconductor device according to claim 7, characterized in that, The semiconductor device further includes a field plate and a gate bus; the parasitic capacitance includes: a first parasitic capacitance and a second parasitic capacitance; Wherein, the first parasitic capacitance is the capacitance between the gate electrode and the field plate; the second parasitic capacitance is the capacitance between the gate bus and the source electrode.
9. The modeling method of the semiconductor device according to claim 7, characterized in that, In the step of repeatedly performing the test on the S-parameters of the device under test for different devices under test, at least two different devices under test are tested; In the step of obtaining the full-rank equation constructed by at least two of the capacitance relationships, a second-order full-rank equation is constructed.
10. The modeling method of the semiconductor device according to claim 1, characterized in that, The proportion of the plurality of components in the capacitance relationship is determined by the device structure.