Spice circuit-level simulation modeling method based on CAS storage and calculation unit

Abstract

The invention discloses a Spice circuit-level simulation modeling method based on a CAS storage and calculation unit, and the method comprises the steps: firstly describing the physical process of a whole model in detail, including changing the resistance characteristics of a device through the growth of a CF channel in an SET process, and forming a current through a CF and a dielectric layer barrier by charges; cF cracks to form current in the RESET process, and the ion field diffusion and recombination process is modeled as an energy relaxation process; secondly, establishing a CAS Spice circuit-level simulation model for providing accurate circuit parameter design, and considering a physical mechanism, a CF evolution process, an electric transport process, a heat conduction effect and a parasitic effect of the resistance switch; then designing a reasonable Spice model code framework, including defining port information, constant and variable parameters, and initializing the overall parameters; and finally, analyzing related structures and principles of the physical process stored and memorized by the CAS storage and calculation unit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits and intelligent computing chips, and particularly relates to a Spice circuit-level simulation modeling method based on a CAS memory and computing unit. Background Art

[0002] In the field of integrated circuits and intelligent computing chips, with the continuous development of technology, the energy efficiency requirements for chips are increasing day by day. CAS (Cu Atom Switch, a microscopic switch based on the arrangement or migration of copper atoms) devices have the potential to be applied to high-energy-efficiency intelligent computing chips due to their unique physical properties. The CAS device forms a fusing mechanism based on natural CF (Conductive Filament), can be used as a memory storage unit, and is compatible with the current CMOS technology, showing advantages in terms of area and power consumption. Its working process involves the growth and rupture of CF, which changes the resistance characteristics of the device, thereby realizing the storage function. In the SET process, the CF channel grows, and charges form a current through the CF and the dielectric layer barrier, changing the device resistance; in the RESET process, the dissociated Cu ions and oxygen ions are released and recombined, resulting in the rupture of CF, also forming a current. The ion field diffusion and recombination process is modeled as an energy relaxation process. In both processes, the local current and electron transfer cause a local temperature increase, and the temperature affects the resistivity in different situations.

[0003] Currently, each process manufacturer has not developed a CAS memory storage IP and engineering simulation model design file suitable for commercialization. Although many researchers have carried out modeling work on the switching behavior of metal-oxide memristors and proposed some sub-circuit-based spice models to describe the physical characteristics of the devices, for a certain actual device characteristic, there is no general, convenient-to-fit, parameter-perfect physical compact model suitable for large-area array expansion and circuit design.

[0004] The existing models cannot accurately fit the simulation characteristics of the measured devices, and lack effective parameter design guidance in expanding synaptic arrays and circuit-level simulations. The specific manifestations are as follows: for a certain actual device characteristic, there is no general model, and different devices need to develop models again, with high cost and low efficiency; the models are not convenient to fit, and it is difficult to adjust according to the parameters of the actual devices, resulting in poor matching between the models and the actual devices; the parameters are not perfect, and various physical phenomena during the operation of the devices, such as heat conduction effects and parasitic effects, cannot be comprehensively considered, affecting the accurate description of the device behavior by the models; they are not suitable for large-area array expansion and circuit design, restricting their application in actual production. Summary of the Invention

[0005] The object of the present invention is to provide a Spice circuit-level simulation modeling method based on a CAS memory-computation unit, so as to solve the key problem of fitting the simulated characteristics of measured devices, realize the generalization of the model, facilitate fitting, improve parameters, and be applicable to large-area array expansion and circuit design, providing strong support for the design of high-energy-efficiency intelligent computing chips.

[0006] To solve the above technical problems, the present invention provides a Spice circuit-level simulation modeling method based on a CAS memory-computation unit. The Spice circuit-level simulation model based on the CAS memory-computation unit is realized through the following steps: Modeling the physical process: Describe the physical process of the entire model, including the growth of the conductive filament CF channel during the SET process, which changes the resistance characteristics of the device, and the formation of current by charges passing through the conductive filament CF and the dielectric layer barrier; during the RESET process, the conductive filament CF breaks to form current, and the ion field diffusion and recombination process is modeled as an energy relaxation process. Modeling the mathematical method: Establish a CAS Spice circuit-level simulation model for accurate circuit parameter design, considering the physical mechanism of resistive switching, the evolution process of the conductive filament CF, the electrical transport process, the heat conduction effect, and the parasitic effect, and introducing an error model. Spice model code framework: Design a reasonable Spice model code framework, including defining port information, constant and variable parameters, and initializing the overall parameters. Analyze the structure and principle related to the physical process of the CAS memory-computation unit's storage and memory: During the SET process, the conductive filament CF channel grows. At this time, charges pass through the conductive filament CF and the dielectric layer barrier to form current, resulting in a change in the device resistance; the RESET process is the opposite. After dissociation, Cu ions and oxygen ions are released, and the Cu ions return to the vicinity of the metal electrode and are reduced to copper atoms, resulting in the rupture of the conductive filament CF and the formation of current.

[0007] In one embodiment, the modeling of the physical process further includes: Based on random simulation, model the evolution process of the conductive filament CF, simplify its geometric shape to a cylindrical conductive filament CF, and model the programming and reset processes as the change in the gap distance x between the top electrode and the tip of the conductive filament CF; model the resistive switching and conduction behavior, and derive mathematical equations describing the resistance of the device in different states, such as the resistance R in the low-resistance state LRS , the resistance R of the Cu conductive filament CF , the resistance R of the dielectric layer Bar , and model the temperature dynamics of the conductive filament CF and the dielectric barrier with differential equations.

[0008] In one embodiment, the overall structure of the Spice circuit-level simulation model based on the CAS memory cell has two ports, namely the top electrode and the bottom electrode, which interact with the external circuit. The model resistance consists of the resistance R of the Cu conductive filament CF and the resistance R of the dielectric layer Bar ; Model the evolution process of the conductive filament CF, simplify it to establish a cylindrical conductive filament CF with a diameter of w between the two electrodes, and model the programming and resetting processes as the change of the gap distance x between the top electrode and the tip of the conductive filament CF. The resistance R in the low-resistance state LRS is described by the following formula: where ρ is the resistivity of the metal oxide, t ox is the thickness of the blocking layer, and S is the cross-sectional area of the conductive filament CF; before the formation of R LRS , the resistance characteristics of the device under the action of the electric field are composed of the quasi-Ohmic charge transport resistance R of the conductive filament CF CF and the trap-assisted tunneling transport resistance R in the potential barrier of the dielectric layer region Bar ; The gap distance x between the top electrode and the tip of the conductive filament CF is related to the temperature influence coefficient and is described by the following formula: where, is the temperature coefficient of resistivity, is the temperature of the conductive filament, is the measured temperature at; R Bar is related to the dielectric layer material and the activation energy factor of trap-assisted tunneling, and is described by the following formula: where, is the fitting parameter of the blocking layer resistance, is the tunneling length, is the conductivity of the blocking layer, is the temperature of the blocking layer, is the tunneling activation energy; During the programming SET process, the conductive filament CF gradually grows. The rupture process of the conductive filament CF during the reset RESET process corresponds to the entire conductive filament CF first breaking at the top electrode and then gradually extending in the inward direction as the voltage increases. The gap distance x between the tip of the conductive filament CF and the top electrode determines the resistance of the device between the high-resistance state HRS and the low-resistance state LRS, which is determined by the following formula: SET:

[0009] RESET: ; wherein is the transient response frequency, is the bond-breaking activation energy, is the bond-breaking field enhancement factor, is the oxygen ion diffusion activation energy, is the oxygen ion diffusion field enhancement factor, is the barrier layer thickness, is the oxygen vacancy drift velocity, is the copper ion drift velocity, is the barrier layer conductivity, a is the fitting factor of the IV curve conduction slope, and b is the fitting factor of the IV curve conduction curvature.

[0010] In one embodiment, the temperature dynamics of the conductive filament CF and the dielectric barrier are modeled using differential equations, including: The temperature dynamics of the conductive filament CF and the dielectric barrier are modeled using the following formula, applicable to the case of being driven by extremely short pulses: wherein, is the conductive filament temperature, is the reciprocal of the CF thermal capacitance, is the CF potential difference, is the overall current, is the CF thermoelectric conductivity, is the ambient temperature, is the overall thermoelectric conductivity, is the barrier layer temperature, is the reciprocal of the barrier layer thermal capacitance, is the barrier layer potential difference, is the barrier layer thermoelectric conductivity.

[0011] A Spice circuit-level simulation modeling method based on a CAS memory-computation unit provided by the present invention can be used in energy-efficient intelligent computing chips, provide parameter design guidance for expanding synaptic arrays and circuit-level simulations, and achieve accurate fitting of the measured device simulation characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram of the Spice model of the CAS memory-computation unit in an embodiment of the present invention.

[0013] Figure 2 is the overall code design framework of the model of the CAS memory-computation unit in an embodiment of the present invention.

[0014] Figure 3It is the code design framework for the SET / RESET process in the normal mode of the CAS memory - computing unit in the embodiments of the present invention.

[0015] Figure 4 It is the code design framework for updating the resistance model in the RTN mode of the CAS memory - computing unit in the embodiments of the present invention.

[0016] Figure 5 It is the model circuit simulation structure of the CAS memory - computing unit in the embodiments of the present invention.

[0017] Figure 6 It is the simulation method for the circuit IV characteristic curve and transient pulse response curve of the CAS memory - computing unit in the embodiments of the present invention.

[0018] Figure 7 It is the simulation result diagram of the circuit IV characteristic curve of the CAS memory - computing unit in the embodiments of the present invention.

[0019] Figure 8 It is the simulation result diagram of the transient pulse response curve of the CAS memory - computing unit in the embodiments of the present invention. Specific embodiments

[0020] The following further details a Spice circuit - level simulation and modeling method based on a CAS memory - computing unit proposed by the present invention in combination with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in very simplified forms and use non - precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0021] The present invention provides a Spice circuit - level simulation and modeling method based on a CAS memory - computing unit, which is specifically realized through the following technical solutions: Modeling physical process: Describe in detail the physical process of the entire model, including the growth of the CF (Conductive Filament) channel during the SET process, which changes the device resistance characteristics, the charge passing through the CF, and the formation of current through the dielectric layer barrier; during the RESET process, the rupture of the CF forms current, and the ion field diffusion and recombination process is modeled as an energy relaxation process, and the influence of local temperature increase on the resistivity in both processes is considered. Through such a comprehensive and accurate description of the physical process, a solid foundation is provided for the establishment of the model, solving the problem in the prior art that the description of the device physical process is incomplete, resulting in the model being unable to accurately fit the actual device behavior.

[0022] Modeling mathematical methods: Establish a CAS Spice circuit-level simulation model for accurately providing circuit parameter design, considering the physical mechanism of resistive switching, the CF evolution process, the electron transport process, the heat conduction effect, and parasitic effects, and introducing an error model in specific cases. Based on stochastic simulation, model the CF evolution process, simplify its geometric shape to a cylindrical CF, and model the programming and resetting processes as the change in the gap distance x between the top electrode and the tip of the CF. Model the resistive switching and conduction behaviors, and derive mathematical equations describing the resistance of the device in different states, such as the resistance R LRS in the low-resistance state, the resistance R CF of the Cu conductive filament, the resistance R Bar of the dielectric layer, etc. Model the temperature dynamics of the CF and the dielectric barrier using differential equations. Through these mathematical methods, comprehensively consider various factors affecting the device behavior, achieve an accurate mathematical description of the device behavior, and solve the problems of imperfect model parameters and inability to comprehensively consider device physical phenomena in the prior art. In addition, by introducing an error model, consider the problems brought by the instability of the memristive device analog storage operation, make the model more in line with the actual situation, and improve the accuracy and practicality of the model.

[0023] Spice model code framework: Design a reasonable Spice model code framework, including defining port information, constant and variable parameters, and initializing the overall parameters. The model includes a normal mode and an RTN (Random Telegram noise) mode. The RTN mode is only enabled during transient analysis, and the change in resistance during the SET / REST process of the device is simulated by calculating and updating the resistance through theoretical calculation formulas in different modes. The design of this code framework enables the model to flexibly adapt to different analysis requirements, facilitates users to operate and adjust, and solves the problems that the model in the prior art is not convenient to fit and difficult to adjust according to actual needs. At the same time, by accurately simulating the resistance change, it provides a reliable basis for circuit-level simulation, which helps to achieve large-area array expansion and circuit design.

[0024] Analyze the relevant structures and principles of the physical process of storing and memorizing in the CAS memory-computation unit. From a physical process perspective, during the SET process, the CF channel grows. At this time, charges form a current through the CF and the dielectric layer barrier, resulting in a change in the device resistance. This is because redox reactions occur between the metal electrode and the dielectric layer, generating a conductive CF channel. As the CF grows, its connection with the top electrode changes, thus affecting the passage of current and further changing the resistance. The RESET process is the opposite. After dissociation, Cu ions and oxygen ions are released. The Cu ions return to the vicinity of the metal electrode and are reduced to copper atoms, causing the CF to break and forming a current. In these two processes, the ion field diffusion and recombination process is modeled as an energy relaxation process. At the same time, local current and electron transfer cause a local temperature increase, and temperature affects the resistivity. For example, during the growth or breakage of the CF, the change in temperature will affect the resistance characteristics of the CF and the dielectric layer.

[0025] As Figure 1 shown, the overall structure of the Spice circuit-level simulation model of the CAS memory-computation unit proposed in the present invention has two ports, namely the top electrode and the bottom electrode, which interact with the external circuit. The model resistance is composed of the Cu conductive filament resistance R CF and the dielectric layer resistance R Bar .

[0026] Model the CF evolution process. Simplify it to establish a cylindrical CF with a diameter of w between two electrodes. The programming and resetting processes are modeled as the change in the gap distance x between the top electrode and the tip of the CF, as Figure 1 shown. Through this simplification, it is more convenient to describe the evolution of the CF with mathematical equations. For the resistance switching and conduction behaviors, a series of mathematical equations are derived. The resistance R LRS in the low-resistance state is described by the following formula: where ρ is the resistivity of the metal oxide, t ox is the thickness of the blocking layer, and S is the cross-sectional area of the CF. Before the formation of R LRS , the resistance value characteristics of the device under the action of the electric field are composed of the quasi-Ohmic charge transport resistance R CF of the CF and the trap-assisted tunneling transport resistance R Bar in the dielectric layer region barrier. The gap distance x between the top electrode and the tip of the conductive filament CF is related to the temperature influence coefficient and is described by the following formula: where, is the temperature coefficient of resistivity, is the temperature of the conductive filament, is Measured temperature below; R Bar Related to factors such as dielectric layer material and activation energy of trap-assisted tunneling, and is described by the following formula: During the programming (SET) process, the CF gradually grows. The rupture process of the CF during the reset (RESET) process corresponds to the entire CF first disconnecting at the top electrode and then gradually extending in the inward direction as the voltage increases. The gap distance x between the CF tip and the top electrode in these two processes determines the resistance of the device between the HRS (High-Resistance State) and the LRS (Low-Resistance State), and is determined by the following formula: SET:

[0027] RESET:

[0028] Where Is the transient response frequency, Is the activation energy of bond breaking, Is the bond-breaking field enhancement factor, Is the activation energy of oxygen ion diffusion, Is the oxygen ion diffusion field enhancement factor, Is the barrier layer thickness, Is the oxygen vacancy drift velocity, Is the copper ion drift velocity, Is the barrier layer conductivity, a is the fitting factor of the IV curve conduction slope, and b is the fitting factor of the IV curve conduction curvature.

[0029] The temperature dynamics of the CF and the dielectric barrier are modeled by the following formula, which is applicable to the case driven by extremely short pulses: Where, Is the temperature of the conductive filament, Is the reciprocal of the CF thermal capacitance, Is the CF potential difference, Is the overall current, Is the CF thermoelectric conductivity, Is the ambient temperature, Is the overall thermoelectric conductivity, Is the barrier layer temperature, Is the reciprocal of the barrier layer thermal capacitance, Is the barrier layer potential difference, is the barrier layer thermal conductivity. These mathematical equations comprehensively and accurately describe the electrical and thermal characteristics of the device in different states, providing a basis for accurate simulation of the model. As shown in Table 1, the model defines the constant and variable parameters used in mathematical calculations, including the actual physical parameters of the device, initializes the overall parameters, and through physical description and mathematical methods, targeted parameter adjustment can be used to fit and simulate the measured device performance.

[0030] Table 1 Design Parameters of the Mathematical Modeling of the CAS Memory and Computing Unit Conventional parameters Description Unit rho Resistivity of metal oxide Ω·nm <![CDATA[t ox > Barrier layer thickness nm <![CDATA[S0]]> Cross-section of conductive filament <![CDATA[nm 2 > <![CDATA[E a > Tunneling activation energy eV <![CDATA[T0]]> Ambient temperature K <![CDATA[L0]]> Unit tunneling length nm <![CDATA[V0]]> HRS non-linearity factor V α Temperature coefficient of resistivity 1 / K β Fitting parameter of barrier layer resistance NA <![CDATA[c0]]> Transient response frequency Hz <![CDATA[C pb > Barrier layer thermal capacitance J / K <![CDATA[C pcf > CF thermal capacitance J / K <![CDATA[k Bar > Barrier layer thermoelectric conductivity W / K <![CDATA[k cf > CF thermoelectric conductivity W / K <![CDATA[k ex > Overall thermoelectric conductivity W / K <![CDATA[E ad > Activation energy of oxygen ion diffusion eV g Field enhancement factor of oxygen ion diffusion e·nm a Fitting factor of IV curve conduction slope e·nm b Fitting factor of IV curve conduction curvature NA <![CDATA[E ag > Activation energy of bond breakage eV gg Field enhancement factor of bond breakage e·nm As Figure 2 shown, the Spice model code framework implemented by the present invention is divided into a normal mode and an RTN mode.

[0031] As Figure 3 shown, in the normal mode, the change of resistance during the SET / RESET process of the device is simulated through a specific calculation process. According to the parameters and equations determined by the above physical process and mathematical model, the resistance is calculated and updated, so as to realize the simulation of the resistance change under the normal working state of the device.

[0032] In the RTN mode, as Figure 4 shown, considering the influence of the RTN (random telegraph noise) phenomenon on the current fluctuation of the device, when simulating the resistance change, white Gaussian noise is added to the CF cross-section and the barrier thickness during the SET and RESET events to obtain the SET and RESET variability of the device. In this way, in the RTN mode, the resistance change and current fluctuation caused by noise factors during the actual operation of the device can be more accurately simulated, improving the authenticity and reliability of the model.

[0033] As Figure 5 shown, circuit-level simulation tests are carried out on the established model. The simulation needs to connect a MOS transistor in series as a current-limiting device. Since the IV curve scan needs to perform positive and negative voltage scans at the unidirectional end, in the case of negative voltage scan, a single diode is introduced to isolate the MOS transistor channel to realize the SET function test.

[0034] As Figure 6 shown, a method for simulating the IV characteristics and transient pulse response of the model is provided, including single-ended positive and negative voltage continuous scans and transient pulse excitation responses.

[0035] As Figure 7 shown, it is the IV characteristic cycle simulation curve of the model under the default parameter settings. It can be seen that the model well realizes the conduction reset and stepped resistance states, and there are stability changes with the cycle period.

[0036] As Figure 8As shown, it is the transient pulse response curve of the model under the default parameter settings. It can be seen that in the transient simulation of the model, applying pulse excitations with different amplitudes will produce different resistive state programming effects.

[0037] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure fall within the protection scope of the claims.

Claims

1. A Spice circuit-level simulation modeling method based on a CAS memory-computation unit, characterized in that The Spice circuit-level simulation model based on the CAS memory-computation unit is implemented through the following steps: Modeling the physical process: Describe the physical process of the entire model, including the growth of the conductive filament CF channel during the SET process, which changes the device resistance characteristics, and the formation of current by the charge passing through the conductive filament CF and the dielectric layer barrier; during the RESET process, the rupture of the conductive filament CF forms current, and the ion field diffusion and recombination process is modeled as an energy relaxation process; Modeling the mathematical method: Establish a CAS Spice circuit-level simulation model for accurate circuit parameter design, considering the physical mechanism of resistive switching, the evolution process of the conductive filament CF, the electrical transport process, the heat conduction effect, and the parasitic effect, and introduce an error model; Spice model code framework: Design a reasonable Spice model code framework, including defining port information, constant and variable parameters, and initializing the overall parameters; Analyze the structure and principle related to the physical process of the CAS memory-computation unit storing and memorizing: During the SET process, the conductive filament CF channel grows, and at this time, the charge forms current through the conductive filament CF and the dielectric layer barrier, resulting in a change in the device resistance; The RESET process is the opposite. The dissociated Cu ions and oxygen ions are released and return to recombine near the metal electrode, resulting in the rupture of the conductive filament CF and the formation of current.

2. The Spice circuit-level simulation modeling method based on the CAS computing-in-memory unit according to claim 1, wherein, The described physical process of modeling further includes: based on stochastic simulation, modeling the evolution process of the conductive filament CF, simplifying its geometric shape to a cylindrical conductive filament CF, and modeling the programming and resetting processes as the change in the gap distance between the top electrode and the tip of the conductive filament CF; modeling the resistive switching and conduction behaviors, and deriving mathematical equations describing the resistance of the device in different states, such as the resistance R in the low-resistance state, the resistance R of the Cu conductive filament, the resistance R of the dielectric layer, and modeling the temperature dynamics of the conductive filament CF and the dielectric barrier using differential equations. ; modeling the resistive switching and conduction behaviors, and deriving mathematical equations describing the resistance of the device in different states, such as the resistance R in the low-resistance state LRS , the resistance R of the Cu conductive filament CF , the resistance R of the dielectric layer Bar , and modeling the temperature dynamics of the conductive filament CF and the dielectric barrier using differential equations.

3. The Spice circuit-level simulation modeling method based on the CAS computing-in-memory unit according to claim 2, wherein, The overall structure of the Spice circuit-level simulation model based on the CAS memory-computing unit has two ports, namely the top electrode and the bottom electrode, which interact with the external circuit. The model resistance consists of the resistance R of the Cu conductive filament CF and the resistance R of the dielectric layer Bar ; Model the evolution process of the conductive filament CF, simplify it to establish a cylindrical conductive filament CF with a diameter of w between two electrodes, and model the programming and resetting processes as the change of the gap distance x between the top electrode and the tip of the conductive filament CF. The resistance R in the low-resistance state LRS is described by the following formula: where ρ is the resistivity of the metal oxide, t ox is the thickness of the blocking layer, and S is the cross-sectional area of the conductive filament CF; before forming R LRS , the resistance characteristics of the device under the action of an electric field are composed of the quasi-Ohmic charge transport resistance R CF of the conductive filament CF and the trap-assisted tunneling transport resistance R Bar in the potential barrier of the dielectric layer region; R CF is related to the length x of the conductive filament CF from the top electrode and the temperature influence coefficient, and is described by the following formula: Among them, is the temperature coefficient of resistivity, is the temperature of the conductive filament, is the measured temperature at; R Bar is related to factors such as the dielectric layer material and the activation energy of trap-assisted tunneling, and is described by the following formula: Among them, is the fitting parameter of the barrier layer resistance, is the tunneling length, is the conductivity of the barrier layer, is the temperature of the barrier layer, is the tunneling activation energy; Programming During the SET process, the conductive filament CF gradually grows. The rupture process of the conductive filament CF during the RESET process corresponds to the entire conductive filament CF first disconnecting at the top electrode and then gradually extending in the inward direction as the voltage increases. The gap distance x between the tip of the conductive filament CF and the top electrode in these two processes determines the resistance of the device between the high-resistance state HRS and the low-resistance state LRS, which is determined by the following formula: SET: RESET: ; wherein is the transient response frequency, is the bond-breaking activation energy, is the bond-breaking field enhancement factor, is the oxygen ion diffusion activation energy, is the oxygen ion diffusion field enhancement factor, is the barrier layer thickness, is the oxygen vacancy drift velocity, is the copper ion drift velocity, is the barrier layer conductivity, a is the fitting factor of the IV curve conduction slope, and b is the fitting factor of the IV curve conduction curvature.

4. The Spice circuit-level simulation modeling method based on the CAS computing-in-memory unit according to claim 3, wherein, The temperature dynamics of the conductive filament CF and the dielectric barrier are modeled using differential equations, including: The temperature dynamics of the conductive filament CF and the dielectric barrier are modeled using the following formula, which is applicable to the case of being driven by extremely short pulses: These mathematical equations comprehensively and accurately describe the electrical and thermal characteristics of the device in different states, providing a basis for accurate simulation of the model.

Images