ALD (atomic layer deposition) method for seed layer in silicon through hole with high aspect ratio

Abstract

The invention provides an ALD (atomic layer deposition) method for a seed layer in a high-aspect-ratio silicon through hole, which comprises the following steps of: preparing the high-aspect-ratio silicon through hole on a substrate, and enabling the aspect ratio of the silicon through hole to be greater than or equal to 10: 1; depositing a copper film or a cobalt film in the silicon through hole by adopting ALD (Atomic Layer Deposition), or depositing a copper seed layer after preparing an insulating layer and a diffusion barrier layer; wherein a precursor adopted for depositing the copper film or the copper seed layer comprises at least one of bis (hexafluoroacetylacetone) copper, dimethylamino-2-propoxy copper, bis (dimethylamino-2-propoxy) copper and bis (N, N '-di-sec-acetamidino) copper, and ZnEt2; and performing secondary annealing treatment, wherein the temperature of the secondary annealing treatment is higher than that of the primary annealing treatment. By adopting the technical scheme of the invention, the obtained seed layer is more compact, flat and uniform, the coverage rate of the surface, the side wall and the bottom is good, and successful preparation of a subsequent electroplated layer is facilitated.

Description

Technical Field

[0001] The present invention relates to the field of advanced chip integration packaging, and particularly to an ALD deposition method for a seed layer in a through-silicon via with a high aspect ratio. Background Art

[0002] TSV (through silicon via) is a key technology for 3D integrated circuits, which can improve chip performance and functional density by providing vertical interconnections. Small-diameter (<3 µm), high-aspect-ratio TSVs are widely used in artificial intelligence chips, radio frequency chips, CMOS image sensors, and MEMS devices. However, the deposition process inside the vias still faces significant challenges. Traditional methods such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) have insufficient coverage and film uniformity in high-aspect-ratio TSVs. Atomic layer deposition (ALD), due to its surface self-limiting reaction and atomic-level film thickness control ability, can effectively improve deposition uniformity, reduce surface defects of the film layer, and enhance the reliability of subsequent copper electroplating filling, and can be used as one of the promising potential solutions.

[0003] Currently, the research on TSV via filling mainly focuses on using PVD and CVD methods to prepare insulating layers such as SiO2 and Al2O3, using ALD and magnetron sputtering principles to prepare diffusion barrier layers (such as TaN and TiN), mainly using PVD and sputtering methods to prepare seed layers, and finally using electroplating methods for copper filling. However, the above methods face challenges of precursor diffusion limitation and deposition uniformity in the application of high-aspect-ratio TSVs. Summary of the Invention

[0004] In view of the above technical problems, the present invention discloses an ALD deposition method for a seed layer in a through-silicon via with a high aspect ratio. Herein, the high aspect ratio means the depth:width ≥ 10:1.

[0005] For this, the technical solution adopted by the present invention is as follows: An ALD deposition method for a seed layer in a through-silicon via with a high aspect ratio, comprising the following steps: Step S1, preparing a through-silicon via with a high aspect ratio on a substrate, wherein the aspect ratio of the through-silicon via ≥ 10:1; Step S2: Prepare an insulating layer and a diffusion barrier layer in the through-silicon via by ALD, and then deposit a copper film or a cobalt film seed layer. Among them, the precursors used in depositing the copper film or the copper seed layer include at least one of copper bis(hexafluoroacetylacetonate), copper dimethylamino-2-propoxide, Cu(dmamb)2 (bis(dimethylamino-2-propoxy)copper), and Cu(sBu-Me-amd)2 (bis(N,N'-di-sec-butylethylamidinato)copper), and diethylzinc (ZnEt2); the precursors used in depositing the cobalt film include at least one of Co(C5H5)2, C5H5Co(CO)2, and C 12 H 10 at least one of Co2O6, and ZnEt2; Step S3: Perform a secondary annealing treatment, where the temperature of the second annealing is higher than that of the first annealing. Further, the temperature of the second annealing is 300 - 400 °C higher than that of the first annealing.

[0006] As a further improvement of the present invention, in Step S1, before preparing the through-silicon via, after the substrate is cleaned, dried, argon plasma treatment is performed.

[0007] As a further improvement of the present invention, the cleaning and drying include ultrasonic cleaning with isopropyl alcohol, then secondary ultrasonic cleaning with deionized water, and then drying with nitrogen; further, the cleaning time for each time is at least 15 min.

[0008] As a further improvement of the present invention, the time of the argon plasma treatment is 15 - 30 min. Further, the temperature of the argon plasma treatment is 20 - 40 °C.

[0009] As a further improvement of the present invention, in Step S1, on the substrate, by using the method of deep reactive ion etching and the BOSCH process cycle etching passivation, a through-silicon via with a high aspect ratio is formed. Further, the gases required for the deep reactive ion etching are sulfur hexafluoride (SF6) and octafluorocyclobutane (C4F8).

[0010] As a further improvement of the present invention, in Step S3, the secondary annealing treatment includes: The first time: Anneal at 200 - 300 °C for 3 - 5 h in the ALD chamber in an in-situ vacuum environment or a protective atmosphere environment; The second time: Place it in a CVD tube furnace and anneal at 500 - 700 °C for 3 - 5 h in a vacuum environment or a protective atmosphere environment.

[0011] As a further improvement of the present invention, the protective atmosphere is nitrogen or an inert gas. Further, the inert gas is argon.

[0012] As a further improvement of the present invention, the insulating layer is prepared by thermal oxidation, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD).

[0013] As a further improvement of the present invention, the diffusion barrier layer is prepared by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electrochemical deposition (ECD), magnetron sputtering, molecular beam epitaxy (MBE) or electroless plating.

[0014] As a further improvement of the present invention, the thickness of the insulating layer is 100 nm to 1 µm.

[0015] As a further improvement of the present invention, the thickness of the diffusion barrier layer is 2 to 20 nm.

[0016] As a further improvement of the present invention, the material of the insulating layer includes at least one of SiO2, Al2O3, HfO2, PI and BCB.

[0017] As a further improvement of the present invention, the material of the diffusion barrier layer includes at least one of Ta, Ti, TaN and TiN.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: By adopting the technical solution of the present invention, the obtained seed layer is denser, flatter and more uniform. Whether it is on the middle sidewall or the bottom of the through hole, the coverage rate and thickness uniformity of the seed layer are good. The seed layer particles are dense and uniform, which is convenient for subsequent electroplating filling of the holes. Moreover, compared with the seed layer prepared by magnetron sputtering, it has a better conformal effect and better copper film connectivity; it solves the problem of uneven electroplating filling of the holes caused by low deposition coverage rate and poor uniformity of the seed layer in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic optical microscope diagram of the surface of a high aspect ratio silicon through hole by deep reactive ion etching in Example 1 of the present invention.

[0020] Figure 2 It is a schematic scanning electron microscope (SEM) diagram of the surface of a high aspect ratio silicon through hole by deep reactive ion etching in Example 1 of the present invention.

[0021] Figure 3 It is a schematic overall scanning electron microscope (SEM) diagram of a high aspect ratio silicon through hole by deep reactive ion etching in Example 1 of the present invention.

[0022] Figure 4 Schematic diagram of local sidewall scanning electron microscope (SEM) of high aspect ratio silicon through - hole by deep reactive ion etching in Embodiment 1 of the present invention.

[0023] Figure 5 Schematic diagram of bottom scanning electron microscope (SEM) of high aspect ratio silicon through - hole by deep reactive ion etching in Embodiment 1 of the present invention.

[0024] Figure 6 Comparison of SEM images of copper seed layer prepared by atomic layer deposition in Embodiment 1 of the present invention and copper seed layer prepared by magnetron sputtering in Comparative Example 1, where (a) is Comparative Example 1 and (b) is Embodiment 1.

[0025] Figure 7 AFM schematic diagram of copper seed layer thickness on the surface of silicon substrate by atomic layer deposition for 400 cycles in Embodiment 1 of the present invention, where (b) is the local enlarged view of the box in (a) and (c) is the film thickness obtained by atomic force microscope.

[0026] Figure 8 EDS schematic diagram of silicon through - hole by atomic layer deposition for 400 cycles in Embodiment 1 of the present invention.

[0027] Figure 9 Photo of four - probe test resistance characteristics after annealing in Embodiment 1 of the present invention. Detailed implementation manners

[0028] The following further elaborates on the preferred embodiments of the present invention.

[0029] An ALD deposition method for seed layer in high aspect ratio silicon through - hole includes the following steps: Step S1, preparing a high aspect ratio silicon through - hole on a substrate, where the aspect ratio of the silicon through - hole ≥ 10:1.

[0030] Step S2, using ALD to prepare an insulating layer and a diffusion barrier layer in the silicon through - hole, and then depositing a copper film or a cobalt film seed layer.

[0031] Step S3, performing a secondary annealing treatment.

[0032] For those with an insulating layer and a diffusion barrier layer, first, an insulating layer prepared by methods such as PVD, CVD, thermal oxidation, and ALD is located between the TSV and the diffusion barrier layer to perform electrical blocking and reduce leakage current. At the same time, the low-dielectric-constant insulating material will also reduce the parasitic capacitance of the interconnection, reduce the total signal delay and loss during transmission, and can also reduce crosstalk. In addition, the insulating layer can also enhance the mechanical strength of the TSV and improve stability. The materials of the insulating layer include at least one of SiO2, Al2O3, HfO2, PI, and BCB, and the thickness of the insulating layer is 100nm to 1µm.

[0033] Then, methods such as Sputtering, ALD, PVD, and CVD are used to prepare a diffusion barrier layer, which is located between the insulating layer and the seed layer. The diffusion barrier layer plays an important role between the various TSV film layers. Since metals such as copper and aluminum will diffuse into the silicon substrate or the dielectric layer, resulting in device short-circuit or leakage, the main function of the diffusion barrier layer is to block the diffusion and migration of metal atoms into the internal silicon substrate or dielectric layer through a dense film layer, ensuring that the device can work stably and improving the reliability of the interconnection. Special diffusion barrier layers such as Ti and Ta can also be selected. At the same time, these materials can also be used as adhesion layers to enhance the bonding strength of the subsequent seed layer and improve the uniformity of the seed layer. The materials of the diffusion barrier layer include at least one of Ta, Ti, TaN, and TiN, and the thickness of the diffusion barrier layer is 2 to 20nm.

[0034] The seed layer, as a pre-process of electroplating, is located between the diffusion barrier layer and the electroplated metal. Its main function is to serve as a conductive substrate to provide a current path for subsequent copper electroplating, ensuring that metal ions in the electroplating solution can uniformly cover the surface of the seed layer. The film layer effect of the seed layer directly determines the quality of subsequent electroplating. If the seed layer is not evenly covered, problems such as holes or uneven coverage will occur in the electroplated metal. Conventional methods include sputtering and PVD.

[0035] In step S2 of this embodiment, the copper source precursors for depositing the copper film or the seed layer are at least one of copper hexafluoroacetylacetonate (Cu(hfac)2), dimethylamino-2-propoxy copper, Cu(dmamb)2, and Cu(sBu-Me-amd)2, or the cobalt source precursors are at least one of Co(C5H5)2, C5H5Co(CO)2, and C 12 H 10 At least one of Co2O6, and the other precursor is ZnEt2. The cobalt source precursors used for depositing the cobalt film are at least one of Co(C5H5)2, C5H5Co(CO)2, and C 12 H 10 At least one of Co2O6, and the other precursor is ZnEt2.

[0036] In step S1, before fabricating the through-silicon via with a high aspect ratio, the substrate is first processed, including: The substrate is ultrasonically cleaned with isopropyl alcohol for the first time for 15 min, then ultrasonically cleaned with deionized water for the second time for 15 min, and then dried with nitrogen; the nitrogen-dried substrate is subjected to argon plasma treatment.

[0037] Furthermore, the time of the argon plasma treatment is 15 - 30 min; the temperature of the argon plasma treatment is 20 - 40 °C.

[0038] Cleaning the substrate can ensure the cleanliness of the substrate surface. Here, taking the cleaning of a silicon wafer as an example, the cleaning steps can be: first, put the silicon wafer into a beaker, pour an appropriate amount of isopropyl alcohol, and perform ultrasonic cleaning for 15 min. Then pour out the isopropyl alcohol, inject an appropriate amount of deionized water, and perform ultrasonic cleaning again for 15 min. After that, take out the silicon wafer, dry it with nitrogen, and then place the silicon wafer in a plasma treatment device. At 20 - 40 °C, perform argon plasma treatment for 15 - 30 min. Through plasma treatment, defects can be introduced on the substrate surface, improving the adhesion of the substrate and making the substrate surface more active, which is beneficial to the bonding between the substrate and the subsequent film layer.

[0039] In step S3, the secondary annealing treatment includes the following steps: Set the first vacuum annealing at 200 - 300 °C in the ALD chamber; then place the sample in the heating area of the CVD tube furnace for the second annealing, and set the annealing temperature at 500 - 700 °C. During the above two annealing processes, a vacuum or inert gas atmosphere can be maintained. The inert gas can be selected as N2 or Ar, and the annealing time is set at about 3 - 5 h.

[0040] The technical solutions of the present invention will be further described in detail below in conjunction with specific embodiments and the accompanying drawings. It should be understood that the following embodiments are only used to explain the present invention and are not used to limit the present invention. Embodiment 1

[0041] A method for depositing a cobalt film seed layer in a through-silicon via with a high aspect ratio (10:1) using an atomic layer deposition system (ALD), including: In step S1, the substrate material is Si; the substrate is first ultrasonically cleaned with isopropyl alcohol, then ultrasonically cleaned with deionized water for the second time, and then dried with nitrogen, with each cleaning time being 15 min. Then argon plasma treatment is performed. The time of the argon plasma treatment is 15 min, and the temperature of the argon plasma treatment is 40 °C.

[0042] Then, deep reactive ion etching is used on the surface of the substrate, and the Bosch process is adopted to perform a repeated cycle of etching and passivation processes using two gases, sulfur hexafluoride (SF6) and octafluorocyclobutane (C4F8), to form through-silicon vias with a high aspect ratio (≥10:1).

[0043] Step S2: After using ALD to first prepare an insulating layer and a diffusion barrier layer in the through-silicon vias, use ALD to deposit a Co film seed layer in the high aspect ratio through-silicon vias. Among them, the precursors used for depositing the copper film or the copper seed layer are at least one of Co(C5H5)2, C5H5Co(CO)2, and C 12 H 10 o2O6, and diethylzinc (ZnEt2). In this embodiment, Co(C5H5)2 and diethylzinc are used as precursors. Among them, the insulating layer is prepared by thermal oxidation method, the material is SiO2, and the thickness is 100 nm; the diffusion barrier layer is prepared by physical vapor deposition method, the material is Ti, and the thickness is 5 nm.

[0044] Step S3: Perform a secondary annealing treatment, including: setting a first vacuum annealing at 300 °C in the ALD chamber; then placing the sample in the heating area of a CVD tube furnace for a second annealing, and setting the annealing temperature at 700 °C. During the above two annealing processes, a vacuum or an inert gas atmosphere can be maintained. The inert gas can be selected from N2 or Ar. In this embodiment, a vacuum is maintained, and the annealing time is 3 h. Example 2

[0045] A method for depositing a copper film seed layer in a through-silicon via with a high aspect ratio (10:1) using an atomic layer deposition system (ALD). The difference in this embodiment is that in step S2, use ALD to first prepare an insulating layer and a diffusion barrier layer in the through-silicon vias, and then deposit the copper film seed layer, as well as the process parameters of the secondary annealing treatment in step S3. Specifically:[[]] In step S2, use PVD to prepare the insulating layer, which is disposed between the TSV and the diffusion barrier layer, the material is SiO2; the thickness is 200 nm; Use sputtering to prepare the diffusion barrier layer, which is disposed between the insulating layer and the seed layer, the material is Ta; the thickness is 10 nm; Then use ALD to deposit a Cu film in the high aspect ratio TSV. The precursors used for depositing the copper film are at least one of bis(hexafluoroacetylacetonato)copper, dimethylamino-2-propoxycopper, Cu(dmamb)2, and Cu(sBu-Me-amd)2, and diethylzinc (ZnEt2). In this embodiment, the precursors are bis(hexafluoroacetylacetonato)copper and diethylzinc.

[0046] Step S3: Perform secondary annealing, including: setting the temperature at 200°C in the ALD chamber for the first vacuum annealing; then placing the sample in the heating zone of a CVD tube furnace for the second annealing, with the annealing temperature set at 500°C. During the above two annealing processes, a vacuum or inert gas atmosphere can be maintained. The inert gas can be N2 or Ar. In this embodiment, it is an N2 atmosphere, and the annealing time is 5 h. Example 3

[0047] A method for depositing a copper film seed layer in a through-silicon via (TSV) with a high aspect ratio (10:1) using an atomic layer deposition system (ALD), comprising: Step S1: The substrate material is Si; first, ultrasonically clean the substrate with isopropyl alcohol, then perform a second ultrasonic cleaning with deionized water, and then dry it with nitrogen. The cleaning time for each time is 15 min. Then, perform argon plasma treatment. The time of the argon plasma treatment is 30 min, and the temperature of the argon plasma treatment is 20°C.

[0048] Then, use deep reactive ion etching on the surface of the substrate to form a through-silicon via with a high aspect ratio (≥10:1) through a repeated cycle of etching and passivation processes using two gases, sulfur hexafluoride (SF6) and octafluorocyclobutane (C4F8), by the BOSCH process.

[0049] Step S2: First, prepare an insulating layer and a diffusion barrier layer in the through-silicon via using ALD, and then deposit a Co film seed layer.

[0050] Prepare the insulating layer by CVD, which is disposed between the TSV and the diffusion barrier layer. The material is Al2O3; the thickness is 500 nm; Prepare the diffusion barrier layer by CVD, which is disposed between the insulating layer and the seed layer. The material is TiN; the thickness is 20 nm.

[0051] Deposit a Co film in the high aspect ratio TSV using ALD. The precursors used in depositing the cobalt film include at least one of Co(C5H5)2, C5H5Co(CO)2, and C 12 H 10 o2O6, and ZnEt2; Step S3: Perform secondary annealing, including: setting the temperature at 250°C in the ALD chamber for the first vacuum annealing; then placing the sample in the heating zone of a CVD tube furnace for the second annealing, with the annealing temperature set at 600°C. During the above two annealing processes, a vacuum or inert gas atmosphere can be maintained. The inert gas can be N2 or Ar. In this embodiment, it is an Ar atmosphere, and the annealing time is 4 h.

[0052] Comparative Example 1 Except that the preparation method of the Cu film is different, which is sputtering, the others are the same as in Example 1. Since the process of the Cu film in Comparative Example 1 does not have good conformality, the coverage rate of the film layer is not good, and the thickness uniformity is poor. The thickness at the re-opening is relatively thick, and the uniformity of Cu in the middle sidewall and bottom is poor. Therefore, in the subsequent electroplating process, it is easy for the filled metal to have holes and gaps, and the distribution is uneven, resulting in the final interconnection stability, which may lead to an increase in the overall resistance of the TSV, an increase in power consumption, and an impact on the signal transmission speed. In high-frequency applications, it will introduce parasitic capacitance or parasitic inductance, causing signal delay or crosstalk.

[0053] Perform performance characterization tests on the copper film seed layer deposited in the silicon through hole obtained in Example 1.

[0054] As Figure 1 shown is a schematic diagram of an optical microscope after depositing a copper seed layer on the surface of the TSV after deep reactive ion etching using atomic layer deposition. Figure 2 In it, perform scanning electron microscope characterization on the surface of the copper thin film that has been deposited. From Figure 2 it can be seen that the Cu particles are closely arranged, indicating that the Cu film has good denseness. Further, use the method of laser stealth dicing to cut the TSV, and then perform scanning electron microscope characterization on the silicon through hole. As Figure 3 shown, it shows the overall morphology of the TSV, and the aspect ratio is about 30:3. The morphology of the TSV is good, indicating that the etching effect is very good. Magnify and observe the local details of the TSV. As Figure 4 and Figure 5 shown, perform detailed characterization on the sidewall and bottom of the TSV respectively. It can be clearly seen that whether it is in the middle sidewall or the bottom of the through hole, the coverage rate of Cu is good, and the thickness uniformity is also good. The Cu particles are dense and uniform, demonstrating the good conformality effect of the ALD process. Figure 6 In it, compare the copper seed layers prepared by magnetron sputtering and atomic layer deposition. On the left and right in the figure are the copper seed layers prepared by magnetron sputtering and atomic layer deposition respectively. Obviously, the copper seed layer prepared by atomic layer deposition has better conformality and better connectivity of the copper film. Figure 7 In it, use an atomic force microscope (AFM) to measure the thickness of the Cu layer. The result of the thickness scan shows that after 400 cycles, the thickness of the deposited Cu film is about 64.511 nm. Then, perform EDS elemental analysis on the inside of the TSV through hole. The elemental distribution is as Figure 8 shown. In the elemental distribution, it can be seen that the concentration of the Cu element accounts for a relatively high proportion, indicating that the Cu element is evenly distributed inside the through hole.

[0055] The relevant electrical performance tests were carried out on the deposited Cu layer. Before annealing, the resistance of the Cu layer was in the megohm level and showed a non-conductive state, indicating that the internal connection effect of the Cu film was not good. Subsequently, annealing treatment was carried out. The resistance of the annealed Cu was measured again using a four-probe sheet resistance meter, and it was found that the resistance decreased significantly, about 0.67 mΩ·cm, and the electrical conductivity increased greatly. The test results are as Figure 9 shown. It can be seen that the secondary annealing treatment can effectively improve the uniformity of the seed layer, repair the material, rearrange the internal structure of the crystal, restore the integrity of the crystal lattice, and at the same time, the key point is that it can improve the conductivity and electrical properties.

[0056] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. An ALD deposition method for a seed layer in a silicon through hole with a high aspect ratio, characterized in that It includes the following steps: Step S1, preparing a through-silicon via with a high aspect ratio on a substrate, wherein the aspect ratio of the through-silicon via ≥ 10:1; Step S2, an insulating layer and a diffusion barrier layer are prepared in the through-silicon via by ALD, and then a copper film or a cobalt film seed layer is deposited; wherein, the precursors used in depositing the copper film or the copper seed layer include at least one of copper bis(hexafluoroacetylacetonate), copper dimethylamino-2-propoxide, bis(dimethylamino-2-propoxy)copper, and bis(N,N'-di-sec-amidinato)copper, and ZnEt2; the precursors used in depositing the cobalt film include at least one of Co(C5H5)2, C5H5Co(CO)2, and C 12 H 10 at least one of Co2O6, and ZnEt2; Step S3, performing a secondary annealing treatment, wherein the temperature of the second annealing is higher than that of the first annealing.

2. The ALD deposition method of the seed layer in the silicon through hole with a high aspect ratio according to claim 1, wherein: In step S1, before preparing the through-silicon via, after the substrate is cleaned and dried, argon plasma treatment is performed.

3. The ALD deposition method of the seed layer in the silicon through hole with a high aspect ratio according to claim 2, wherein: The cleaning and drying include ultrasonic cleaning with isopropyl alcohol, then secondary ultrasonic cleaning with deionized water, and then drying with nitrogen; the cleaning time for each time is at least 15 min.

4. The ALD deposition method of the seed layer in the silicon through hole with a high aspect ratio according to claim 2, wherein: The time of the argon plasma treatment is 15 - 30 min; the temperature of the argon plasma treatment is 20 - 40 °C.

5. The ALD deposition method of the seed layer in the silicon through hole with a high aspect ratio according to claim 1, wherein: In step S1, on the substrate, a through-silicon via with a high aspect ratio is formed by using a deep reactive ion etching method and a BOSCH process cycle for etching and passivation; the gases used in the deep reactive ion etching are sulfur hexafluoride and perfluorocyclobutane.

6. The ALD deposition method of the seed layer in the silicon through hole with a high aspect ratio according to claim 1, characterized in that: In step S3, the secondary annealing treatment includes annealing at 200 - 300 °C for 3 - 5 h in an ALD chamber in an in-situ vacuum environment or a protective atmosphere environment, and annealing at 500 - 700 °C for 3 - 5 h in a CVD tube furnace in a vacuum environment or a protective atmosphere environment.

7. The ALD deposition method of the seed layer in the high aspect ratio through-silicon via according to claim 6, wherein: The protective atmosphere is nitrogen or an inert gas, and the inert gas is argon.

8. The ALD deposition method of the seed layer in the high aspect ratio through-silicon via according to claim 1, wherein: The insulating layer is prepared by a method of thermal oxidation, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition or atomic layer deposition, and the diffusion barrier layer is prepared by a method of physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemcial deposition, magnetron sputtering, molecular beam epitaxy or electroless plating.

9. The ALD deposition method of the seed layer in the silicon through hole with a high aspect ratio according to claim 8, characterized in that: The thickness of the insulating layer is 100 nm - 1 µm, and the thickness of the diffusion barrier layer is 2 - 20 nm.

10. The ALD deposition method of the seed layer in the silicon through hole with a high aspect ratio according to claim 9, wherein: The material of the insulating layer includes at least one of SiO2, Al2O3, HfO2, PI, BCB; the material of the diffusion barrier layer includes at least one of Ta, Ti, TaN, TiN.

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