Chip stacking structure and packaging method

Abstract

This invention relates to the field of chip packaging technology, specifically disclosing a chip stacking structure and packaging method, comprising: at least two chip bodies, adjacent chip bodies being electrically connected via solder joints, and heat dissipation channels being provided between adjacent chip bodies, with the heat dissipation channels between any two adjacent chip bodies being interconnected. By providing heat dissipation channels between every two adjacent chip bodies and ensuring that the heat dissipation channels of each layer are interconnected, and connecting these heat dissipation channels to an external cooling device, effective heat dissipation can be achieved between every two adjacent chip bodies through liquid cooling, improving the heat dissipation capacity of the chip stacking structure, supporting the stacking of more chip bodies, resulting in higher integration, and providing reliable heat dissipation for high-power chips, ensuring the operational reliability of each chip body.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a chip stacking structure and packaging method. Background Technology

[0002] Chip stacking is a technology that vertically stacks multiple chips together to achieve higher integration and performance. It is widely used in smart electronic products, communication technology, computers and servers, and autonomous driving. Traditional packaging stacking is a technology that stacks multiple chips together using packaging technology, usually using bonding wires to connect the chips to the packaging substrate. 3D packaging stacking uses TSV (through silicon via) technology to achieve vertical interconnection between chips, which can significantly improve integration and performance.

[0003] Chip stacking structures can reduce the geometric dimensions of packages, and TSV (Through Silicon Via) technology can significantly shorten the length of electrical interconnects, thereby reducing signal delay and improving data processing speed. However, multi-layer chips with 3D package stacking structures have poor heat dissipation, which affects their stability in use.

[0004] Therefore, it is necessary to propose a chip stacking structure and packaging method to at least partially solve the problems existing in the prior art. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To at least partially solve the above problems, the present invention provides a chip stacking structure, comprising: at least two chip bodies, two adjacent chip bodies being electrically connected by a solder joint, a heat dissipation channel being provided between two adjacent chip bodies, and the heat dissipation channels between any two adjacent chip bodies being interconnected.

[0007] Preferably, the heat dissipation channel includes: a first channel groove and a second channel groove; in two adjacent chip bodies, the bottom of the upper chip body is provided with a first channel groove, and the top of the lower chip body is provided with a protrusion, the protrusion being provided with a second channel groove.

[0008] The chip body is also provided with a second through hole, and the second through hole in the upper chip body and the second through hole in the lower chip body are connected by a heat dissipation channel.

[0009] Preferably, the heat dissipation channel is arranged in an S-shape, and the second through holes on two adjacent chip bodies are located at the two ends of the heat dissipation channel; the heat dissipation channel can separate two adjacent horizontally or vertically soldered parts.

[0010] Preferably, the heat dissipation channels are arranged in a grid pattern, and the second through holes on two adjacent chip bodies are located at the diagonal points of the heat dissipation channels; the grid-shaped heat dissipation channels form an isolation area, and a soldering part is arranged in each isolation area.

[0011] Preferably, the heat dissipation channel is arranged in a continuous curved pattern, and the second through holes on two adjacent chip bodies are located at the two ends of the heat dissipation channel respectively; the heat dissipation channel passes around each solder joint in sequence, separating two horizontally adjacent and vertically adjacent solder joints.

[0012] Preferably, the second flow channel is provided with one or more combinations of a metal layer, a carbon nanotube layer, and a graphene layer.

[0013] Preferably, the chip body has a first through hole, and a conductive part is provided in the first through hole;

[0014] The welding part includes a welding body and a conductor; in two adjacent chip bodies, the bottom of the upper chip body is provided with a welding body, which is connected to the conductor, and the top of the lower chip body is provided with a conductor, which is connected to the conductor.

[0015] Preferably, a connection layer is provided between two adjacent chip bodies. The connection layer has a first clearance area corresponding to the soldering part and a second clearance area corresponding to the protrusion. The thickness of the connection layer is set to correspond to the height of the protrusion.

[0016] A packaging method for a chip stacked structure includes:

[0017] Prepare two adjacent chip bodies, create the first flow channel groove at the bottom of the upper chip body, and create the second flow channel groove at the top of the lower chip body;

[0018] In two adjacent chip bodies, a connection layer is formed on the bottom surface of the upper chip body, and a first clearance area and a second clearance area are formed on the connection layer; wherein, the first clearance area is formed at the position corresponding to the conductive part of the chip body, and the second clearance area is formed at the position corresponding to the first flow channel groove.

[0019] In two adjacent chip bodies, a solder body is made on the bottom surface of the upper chip body to connect the solder body to the conductive part, and a conductive part is welded on the top surface of the conductive part of the lower chip body.

[0020] Multi-layer chip bodies are stacked, pressure is applied to the top of the multi-layer chip bodies, and the solder body is soldered to the conductor through a vacuum reflow process. Adjacent chip bodies are connected through a connecting layer.

[0021] Preferably, after forming the second flow channel groove on top of the lower chip body, the process further includes: forming a metal layer in the second flow channel groove using an electroplating process, or forming a carbon nanotube layer or a graphene layer in the second flow channel groove using a spraying process.

[0022] Compared with the prior art, the present invention has at least the following beneficial effects:

[0023] The chip stacking structure and packaging method described in this invention provide a heat dissipation channel between every two adjacent chip bodies, and make the heat dissipation channels of each layer interconnected. The heat dissipation channels are connected to external cooling equipment, which can effectively dissipate heat between every two adjacent chip bodies through liquid cooling, improve the heat dissipation capacity of the chip stacking structure, support the stacking of more layers of chip bodies, achieve higher integration, and provide reliable heat dissipation for high-power chips, ensuring the operational reliability of each chip body.

[0024] The chip stacking structure and packaging method described in this invention, as well as other advantages, objectives and features of this invention, will be partly apparent from the following description, and partly understood by those skilled in the art through study and practice of this invention. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0026] Figure 1 This is a schematic diagram of the chip stacking structure described in this invention;

[0027] Figure 2 This is a schematic diagram of the S-shaped heat dissipation flow channel arrangement in the chip stacking structure described in this invention;

[0028] Figure 3 This is a schematic diagram of the heat dissipation channels arranged in a grid pattern in the chip stacking structure described in this invention;

[0029] Figure 4 This is a schematic diagram of the chip stacking structure described in this invention, in which the heat dissipation channels are arranged in a continuous curved pattern.

[0030] Figure 5 This is a schematic diagram of the chip stacking structure described in this invention, where multiple chip bodies are stacked together without vacuum reflow process.

[0031] Figure 6This is a schematic diagram of the structure in which a conductor is inserted into the first clearance area in the chip stacking structure described in this invention.

[0032] Figure 7 This is a schematic diagram of the chip stacking structure described in this invention, in which a metal layer, a carbon nanotube layer, and / or a graphene layer are disposed in the second flow channel groove.

[0033] Figure 8 This is a schematic diagram of the chip stacking structure packaging method of the present invention after the first and second flow channel grooves are fabricated on the chip body;

[0034] Figure 9 This is a schematic diagram of the structure of the interconnect layer fabricated on the chip body in the chip stacking structure packaging method of the present invention.

[0035] Figure 10 This is a schematic diagram of the structure in which a first clearance region and a second clearance region are formed on the interconnect layer in the chip stacking structure packaging method of the present invention.

[0036] Figure 11 This is a schematic diagram of the structure for fabricating the solder body and conductor in the chip stacking structure packaging method of the present invention. Detailed Implementation

[0037] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments, so that those skilled in the art can implement it based on the description.

[0038] It should be understood that terms such as “having,” “comprising,” and “including” as used herein do not exclude the presence or addition of one or more other elements or combinations thereof.

[0039] like Figure 1 As shown, the present invention provides a chip stacking structure, including: at least two chip bodies 1, two adjacent chip bodies 1 are electrically connected by a soldering part 3, a heat dissipation channel 2 is provided between two adjacent chip bodies 1, and the heat dissipation channel 2 between any two adjacent chip bodies 1 is connected.

[0040] The present invention mainly improves the 3D packaging stacking structure by setting heat dissipation channels 2 between every two adjacent chip bodies 1 and making the heat dissipation channels 2 of each layer connected. The heat dissipation channels 2 are connected to external cooling equipment, which can effectively dissipate heat between every two adjacent chip bodies 1 by liquid cooling, thereby improving the heat dissipation effect.

[0041] The above solution can improve the heat dissipation capacity of the chip stack structure, support the stacking of more layers of chip body 1, achieve higher integration, and provide reliable heat dissipation for high-power chips, ensuring the working reliability of each chip body 1.

[0042] like Figure 5 As shown, in one embodiment, the heat dissipation channel 2 includes: a first channel groove 21 and a second channel groove 22; in two adjacent chip bodies 1, the bottom of the upper chip body 1 is provided with a first channel groove 21, and the top of the lower chip body 1 is provided with a protrusion 7, and the protrusion 7 is provided with a second channel groove 22.

[0043] The chip body 1 is also provided with a second through hole 11, and the second through hole 11 of the upper chip body 1 and the second through hole 11 of the lower chip body 1 are connected through the heat dissipation channel 2.

[0044] The second through hole 11 is used to communicate with the second flow channel 22 located above it or with an external cooling device; or, the second through hole 11 is used to communicate with the first flow channel 21 located below it or with an external cooling device.

[0045] The first channel groove 21 and the second channel groove 22 are respectively provided. After the protrusion 7 of the lower chip body 1 contacts the bottom surface of the upper chip body 1, the first channel groove 21 and the second channel groove 22 form a heat dissipation channel 2. The second through hole 11 on the same chip body 1 is connected to the first channel groove 21 and / or the second channel groove 22 of the chip body 1, so that after the multiple layers of chip bodies 1 are stacked, the multiple layers of heat dissipation channels 2 can be connected through the second through hole 11.

[0046] The second through hole 11 on the top and bottom chip body 1 also needs to be connected to the cooling device. For example, a horizontal through hole connected to the second through hole 11 can be provided on the side of the bottom chip body 1 to facilitate connection with the cooling device. The second through hole 11 on the middle chip body 1 is only used to connect the heat dissipation channels 2 of the upper and lower layers.

[0047] Through the above design, the second through holes 11 located at the top and bottom layers can be used as the inlet and outlet of the circulating cooling fluid in the cooling device, thereby realizing heat dissipation of the multi-layer chip body 1.

[0048] The present invention provides three arrangements of heat dissipation channels 2, and the multiple heat dissipation channels 2 between the multilayer chip body 1 can be selected from one or more combinations of the three arrangements.

[0049] like Figure 2 As shown, in one embodiment, the heat dissipation channel 2 is arranged in an S-shape, and the second through holes 11 on two adjacent chip bodies 1 are located at the two ends of the heat dissipation channel 2 respectively; the heat dissipation channel 2 can separate two horizontally adjacent or vertically adjacent solder parts 3.

[0050] This embodiment is the first arrangement of the heat dissipation channel 2. The heat dissipation channel 2 can be arranged in an S-shape between the welding parts 3 in each adjacent column or row to ensure that the heat dissipation effect around each welding part 3 is the same, thereby improving the heat dissipation uniformity of the chip body 1.

[0051] like Figure 3 As shown, in one embodiment, the heat dissipation channel 2 is arranged in a grid pattern, and the second through holes 11 on two adjacent chip bodies 1 are located at the diagonal points of the heat dissipation channel 2; the grid-shaped heat dissipation channel 2 forms an isolation region 8, and a soldering part 3 is arranged in each isolation region 8.

[0052] This embodiment is a second arrangement of the heat dissipation channel 2. The heat dissipation channel 2 can separate each welding part 3, so that each welding part 3 is located in an isolation area 8. After the cooling fluid enters from a second through hole 11, it will disperse and flow into the grid-type heat dissipation channel 2, and flow from multiple directions to another second through hole 11 at the diagonal point, and enter the next layer of heat dissipation channel 2 through this second through hole 11. The flow direction of the cooling fluid in the multi-layer heat dissipation channel 2 can be from top to bottom or from bottom to top.

[0053] like Figure 4 As shown, in one embodiment, the heat dissipation channel 2 is arranged in a continuous curved pattern, and the second through holes 11 on two adjacent chip bodies 1 are located at the two ends of the heat dissipation channel 2 respectively; the heat dissipation channel 2 passes around each solder part 3 in sequence, separating two horizontally adjacent and vertically adjacent solder parts 3.

[0054] This embodiment represents the third arrangement of the heat dissipation channel 2. Two adjacent horizontally and vertically adjacent welding parts 3 can be separated by the heat dissipation channel 2, so that each welding part 3 can be effectively dissipated. Furthermore, the continuous curved arrangement can increase the heat dissipation area of ​​the chip body 1, thereby improving the heat dissipation effect.

[0055] like Figure 7 As shown, in one embodiment, the second flow channel 22 is provided with one or more combinations of a metal layer, a carbon nanotube layer, and a graphene layer.

[0056] Furthermore, the first flow channel 21 is also provided with one or more combinations of metal layer, carbon nanotube layer and graphene layer.

[0057] like Figure 1 As shown, the height of the protrusion 7 corresponds to the height of the welded part 3. Therefore, by selecting a grid-type heat dissipation channel 2 or a heat dissipation channel 2 arranged with a continuous curve, multiple welded parts 3 can be effectively isolated.

[0058] Preferably, a metal layer is disposed in the second flow channel 22; or, a metal layer is disposed in the second flow channel 22, and a carbon nanotube layer or a graphene layer is disposed on the outside of the metal layer; or, a carbon nanotube layer or a graphene layer is disposed in the second flow channel 22.

[0059] The metal layer can be made of copper, aluminum, or silver paste coating, which can absorb the heat of the chip body 1 and has a strong shielding effect; the carbon nanotube layer or graphene layer also has good thermal conductivity and shielding effect; since signal interference is prone to occur between the solder joints 3 between the multilayer chip bodies 1, the metal layer, carbon nanotube layer or graphene layer can isolate each solder joint 3, reduce interference between signals, and ensure the stability of signal transmission. In addition, during soldering, the protrusions 7 can also effectively isolate adjacent solder joints 3, prevent adjacent solder joints 3 from contacting each other, and ensure the stability of soldering.

[0060] Adding a carbon nanotube layer or graphene layer outside the metal layer further improves the heat dissipation of the chip body 1 and enhances the shielding effect on the adjacent solder joints 3.

[0061] like Figure 5 and Figure 6 As shown, in one embodiment, the chip body 1 is provided with a first through hole, and a conductive part 12 is provided in the first through hole;

[0062] The welding part 3 includes a welding body 4 and a conductor 5; in two adjacent chip bodies 1, the bottom of the upper chip body 1 is provided with a welding body 4, which is connected to the conductor 12, and the top of the lower chip body 1 is provided with a conductor 5, which is connected to the conductor 12.

[0063] The top surface of conductor 5 is recessed.

[0064] The solder body 4 can be a solder ball, and the conductor 5 can be a conductive block made of metal. The solder body 4 and the conductor 5 can be welded together by vacuum reflow soldering to form a welded part 3. During the welding process, the solder body 4 melts and comes into contact with the conductor 5. After cooling, the two are welded together to form the welded part 3. When the heat dissipation channel 2 is arranged in a grid or continuous curve, the protrusion 7 can isolate adjacent solder bodies 4, thereby preventing adjacent solder bodies 4 from contacting due to insufficient distance. In order to further limit the flow of the solder body 4 to the periphery after melting, the top surface of the conductor 5 is set as a concave shape with a low center and a high edge. When the solder body 4 and the conductor 5 are welded, the melted solder body 4 will not flow to the periphery, thus limiting its flow and ensuring the stability of the welding. In addition, multiple particles or protrusions can be formed on the concave surface to facilitate a firm weld with the solder body 4.

[0065] like Figure 1 and Figure 5As shown, in one embodiment, a connection layer 6 is provided between two adjacent chip bodies 1. The connection layer 6 is provided with a first clearance area 61 corresponding to the welding part 3 and a second clearance area 62 corresponding to the protrusion 7. The thickness of the connection layer 6 is set to correspond to the height of the protrusion 7.

[0066] The bonding layer 6 can be a semi-cured film layer with adhesive properties, such as epoxy resin, and the thickness of the bonding layer 6 corresponds to the height of the protrusion 7.

[0067] The connecting layer 6 can be first bonded or coated onto the bottom surface of the upper chip body 1, and then form a first clearance area 61 and a second clearance area 62 at the corresponding positions of the soldering part 3 and the protrusion 7. When stacking the chip bodies 1, the conductor 5 is inserted into the first clearance area 61 and the protrusion 7 is inserted into the second clearance area 62, specifically as follows: Figure 5 As shown, the conductor 5 and the weld 4 will be welded within the first clearance area 61, further preventing the weld 4 from flowing to the surrounding area after melting. The connecting layer 6 formed after heating and solidification seals the sides of the first flow channel 21 and the second flow channel 22, thereby forming a heat dissipation channel 2 and ensuring the sealing of the heat dissipation channel 2.

[0068] When the welded part 3 is formed by vacuum reflow soldering, heating will cause the upper and lower surfaces of the semi-cured connecting layer 6 to connect with the two chip bodies 1 respectively. The connecting layer 6 is formed by heating and curing.

[0069] like Figures 8-11 As shown, the present invention also provides a packaging method for a chip stacking structure, comprising:

[0070] Prepare two adjacent chip bodies 1, and make a first flow channel groove 21 at the bottom of the upper chip body 1 and a second flow channel groove 22 at the top of the lower chip body 1.

[0071] In two adjacent chip bodies 1, a connecting layer 6 is formed on the bottom surface of the upper chip body 1, and a first clearance area 61 and a second clearance area 62 are formed on the connecting layer 6; wherein, the first clearance area 61 is formed at the corresponding position of the conductive part 12 of the chip body 1, and the second clearance area 62 is formed at the corresponding position of the first flow channel groove 21.

[0072] In two adjacent chip bodies 1, a solder body 4 is made on the bottom surface of the upper chip body 1 so that the solder body 4 is connected to the conductive part 12, and a conductive body 5 is soldered on the top surface of the conductive part 12 of the lower chip body 1.

[0073] The multi-layer chip body 1 is stacked, pressure is applied to the top of the multi-layer chip body 1, and the solder body 4 is soldered to the conductor 5 through a vacuum reflow process. The two adjacent chip bodies 1 are connected through the connecting layer 6.

[0074] like Figure 8 As shown, a protrusion 7 is first fabricated on the chip body 1, then a first through hole and a second through hole are fabricated. A conductive part 12 is formed in the first through hole. After two adjacent chip bodies 1 are prepared, a first flow channel 21 and a second flow channel 22 are fabricated respectively; as shown... Figure 9 As shown, a bonding layer 6 is then fabricated on the bottom surface of the upper chip body 1. For example, a semi-cured bonding layer 6 can be fabricated using a dry film method or a coating process; Figure 10 As shown, a first avoidance area 61 and a second avoidance area 62 are created on the connection layer 6; as Figure 11 As shown, a solder body 4 is fabricated at the bottom of the upper chip body 1, for example, by implanting solder balls to connect the solder balls to the conductive part 12. A conductor 5 is fabricated at the top of the lower chip body 1, for example, by soldering the metal conductor 5 to the conductive part 12. Then, the multiple layers of chip bodies 1 are stacked as shown. Figure 5 In the state shown, the conductor 5 and the protrusion 7 are inserted into the first clearance area 61 and the second clearance area 62 respectively. Pressure is applied to the top of the multilayer chip body 1. The solder 4 located above is melted and combined with the conductor 5 through the vacuum reflow process. The connecting layer 6 is heated and solidified to connect the two adjacent chip bodies 1 together.

[0075] When the conductor 5 and the solder 4 are soldered, they can be done within the first clearance area 61, and the top of the conductor 5 is recessed to prevent the solder 4 from flowing to the surroundings after melting. The connecting layer 6 can seal the contact edge between the top surface of the protrusion 7 and the bottom surface of the upper chip body 1 to form a heat dissipation channel 2. The connecting layer 6 can isolate each solder part 3.

[0076] Furthermore, after fabricating the second flow channel 22 on the top of the lower chip body 1, the process further includes: forming a metal layer in the second flow channel 22 using an electroplating process, or forming a carbon nanotube layer or a graphene layer in the second flow channel 22 using a spraying process.

[0077] The metal layer can be made of copper, aluminum, or silver paste coating, which can absorb the heat of the chip body 1 and has a strong shielding effect; the carbon nanotube layer or graphene layer also has good thermal conductivity and shielding effect.

[0078] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0079] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0080] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the present invention, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A chip stacking structure, characterized in that, include: At least two chip bodies (1) are provided, and two adjacent chip bodies (1) are electrically connected by a soldering part (3). A heat dissipation channel (2) is provided between two adjacent chip bodies (1), and the heat dissipation channel (2) between any two adjacent chip bodies (1) is connected. The heat dissipation channel (2) includes: a first channel groove (21) and a second channel groove (22); in two adjacent chip bodies (1), the bottom of the upper chip body (1) is provided with a first channel groove (21), and the top of the lower chip body (1) is provided with a protrusion (7), and the protrusion (7) is provided with a second channel groove (22). The chip body (1) is also provided with a second through hole (11), and the second through hole (11) of the upper chip body (1) and the second through hole (11) of the lower chip body (1) are connected through a heat dissipation channel (2).

2. The chip stacking structure according to claim 1, characterized in that, The heat dissipation channel (2) is arranged in an S-shape, and the second through holes (11) on the two adjacent chip bodies (1) are located at the two ends of the heat dissipation channel (2); the heat dissipation channel (2) can separate two adjacent horizontally or vertically adjacent solder parts (3).

3. The chip stacking structure according to claim 1, characterized in that, The heat dissipation channel (2) is arranged in a grid pattern, and the second through holes (11) on two adjacent chip bodies (1) are located at the diagonal points of the heat dissipation channel (2); the grid-type heat dissipation channel (2) forms an isolation area (8), and a soldering part (3) is arranged in each isolation area (8).

4. The chip stacking structure according to claim 1, characterized in that, The heat dissipation channel (2) is arranged in a continuous curve, and the second through holes (11) on the two adjacent chip bodies (1) are located at the two ends of the heat dissipation channel (2); the heat dissipation channel (2) passes around each solder part (3) in sequence, separating the two adjacent solder parts (3) in the horizontal and vertical directions.

5. The chip stacking structure according to claim 1, characterized in that, The second flow channel (22) is provided with one or more combinations of a metal layer, a carbon nanotube layer and a graphene layer.

6. The chip stacking structure according to claim 1, characterized in that, The chip body (1) is provided with a first through hole, and a conductive part (12) is provided in the first through hole; The welding part (3) includes a welding body (4) and a conductor (5); in two adjacent chip bodies (1), the bottom of the upper chip body (1) is provided with a welding body (4), which is connected to the conductor (12), and the top of the lower chip body (1) is provided with a conductor (5), which is connected to the conductor (12).

7. The chip stacking structure according to claim 1, characterized in that, A connecting layer (6) is provided between two adjacent chip bodies (1). The connecting layer (6) has a first clearance area (61) corresponding to the welding part (3) and a second clearance area (62) corresponding to the protrusion (7). The thickness of the connecting layer (6) is set to correspond to the height of the protrusion (7).

8. A packaging method for a chip stacking structure, used to package the chip stacking structure according to any one of claims 1-7, characterized in that, include: Prepare two adjacent chip bodies (1), make a first flow channel groove (21) at the bottom of the upper chip body (1), and make a second flow channel groove (22) at the top of the lower chip body (1); In two adjacent chip bodies (1), a connecting layer (6) is formed on the bottom surface of the upper chip body (1), and a first clearance area (61) and a second clearance area (62) are formed on the connecting layer (6); wherein, the first clearance area (61) is formed at the corresponding position of the conductive part (12) of the chip body (1), and the second clearance area (62) is formed at the corresponding position of the first flow channel groove (21); In two adjacent chip bodies (1), a solder body (4) is made on the bottom surface of the upper chip body (1) so that the solder body (4) is connected to the conductive part (12), and a conductive body (5) is soldered on the top surface of the conductive part (12) of the lower chip body (1). The multi-layer chip bodies (1) are stacked and pressure is applied to the top of the multi-layer chip bodies (1). The solder body (4) is soldered to the conductor (5) by vacuum reflow process. The two adjacent chip bodies (1) are connected by the connecting layer (6).

9. The packaging method for a chip stacked structure according to claim 8, characterized in that, After fabricating the second flow channel groove (22) on top of the lower chip body (1), the process further includes: forming a metal layer in the second flow channel groove (22) using an electroplating process, or forming a carbon nanotube layer or a graphene layer in the second flow channel groove (22) using a spraying process.

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