Metastable state error field correction circuit of successive approximation analog-to-digital converter

Abstract

A metastable error field correction circuit of a successive approximation type analog-to-digital converter comprises a NOR gate and a NAND gate which form an error correction module, and a NOR gate, a trigger and a delay unit which form an error detection module, wherein the logic input ends of the NOR gate and the NAND gate of the error correction module are connected with the output end of a comparator of the analog-to-digital converter to be detected, and the logic output ends of the NOR gate and the NAND gate are respectively output to the NOR gate of the error detection module so as to obtain a judgment signal for judging whether a metastable state phenomenon occurs or not; the trigger generates an error pre-calibration signal according to the judgment signal and a clock signal of a comparator of the analog-to-digital converter to be tested; and the delay unit generates a pair of mutually inverted error correction signals according to the judgment signal and the error pre-calibration signal of the trigger, outputs the error correction signals to the NOR gate and the NAND gate of the error correction module to generate corrected signals, and outputs the corrected signals to the latch. On-site correction is carried out on errors caused by the metastable state of the comparator, it can be determined that the errors are smaller than an acceptable range, and errors do not occur in forced setting, so that the reliability of the ADC is remarkably improved, and it is ensured that the ADC can still keep high precision and stability under variable input conditions.

Description

Technical Field

[0001] The present invention relates to a technology in the field of analog-to-digital conversion, specifically a metastable error in-situ correction circuit for a successive approximation analog-to-digital converter. Background Art

[0002] Metastability refers to a phenomenon in which, during the transition process of a circuit, the output may fluctuate between two logic levels and cannot determine its final output state within a certain period of time. When the input of a comparator approaches its decision threshold, the output may be unstable between the high and low states, resulting in uncertainty. Errors caused by metastability are difficult to calibrate like other errors in the ADC transfer function, which may lead to output errors and performance degradation. Existing methods can only detect metastability or correct errors caused by metastability through additional backend coding logic in synchronous ADCs. Summary of the Invention

[0003] Aiming at the problems that existing analog-to-digital converters cannot directly correct the bits where metastable errors occur, cannot determine which bit in a SAR cycle the metastable error appears, and cannot determine whether the remaining error at the end of SAR is less than the acceptable range, which easily leads to potential conversion errors, the present invention proposes a metastable error in-situ correction circuit for a successive approximation analog-to-digital converter, which can perform in-situ correction for errors caused by comparator metastability, determine that the error is less than the acceptable range, and forced setting will not cause errors, thereby significantly improving the reliability of the ADC and ensuring its high precision and stability under changing input conditions.

[0004] The present invention is realized through the following technical solutions:

[0005] The present invention relates to a metastable error in-situ correction circuit for a successive approximation analog-to-digital converter, including: a NOR gate and a NAND gate constituting an error correction module, and a NOR gate, a flip-flop, and a delay unit constituting an error detection module, wherein: the logical input terminals of the NOR gate and the NAND gate of the error correction module are connected to the output terminal of the comparator of the analog-to-digital converter to be measured, and the logical output terminals of the NOR gate and the NAND gate are respectively output to the NOR gate of the error detection module to obtain a decision signal on whether metastability occurs. The flip-flop generates an error pre-calibration signal respectively according to the decision signal and the clock signal of the comparator of the analog-to-digital converter to be measured. The delay unit generates a pair of mutually inverted error correction signals according to the decision signal and the error pre-calibration signal of the flip-flop and outputs them to the NOR gate and the NAND gate of the error correction module to generate a corrected signal and then output it to the latch. Technical Effects

[0006] The present invention generates a fixed detection time window through a comparator clock and a delay unit, and uses the error correction signal generated by the delay unit to forcibly set the outputs of the NOR gate and NAND gate of the error correction module to generate an output result and skip the comparison process of this data bit, enabling the asynchronous successive approximation logic to continue. Compared with the prior art, the present invention can effectively eliminate errors caused by metastability. If metastability does not occur, the correction process will not affect the normal SAR operation, thus ensuring the reliability and stability of the system in high-speed and high-precision applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of the circuit of the present invention;

[0008] Figure 2 is Figure 1 a timing diagram. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0009] As Figure 1 shown, this embodiment relates to a metastable error in-situ correction circuit for a successive approximation analog-to-digital converter, including: a NOR gate and a NAND gate that constitute an error correction module, and a NOR gate, a D flip-flop, and a delay unit that constitute an error detection module, where: the logical input terminals of the NOR gate and NAND gate of the error correction module are connected to the output terminal of the comparator of the analog-to-digital converter to be measured, and the logical output terminals of the NOR gate and NAND gate are respectively output to the NOR gate of the error detection module to obtain a decision signal cmp_finish on whether metastability occurs. The clock signal clk_cmp of the comparator of the analog-to-digital converter to be measured is used as the clock signal of the D flip-flop, the decision signal cmp_finish is used as the reset signal of the D flip-flop, the positive power supply is used as the D input signal of the D flip-flop, and the output terminal Q of the D flip-flop outputs an error pre-calibration signal meta_pre. The delay unit generates mutually opposite error correction signals meta_pos and meta_neg according to the error pre-calibration signal meta_pre and the decision signal cmp_finish. The error correction signal meta_pos and the comparator output D OUTORI generate a corrected signal D after passing through the NOR gate OUT+ and output it to the latch of the CDAC. The error correction signal meta_neg and the comparator output D OUTORI generate a corrected signal D after passing through the NAND gate OUT- and output it to the latch of the CDAC.

[0010] When the decision signal cmp_finish is low, the error pre-calibration signal meta_pre is reset to 0. When the decision signal cmp_finish is high, the error pre-calibration signal meta_pre will become 1 at the first rising edge of clk_cmp.

[0011] When the decision signal cmp_finish is low, the error correction signals meta_pos is reset to 0 and meta_neg is reset to 1; when the decision signal cmp_finish is high, the error correction signal meta_pos is the signal after the delay of the error pre-calibration signal meta_pre.

[0012] The initial state of the clock signal clk_cmp is 0, and the initial state of the comparator output D OUTORI is 1 / 1, the initial state of the decision signal cmp_finish is 1, and the initial states of the error correction signals meta_pos and meta_neg are 0 and 1 respectively.

[0013] The ratio of the NMOS and PMOS transistors in the output stage of the comparator needs to be set so that the driving ability of the PMOS is stronger than that of the NMOS, ensuring that the comparator output D OUTORI is more likely to be pulled to the high level, thus avoiding the state of 0 / 0 of the comparator output D OUTORI during the operation of the comparator.

[0014] As Figure 2 shown, it is the timing of the error in-situ correction technology caused by metastability. When the rising edge of the comparator clock clk_cmp arrives, while the comparator starts to compare, the D flip-flop in the error detection module is also triggered, and the output flips from 0 to 1. This signal is transmitted through the delay unit. The time range for metastability detection is t meta , when the comparator exhibits metastability, that is, within t meta no definite output result is generated, the decision signal cmp_finish remains high all the time, the delay unit is not reset, the positive error correction signal meta_pos is pulled high, forcing the NOR gate output D OUT+ to be pulled to 0; the inverted error correction signal meta_neg is pulled low, forcing the NAND gate output D OUT- to be pulled to 1. Therefore, cmp_finish becomes 0, resetting the D flip-flop and the delay unit, meta_pos becomes 0 again, and meta_neg becomes 1 again, waiting for the comparison in the next cycle. These operations effectively eliminate the metastability problem.

[0015] When the comparator does not exhibit metastability, that is, a definite output result is generated within the metastability detection time t meta , the decision signal cmp_finish will become 0, resetting the D flip-flop and the delay unit. meta_pos will remain 1, and meta_neg will remain 0, which will not affect the normal SAR operation.

[0016] After specific actual experiments, the output results of the ADC are continuously detected multiple times for 227 For these data points, there will be no obvious deterioration in the spectrum performance, that is, no metastability problem occurs, which can prove the high overall reliability of the ADC. In summary, the present invention can perform real-time correction when the ADC is working normally, can process the metastability problem in real time, improves the overall reliability of the system, and ensures the output stability of the ADC under different working conditions. Through simple logical assignment operations, the present invention can effectively eliminate the uncertainty brought by metastability without complex backend coding logic, and this simplification makes the design more efficient.

[0017] Those skilled in the art can make local adjustments to the above specific embodiments in different ways without departing from the principles and purposes of the present invention. The protection scope of the present invention is subject to the claims and is not limited by the above specific embodiments, and all implementation solutions within its scope are subject to the present invention.

Claims

1. A metastable error field correction circuit for a successive approximation analog-to-digital converter, characterized in that Including: An NOR gate, a NAND gate that constitute an error correction module, an NOR gate, a flip-flop, and a delay unit that constitute an error detection module, where: The logical input terminals of the NOR gate and the NAND gate of the error correction module are connected to the output terminal of the comparator of the analog-to-digital converter to be measured. The logical output terminals of the NOR gate and the NAND gate are respectively output to the NOR gate of the error detection module to obtain a decision signal on whether a metastable state phenomenon occurs. The flip-flop generates an error pre-calibration signal according to the decision signal and the clock signal of the comparator of the analog-to-digital converter to be measured. The delay unit generates a pair of mutually inverted error correction signals according to the decision signal and the error pre-calibration signal of the flip-flop and outputs them to the NOR gate and the NAND gate of the error correction module to generate a corrected signal and then output it to the latch.

2. The metastable error site correction circuit of the successive approximation type analog-to-digital converter according to claim 1, characterized in that, The initial states of the clock signal, the positive-phase and negative-phase error correction signals are 0 and 1 respectively.

3. The metastable error field correction circuit of the successive approximation type analog-to-digital converter according to claim 1, characterized in that, The ratio of NMOS and PMOS transistors in the output stage of the comparator needs to be set such that the PMOS size is stronger to ensure that the comparator output does not appear in the 0 / 0 state during the operation of the comparator.

4. The metastable error field correction circuit of the successive approximation type analog-to-digital converter according to claim 1, characterized in that, The flip-flop is a D flip-flop.

5. A calibration method for the circuit according to any one of claims 1-4, characterized in that When the rising edge of the comparator clock arrives and the comparator starts to compare, the flip-flop in the error detection module is triggered and the output flips from 0 to 1. When the comparator does not produce a clear output result within the time range of metastable state detection, that is, a metastable state phenomenon occurs, the decision signal is always at a high level, that is, the delay unit is not reset. The positive-phase error correction signal is pulled high, forcing the output of the NOR gate to 0; the negative-phase error correction signal is pulled low, forcing the output of the NAND gate to 1. The decision signal becomes 0, resetting the flip-flop and the delay unit. The positive-phase error correction signal becomes 0 again, and the negative-phase error correction signal becomes 1 again, waiting for the next cycle of comparison to eliminate the metastable state.

6. The calibration method according to claim 5, characterized in that, When the comparator does not have a metastable state phenomenon, that is, a clear output result is produced within the metastable state detection time, the decision signal will become 0, resetting the flip-flop and the delay unit. The positive-phase error correction signal will remain at 1, and the negative-phase error correction signal will remain at 0.

Images