Active region structure, shield gate trench type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and preparation method

Abstract

The invention discloses an active region structure, a shield gate trench type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a preparation method, and relates to the technical field of power semiconductor chip manufacturing, the active region structure comprises gate polycrystalline silicon and a body region, and the gate polycrystalline silicon comprises first gate polycrystalline silicon and second gate polycrystalline silicon; the plurality of first grid polycrystalline silicon and the plurality of second grid polycrystalline silicon are parallel to each other and are distributed at intervals; the first grid polycrystalline silicon is connected with the grid metal, and the second grid polycrystalline silicon is connected with the source metal; two adjacent pieces of grid polycrystalline silicon are connected through a body region; the body region is divided into a plurality of low Vth regions and high Vth regions which are distributed at intervals in a staggered manner along the length direction; the doping concentration of the high Vth region is greater than the doping concentration of the low Vth region. According to the invention, the second grid polycrystalline silicon is connected to the source metal, the channel width of the device on the same chip is effectively reduced, and the high Vth region array of the long channel is integrated to the active region of the device, so that the drain current zero temperature coefficient point in the transmission characteristic of the MOSFET is reduced, and the SOA performance of the device is effectively enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor chip manufacturing, and particularly to an active region structure, a shielded gate trench MOSFET structure and a preparation method thereof. Background Art

[0002] As an advanced power MOSFET device technology, the shielded gate trench MOSFET device is widely used in application fields with high requirements for linear mode performance such as power systems (for example, hot plug), electronic fuses, and automobiles because of its advantages such as fast switching speed, low power consumption, easy gate driving, small driving power, and fast frequency response.

[0003] The shielded gate trench MOSFET device reduces the gate-drain overlap area of the MOSFET device by introducing a shielded gate electrode, reduces the gate-drain capacitance, achieves the improvement of the switching speed, reduces the dynamic loss of the MOSFET device, and at the same time increases the cell density and reduces the on-resistance. However, due to factors such as chip area, cell design, and packaging performance, it is determined that the power MOSFET device has an energy range in which the drain-source voltage and drain current can be safely processed, that is, the SOA (Safe Operating Aera). With the continuous change and development of the application environment of the MOSFET device, on the one hand, it is required that the power MOSFET device has lower on-resistance loss; on the other hand, it is required that the power MOSFET device can work under high voltage and large current for a longer time, that is, it is required that the MOSFET device has a larger SOA.

[0004] The existing shielded gate trench MOSFET device has excellent device performance due to its excellent specific on-resistance and low FOM (Figure of Merit), but its SOA performance is poor. Summary of the Invention

[0005] The present invention provides an active region structure, a shielded gate trench MOSFET structure and a preparation method thereof, which solve the problem of poor SOA performance of the existing shielded gate trench MOSFET device.

[0006] To achieve the above object, the present invention adopts the following technical solutions: In a first aspect, the present invention provides an active region structure, including gate polysilicon and a body region; The gate polysilicon includes a plurality of first gate polysilicons and a plurality of second gate polysilicons; the plurality of first gate polysilicons and the plurality of second gate polysilicons are parallel to each other and are distributed at intervals; the first gate polysilicon is used to connect with a gate metal, and the second gate polysilicon is used to connect with a source metal; Adjacent two gate polysilicons are connected through the body region; The body region is divided along the length direction into a plurality of low-Vth regions and high-Vth regions which are alternately distributed at intervals; the doping concentration of the high-Vth region is greater than that of the low-Vth region.

[0007] In a possible implementation manner, the low-Vth region is the region in the body region where a single ion implantation operation is performed, and the high-Vth region is the region in the body region where two ion implantation operations are performed.

[0008] In a possible implementation manner, the interval between two adjacent high-Vth regions is greater than 0.2 μm and less than 1 μm.

[0009] In a possible implementation manner, the second gate polysilicon is arranged with one or more of the first gate polysilicons intervening therebetween.

[0010] In a second aspect, the present invention provides a shielded-gate trench MOSFET structure, including a substrate, an epitaxial layer, a shielded polysilicon lead-out region, and the active region structure according to any one of the above, and further including an inner pad oxide layer, shielded polysilicon, a gate oxide layer, a source ion implantation layer, a low-temperature oxide layer, and a borophosphosilicate glass layer; The epitaxial layer is grown on the upper surface of the substrate; The surface of the epitaxial layer is sequentially divided along the length direction into the active region structure and the shielded polysilicon lead-out region; A plurality of active region trenches included in the active region structure, and a plurality of shielded lead-out region trenches included in the shielded polysilicon lead-out region all extend into the interior of the epitaxial layer along the depth direction; the inner pad oxide layer and the shielded polysilicon are sequentially stacked in the lower half of the active region trench and in the shielded lead-out region trench, and the gate oxide layer and gate polysilicon are sequentially stacked in the upper half of the active region trench; the active region trench provided with the first gate polysilicon is the first trench, and the active region trench provided with the second gate polysilicon is the second trench, and the first trench and the second trench are distributed at intervals; A body region and the source ion implantation layer are sequentially stacked outside the upper half of the active region trench and the shielded lead-out region trench in the epitaxial layer; the body region of the active region structure includes a plurality of low-Vth regions and high-Vth regions which are alternately distributed at intervals, and the body region of the shielded polysilicon lead-out region includes a low-Vth region; The low-temperature oxide layer and the borophosphosilicate glass layer are sequentially stacked on the top of the source ion implantation layer.

[0011] In a possible implementation manner, a second contact hole, a first contact hole, and a third contact hole which are vertically arranged from the borophosphosilicate glass layer to the body region are further included; The second contact hole is located within the active region structure and is used to connect to the source metal located outside the borophosphosilicate glass layer; The first contact hole is located within the active region structure and is used to connect the source metal to the second gate polysilicon within the second trench; the first gate polysilicon within the first trench is connected to the gate metal by means of an external lead; The third contact hole is located within the shield polysilicon lead-out region and is used to connect the source metal to the shield polysilicon within the shield lead-out region trench.

[0012] In a possible implementation, the second trench is arranged with a spacing of one or more of the first trenches.

[0013] In a third aspect, the present invention provides a method for manufacturing a shield-gate trench MOSFET structure, the method comprising: In combination with a first mask plate, the active region trench and the shield lead-out region trench are etched inward along the depth direction on the surface of the epitaxial layer; The first mask plate is removed, and an inner pad oxide layer is formed on the upper surfaces of the active region trench, the shield lead-out region trench, and the epitaxial layer; On top of the inner pad oxide layer within the active region trench and the shield lead-out region trench, the shield polysilicon is deposited and formed, and the upper surface of the shield polysilicon is flush with the top opening of the shield lead-out region trench; In combination with a second mask plate, the inner pad oxide layer and the shield polysilicon in the upper half of the active region trench are etched away; On the inner sidewalls of the upper half of the active region trench and the top of the shield polysilicon, on the upper surface of the epitaxial layer, and on the upper surface of the shield polysilicon in the shield lead-out region trench, the gate oxide layer is formed; On top of the gate oxide layer in the upper half of the active region trench, the gate polysilicon is deposited; In combination with a third mask plate, in the upper part of the epitaxial layer and outside the active region trench and the shield lead-out region trench, through two body region ion implantations, a body region composed of the low Vth region and the high Vth region is obtained; In combination with a fourth mask plate, source ion implantation is performed above the body region to obtain the source ion implantation layer; The fourth mask plate is removed, the low-temperature oxide layer is deposited on top of the gate oxide layer, and the borophosphosilicate glass layer is provided on top of the low-temperature oxide layer.

[0014] In a possible implementation, in combination with a third mask plate, a body region composed of a low Vth region and a high Vth region is obtained by two body region ion implantations above the epitaxial layer and on the outer peripheries of the active region trench and the shield lead-out region trench, specifically including: Protect the low Vth region using the third mask plate, and perform the first body region ion implantation above the epitaxial layer and on the outer peripheries of the active region trench and the shield lead-out region trench; Remove the third mask plate, and perform the second body region ion implantation above the epitaxial layer and on the outer peripheries of the active region trench and the shield lead-out region trench to obtain a body region composed of the low Vth region and the high Vth region.

[0015] In a possible implementation, in combination with a third mask plate, a body region composed of a low Vth region and a high Vth region is obtained by two body region ion implantations above the epitaxial layer and on the outer peripheries of the active region trench and the shield lead-out region trench, specifically including: Perform the first body region ion implantation above the epitaxial layer and on the outer peripheries of the active region trench and the shield lead-out region trench; Protect the low Vth region using the third mask plate, and perform the second body region ion implantation above the epitaxial layer and on the outer peripheries of the active region trench and the shield lead-out region trench to obtain a body region composed of the low Vth region and the high Vth region.

[0016] The active region structure provided by the embodiment of the present invention is applied to a shield gate trench MOSFET device. This structure connects the second gate polysilicon in the gate polysilicon to the source metal, effectively reducing the channel width of the devices on the same chip, integrating the high Vth region array with long channels into the active region of the device, thereby reducing the drain current zero temperature coefficient point in the MOSFET transmission characteristics and effectively enhancing the SOA performance of the device.

[0017] In the shield gate trench MOSFET structure provided by the embodiment of the present invention, the gate polysilicon of some cells is connected to the source metal, effectively reducing the channel width of the devices on the same chip; through two ion implantation operations, low Vth regions and high Vth regions are formed to be distributed alternately at intervals, effectively enhancing the SOA performance of the device.

[0018] The preparation method of the shield gate trench MOSFET structure provided by the embodiment of the present invention has a simple process and can be compatible with the manufacturing process of traditional MOSFET devices. Description of the Drawings

[0019] Figure 1 It is a schematic structural diagram of an active region structure provided by the embodiment of the present invention; Figure 2 The cross-section along the Figure 1 AB direction in the figure, after using a photomask to protect part of the body region, a schematic diagram of the first ion implantation operation to form a high-Vth region; Figure 3 The doping simulation diagram after the first ion implantation operation; Figure 4 The cross-section along the Figure 1 AB direction in the figure, after removing the photomask, a schematic diagram of the second ion implantation operation to form a high-Vth region and a low-Vth region; Figure 5 The doping simulation diagram after the second ion implantation operation; Figure 6 The doping concentration distribution simulation diagram from Figures 2 to 4 ; Figure 7 The doping concentration distribution curve diagram of the high-Vth region and the low-Vth region; Figure 8 A schematic diagram of the structure of a shielded-gate trench MOSFET structure provided by an embodiment of the present invention along the Figure 1 CD direction cross-section in the figure; Figure 9 A step flow chart of a preparation method of a shielded-gate trench MOSFET structure provided by an embodiment of the present invention; Figure 10 A process profile schematic diagram of generating an epitaxial layer on the upper surface of a substrate in a preparation method of a shielded-gate trench MOSFET structure provided by an embodiment of the present invention; Figure 11 A process profile schematic diagram of etching active region trenches and shielded lead-out region trenches in the epitaxial layer in a preparation method of a shielded-gate trench MOSFET structure provided by an embodiment of the present invention; Figure 12 A process profile schematic diagram of forming an inner pad oxide layer in a preparation method of a shielded-gate trench MOSFET structure provided by an embodiment of the present invention; Figure 13 A process profile schematic diagram of etching away the inner pad oxide layer and shielded polysilicon on the upper half of the active region trench in a preparation method of a shielded-gate trench MOSFET structure provided by an embodiment of the present invention; Figure 14 A process profile schematic diagram of forming a gate oxide layer in a preparation method of a shielded-gate trench MOSFET structure provided by an embodiment of the present invention; Figure 15 A process profile schematic diagram of depositing gate polysilicon above the gate oxide layer in a preparation method of a shielded-gate trench MOSFET structure provided by an embodiment of the present invention; Figure 16 Process profile schematic diagram when forming a body region composed of a low Vth region and a high Vth region through two body region ion implantations in a method for manufacturing a shielded gate trench MOSFET structure provided by an embodiment of the present invention; Figure 17 Process profile schematic diagram for forming a source ion implantation layer in a method for manufacturing a shielded gate trench MOSFET structure provided by an embodiment of the present invention; Figure 18 Process profile schematic diagram for forming a low-temperature oxide layer and a borophosphosilicate glass layer in a method for manufacturing a shielded gate trench MOSFET structure provided by an embodiment of the present invention; Figure 19 Process profile schematic diagram for forming a second contact hole, a first contact hole, and a third contact hole in a method for manufacturing a shielded gate trench MOSFET structure provided by an embodiment of the present invention; Figure 20 Process profile schematic diagram for forming a source metal connected to a second gate polysilicon in a method for manufacturing a shielded gate trench MOSFET structure provided by an embodiment of the present invention.

[0020] Reference numerals and their descriptions: 11. First gate polysilicon; 12. Second gate polysilicon; 21. Low Vth region; 22. High Vth region; 31. Substrate; 32. Epitaxial layer; 33. Active region trench; 331. First trench; 332. Second trench; 34. Shielded lead-out region trench; 35. Inner pad oxide layer; 36. Shielded polysilicon; 37. Gate oxide layer; 38. Source ion implantation layer; 39. Low-temperature oxide layer; 310. Borophosphosilicate glass layer; 311. Second contact hole; 312. First contact hole; 313. Third contact hole; 314. Source metal. Detailed implementation manners

[0021] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0022] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality of" is two or more. Additionally, the use of "based on" or "in accordance with" implies openness and inclusiveness, because a process, step, calculation, or other action "based on" or "in accordance with" one or more of the stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.

[0023] In the prior art, each generation of SGT power MOSFETs has a smaller pitch and a shorter channel, so we need to find new ways to improve the SOA performance of power MOSFETs.

[0024] When a power MOSFET device operates in the linear mode, the device is simultaneously under a high drain voltage and a high drain current, resulting in high power consumption. When the electrothermal stress exceeds a certain critical value, hot spots will appear in local areas of the active region, leading to thermal runaway and destruction of the device.

[0025] Regarding the problem of improving the SOA performance of shield-gate trench power MOSFETs, researchers have conducted studies in aspects such as electrothermal stability, element pitch in the active region, chip size, trench depth, channel length, threshold voltage, and drain current temperature coefficient, integrating superjunction cells in the active region, or connecting a gate drive circuit to the main MOSFET chip. Researchers have found that the higher the drain current temperature coefficient, the more prone the device is to failure, and a long channel and a small channel width will result in a lower drain current temperature coefficient. Therefore, the SOA performance of MOSFET devices can be improved accordingly.

[0026] To solve the problem of poor SOA performance of existing shield-gate trench MOSFET devices, an embodiment of the present invention provides an active region structure, a shield-gate trench MOSFET structure, and a manufacturing method.

[0027] In a first aspect, as Figure 1 shown, an embodiment of the present invention provides an active region structure, including gate polysilicon and a body region.

[0028] The gate polysilicon includes a plurality of first gate polysilicons 11 and a plurality of second gate polysilicons 12.

[0029] Among them, the plurality of first gate polysilicons 11 and the plurality of second gate polysilicons 12 are parallel to each other and are distributed at intervals; the first gate polysilicon 11 is used to connect to the gate metal, and the second gate polysilicon 12 is used to connect to the source metal 314.

[0030] Two adjacent gate polysilicons are connected through a body region.

[0031] The body region is divided along the length direction into a plurality of low-Vth regions 21 and high-Vth regions 22 that are alternately distributed at intervals. The doping concentration of the high-Vth regions 22 is greater than that of the low-Vth regions 21.

[0032] Wherein, Vth is the threshold voltage of the MOSFET device.

[0033] Furthermore, the low-Vth regions 21 are the regions in the body region where a single ion implantation operation has been performed, and the high-Vth regions 22 are the regions in the body region where two ion implantation operations have been performed.

[0034] Furthermore, the interval between two adjacent high-Vth regions 22 is greater than 0.2 μm and less than 1 μm.

[0035] Furthermore, the second gate polysilicon 12 is arranged with one or more first gate polysilicons 11 in between.

[0036] Specifically, it is achieved by combining two ion implantation operations on the body region with a photomask. That is to say, during one of the two ion implantation operations, the photomask is used to cover a part of the body region, so that only a single doping of the body region is performed in the region covered by the photomask, forming the low-Vth regions 21; the regions not covered by the photomask are doped twice in the body region, forming the high-Vth regions 22.

[0037] Taking the example of first using a photomask to block a part of the body region for the first ion implantation operation; then removing the photomask and performing the second ion implantation operation on the body region in the present invention.

[0038] As Figure 2 、 Figure 3 shown, after the first ion implantation operation, the region of the body region covered by the photomask is not implanted with the ions to be doped, and this region is the low-Vth region 21; the region of the body region not covered by the photomask is implanted with the ions to be doped for the first time, and this region is the high-Vth region 22. As Figure 3 shown, it can be seen from the change in the gray value in the figure that after the first ion implantation operation, the color of the high-Vth region is darker, indicating that a certain concentration of ions to be doped has been implanted; the color of the low-Vth region 21 has not changed significantly relative to the substrate, indicating that no ions to be doped have been implanted.

[0039] As Figure 4 、 Figure 5 shown, during the second ion implantation operation, after removing the photomask, the second ion implantation operation is performed on the entire body region. At this time, the low-Vth regions 21 are implanted with the ions to be doped for the first time, and the high-Vth regions 22 are implanted with the ions to be doped for the second time. As Figure 5As shown, it can be seen from the change of the gray value in the figure that after the second ion implantation operation, the color of the high Vth region deepens again, indicating that the ions to be doped are implanted for the second time; the color of the low Vth region 21 deepens relative to the substrate and is lighter than that of the high Vth region, indicating that the ions to be doped are implanted, and the doping concentration of the low Vth region 21 is lower than that of the high Vth region 22.

[0040] In the doping simulation diagram, D represents the distance between two adjacent high Vth regions 22, and 1um > D > 0.2um.

[0041] After performing the above two ion implantation operations, the doping concentration of the high Vth region 22 is significantly greater than that of the low Vth region 21.

[0042] In the embodiment of the present invention, the active region structure can be the active region structure of an N-type MOSFET or the active region structure of a P-type MOSFET.

[0043] As Figure 6 、 Figure 7 shown, in this embodiment, the active region structure of an N-type MOSFET is taken as an example, where Y represents the depth direction of the cross-section along the Figure 1 AB direction in the device simulation, and X represents the length direction. In the figure, A represents that the substrate and epitaxial layer of the device are N-type doped; C1 and C2 represent that the body region part of the device is P-type doped, and C1 represents the high Vth region 22, and C2 represents the low Vth region 21; from Figure 6 it can be seen that along the depth direction from bottom to top, the concentration of N-type doping gradually decreases, and it becomes P-type doping in the body region part. From Figure 7 it can be seen that in the body region part of the device, the doping concentration of the high Vth region 22 is greater than that of the low Vth region 21.

[0044] The active region structure provided by the embodiment of the present invention is applied to a shielded gate trench MOSFET device. This structure connects the second gate polysilicon in the gate polysilicon to the source metal 314, effectively reducing the channel width of the devices on the same chip, integrating the array of high Vth regions 22 with long channels into the active region of the device, thereby reducing the zero temperature coefficient point of the drain current in the MOSFET transmission characteristics and effectively enhancing the SOA performance of the device.

[0045] Second, as Figure 8 shown, the embodiment of the present invention also provides a shielded gate trench MOSFET structure, including a substrate 31, an epitaxial layer 32, a shielded polysilicon 36 lead-out region, and the active region structure in any one of the above.

[0046] The shielded-gate trench MOSFET structure further includes an inner pad oxide layer 35, a shield polysilicon 36, a gate oxide layer 37, a source ion implantation layer 38, a low-temperature oxide layer 39, and a borophosphosilicate glass layer 310.

[0047] The epitaxial layer 32 is grown on the upper surface of the substrate 31.

[0048] The surface of the epitaxial layer 32 is sequentially divided into an active region structure and a shield polysilicon 36 lead-out region along the length direction.

[0049] A plurality of active region trenches 33 included in the active region structure and a plurality of shield lead-out region trenches 34 included in the shield polysilicon 36 lead-out region both extend into the interior of the epitaxial layer 32 along the depth direction.

[0050] Among them, the inner pad oxide layer 35 and the shield polysilicon 36 are sequentially stacked in the lower half of the active region trench 33 and the shield lead-out region trench 34.

[0051] The gate oxide layer 37 and the gate polysilicon are sequentially stacked in the upper half of the active region trench 33.

[0052] The active region trench 33 provided with the first gate polysilicon 11 is the first trench 331, and the active region trench 33 provided with the second gate polysilicon 12 is the second trench 332. The first trench 331 and the second trench 332 are spaced apart.

[0053] Furthermore, the second trench 332 is provided with an interval of one or more first trenches 331.

[0054] A body region and a source ion implantation layer 38 are sequentially stacked outside the upper half of the active region trench 33 and the shield lead-out region trench 34 in the epitaxial layer 32.

[0055] Among them, the body region of the active region structure includes a plurality of low-Vth regions 21 and high-Vth regions 22 that are alternately distributed at intervals, and the body region of the shield polysilicon 36 lead-out region includes a low-Vth region 21.

[0056] A low-temperature oxide layer 39 and a borophosphosilicate glass layer 310 are sequentially stacked on the top of the source ion implantation layer 38.

[0057] Furthermore, the shielded-gate trench MOSFET structure further includes a second contact hole 311, a first contact hole 312, and a third contact hole 313 that are vertically provided from the borophosphosilicate glass layer 310 to the body region.

[0058] Among them, the second contact hole 311 is located in the active region structure and is used to connect the source metal 314 located outside the borophosphosilicate glass layer 310.

[0059] The first contact hole 312 is located within the active region structure and is used to connect the source metal 314 to the second gate polysilicon 12 within the second trench 332; and the first gate polysilicon 11 within the first trench 331 is connected to the gate metal by means of an external lead.

[0060] The third contact hole 313 is located in the shielding polysilicon 36 lead-out region and is used to connect the source metal 314 to the shielding polysilicon 36 within the shielding lead-out region trench 34.

[0061] The present invention integrates a MOSFET structure with a specific wide SOA in the active region of the MOSFET device. This structure connects the gate polysilicon of some of the active region trenches 33 to the source metal 314 to form the second trench 332, and the gate polysilicon of the remaining active region trenches 33 is still connected to the gate metal to form the first trench 331. When arranging the second trenches 332, they can be arranged with one first trench 331 in between, or multiple first trenches 331 in between.

[0062] In one embodiment of the present invention, when the MOSFET device is an N-type MOSFET, its substrate 31 is an N-type heavily doped semiconductor substrate 31, its epitaxial layer 32 is an N-type lightly doped epitaxial layer 32, such as doped with arsenic or phosphorus. The doping of the source ion implantation layer 38 is N-type heavy doping, such as AS implantation. The body region is P-type doped, such as B implantation. The gate polysilicon is N-type heavily doped polysilicon.

[0063] In another embodiment of the present invention, when the MOSFET device is a P-type MOSFET, the doping of the substrate 31, the epitaxial layer 32, the source ion implantation layer 38, and the gate polysilicon in the previous embodiment are all changed to P-type doping, and the doping of the body region is changed to N-type doping.

[0064] Adopting the structure of the present invention can effectively improve the SOA performance of the MOSFET device by more than 200%. For example: in this embodiment, the 100V withstand voltage SPD series MOSFET products of the traditional structure and the structure of the present invention are tested. The SOA of the traditional structure product is 2.8A, and the SOA of the structure product of the present invention is 10.8A.

[0065] In the shielded gate trench type MOSFET structure provided by the embodiment of the present invention, the gate polysilicon of some cells is connected to the source metal 314, effectively reducing the channel width of the devices on the same chip; through two ion implantation operations, low Vth regions 21 and high Vth regions 22 are formed in an alternating and staggered distribution, effectively enhancing the SOA performance of the device.

[0066] Thirdly, as Figure 9 shown, the embodiment of the present invention also provides a manufacturing method for a shielded gate trench type MOSFET structure, and this method includes: Step 401: Combine with the first mask plate, and etch the surface of the epitaxial layer 32 inward along the depth direction to form an active region trench 33 and a shield lead-out region trench 34.

[0067] Specifically, as Figure 10 , Figure 11 shown, after generating an epitaxial layer 32 with a certain thickness on the upper surface of the substrate 31, the regions that do not need to be etched to form trenches are protected by the first mask plate, and then an active region trench 33 and a shield lead-out region trench 34 are formed in the regions not protected by the first mask plate through photolithography or etching processes.

[0068] The bottoms of the active region trench 33 and the shield lead-out region trench 34 are located within the epitaxial layer 32.

[0069] Step 402: Remove the first mask plate, and generate an inner pad oxide layer 35 on the upper surfaces of the active region trench 33, the shield lead-out region trench 34, and the epitaxial layer 32.

[0070] Specifically, as Figure 12 shown, after removing the first mask plate, an inner pad oxide layer 35 is grown on the upper surfaces of the active region trench 33, the shield lead-out region trench 34, and the epitaxial layer 32 through a thermal oxidation process or a method combining thermal oxidation and chemical vapor deposition. The thickness of the inner pad oxide layer 35 can be adjusted according to the device breakdown voltage requirements.

[0071] Step 403: Deposit and generate a shield polysilicon 36 above the inner pad oxide layer 35 in the active region trench 33 and the shield lead-out region trench 34, and the upper surface of the shield polysilicon 36 is flush with the top opening of the shield lead-out region trench 34.

[0072] Specifically, a shield polysilicon 36 is deposited above the inner pad oxide layer 35 in the active region trench 33 and the shield lead-out region trench 34, and the upper surface of the shield polysilicon 36 is made flush with the top opening of the shield lead-out region trench 34.

[0073] Step 404: Combine with the second mask plate, and etch away the inner pad oxide layer 35 and the shield polysilicon 36 in the upper half of the active region trench 33.

[0074] Among them, the second mask plate is the mask for the shield polysilicon 36. As Figure 13 shown, use the mask for the shield polysilicon 36 to etch the shield polysilicon 36 in the active region trench 33 to a set depth, remove the mask for the shield polysilicon 36, and etch the inner pad oxide layer 35 slightly below the surface of the shield polysilicon 36.

[0075] Step 405: Generate a gate oxide layer 37 on the inner sidewalls of the upper half of the active region trench 33, the top of the shield polysilicon 36, the upper surface of the epitaxial layer 32, and the upper surface of the shield polysilicon 36 in the shield lead-out region trench 34.

[0076] Specifically, as Figure 14 shown, on the inner sidewall of the upper half of the active region trench 33, the top of the shield polysilicon 36, the upper surface of the epitaxial layer 32, and the upper surface of the shield polysilicon 36 in the shield lead-out region trench 34, a gate oxide layer 37 is formed by a thermal oxidation process.

[0077] Step 406: Deposit gate polysilicon above the gate oxide layer 37 in the upper half of the active region trench 33.

[0078] Specifically, as Figure 15 shown, deposit gate polysilicon above the gate oxide layer 37 in the active region trench 33, and by chemical mechanical polishing and etching, etch the gate polysilicon to about 0.1 micrometer below the upper surface of the epitaxial layer 32.

[0079] Step 407: Combine with the third mask plate, and perform two body region ion implantations in the upper part of the epitaxial layer 32 and outside the active region trench 33 and the shield lead-out region trench 34 to obtain a body region composed of a low Vth region 21 and a high Vth region 22.

[0080] Among them, the third mask plate is a photomask. As Figure 16 shown, during the two body region ion implantations, use the photomask to cover part of the body region once, and do not use the photomask on the other side. So that the region not covered by the photomask is implanted with ions twice to form the high Vth region 22; the region not covered by the photomask is only implanted with ions once to form the low Vth region 21. And the low Vth region 21 and the high Vth region 22 are distributed alternately at intervals.

[0081] Step 408: Combine with the fourth mask plate, and perform source ion implantation above the body region to obtain a source ion implantation layer 38.

[0082] Specifically, as Figure 17 shown, combine with the fourth mask plate, and perform source ion implantation above the body region to form a source ion implantation layer 38.

[0083] Step 409: Remove the fourth mask plate, deposit a low temperature oxide layer 39 on the top of the gate oxide layer 37, and set a borophosphosilicate glass layer 310 on the top of the low temperature oxide layer 39.

[0084] Specifically, as Figure 18 shown, deposit a low temperature oxide layer 39 on the top of the gate oxide layer 37 above the epitaxial layer 32, and deposit a borophosphosilicate glass layer 310 on the top of the low temperature oxide layer 39.

[0085] Furthermore, as Figure 19As shown, in combination with the contact hole mask, contact holes are etched downward from the top of the borophosphosilicate glass layer 310. Among them, no holes are opened above the first trench 331, and holes are opened above the second trench 332 and the shield lead-out area trench 34.

[0086] Specifically, the contact hole opened above the second trench 332 is the first contact hole 312, which is used to connect the source metal 314 outside the borophosphosilicate glass layer 310 to the second gate polysilicon 12 in the second trench 332.

[0087] The contact hole opened within the active region structure and outside the active region trench 33 is the second contact hole 311.

[0088] The contact hole opened above the shield lead-out area trench 34 is the third contact hole 313, which is used to connect the source metal 314 to the shield polysilicon 36 in the shield lead-out area trench 34.

[0089] Furthermore, as Figure 20 shown, metal layer deposition is performed, and the source metal 314 is formed on the upper surface of the borophosphosilicate glass layer 310 through metal layer lithography. The second gate polysilicon 12 in the second trench 332 is connected to the source metal 314 through the first contact hole 312, and the shield polysilicon 36 in the shield lead-out area trench 34 is connected to the gate metal through the third contact hole 313; the gate metal is not shown in the figure, and the first gate polysilicon 11 in the first trench 331 is connected to the gate metal by means of an external lead.

[0090] Furthermore, in one embodiment of the present invention, in combination with the third mask, two body region ion implantations are performed on the upper part of the epitaxial layer 32 and outside the active region trench 33 and the shield lead-out area trench 34 to obtain a body region composed of a low Vth region 21 and a high Vth region 22, specifically including: Use the third mask to protect the low Vth region 21, and perform the first body region ion implantation on the upper part of the epitaxial layer 32 and outside the active region trench 33 and the shield lead-out area trench 34.

[0091] Remove the third mask, and perform the second body region ion implantation on the upper part of the epitaxial layer 32 and outside the active region trench 33 and the shield lead-out area trench 34 to obtain a body region composed of a low Vth region 21 and a high Vth region 22.

[0092] Furthermore, in another embodiment of the present invention, in combination with the third mask, two body region ion implantations are performed on the upper part of the epitaxial layer 32 and outside the active region trench 33 and the shield lead-out area trench 34 to obtain a body region composed of a low Vth region 21 and a high Vth region 22, specifically including: Above the epitaxial layer 32 and on the outer periphery of the active region trench 33 and the shield extraction region trench 34, a first body region ion implantation is performed. Using the third mask plate to protect the low Vth region 21, above the epitaxial layer 32 and on the outer periphery of the active region trench 33 and the shield extraction region trench 34, a second body region ion implantation is performed to obtain a body region composed of the low Vth region 21 and the high Vth region 22.

[0093] In this embodiment, taking the manufacturing method of an N-type MOSFET as an example, the substrate 31 is an N-type heavily doped semiconductor substrate 31, the epitaxial layer 32 is an N-type lightly doped epitaxial layer 32, and the N-type doping is specifically arsenic or phosphorus doping. The source ion implantation layer 38 uses AS implantation, the body region uses B implantation, and the gate polysilicon uses N-type heavily doped polysilicon.

[0094] The shield gate trench MOSFET structure prepared by the manufacturing method of the present invention connects the second gate polysilicon in the gate polysilicon to the source metal 314. Through two ion implantation operations, the low Vth regions 21 and the high Vth regions 22 are formed to be spaced and staggered, effectively enhancing the SOA performance of the device; the manufacturing method of the present invention has a simple process and is compatible with the manufacturing process of traditional MOSFET devices.

[0095] The shield gate trench MOSFET prepared by the present invention can be widely applied in working fields such as the linear region and hot plug.

[0096] As described above, only the specific embodiments of the present invention are provided, but the protection scope of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. An active region structure includes a gate polysilicon and a body region, and is characterized in that: The gate polysilicon includes a plurality of first gate polysilicons and a plurality of second gate polysilicons; the plurality of first gate polysilicons and the plurality of second gate polysilicons are parallel to each other and are spaced apart; the first gate polysilicon is used to connect to a gate metal, and the second gate polysilicon is used to connect to a source metal; Two adjacent gate polysilicons are connected through the body region; The body region is divided along the length direction into a plurality of low-Vth regions and high-Vth regions that are alternately spaced; the doping concentration of the high-Vth region is greater than that of the low-Vth region.

2. The active region structure according to claim 1, characterized in that The low-Vth region is the region in the body region where a single ion implantation operation is performed, and the high-Vth region is the region in the body region where two ion implantation operations are performed.

3. The active region structure according to claim 1, characterized in that, In each body region, the spacing between two adjacent high-Vth regions is greater than 0.2 μm and less than 1 μm.

4. The active region structure according to claim 1, characterized in that, The second gate polysilicon is provided with an interval of one or more of the first gate polysilicons.

5. Shielded gate trench MOSFET structure, characterized in that It includes a substrate, an epitaxial layer, a shield polysilicon lead-out region, and the active region structure according to any one of claims 1 to 4, and further includes an inner pad oxide layer, a shield polysilicon, a gate oxide layer, a source ion implantation layer, a low-temperature oxide layer, and a borophosphosilicate glass layer; The epitaxial layer is grown on the upper surface of the substrate; The surface of the epitaxial layer is sequentially divided along the length direction into the active region structure and the shield polysilicon lead-out region; A plurality of active region trenches included in the active region structure and a plurality of shield lead-out region trenches included in the shield polysilicon lead-out region both extend along the depth direction into the epitaxial layer; the inner pad oxide layer and the shield polysilicon are sequentially stacked in the lower half of the active region trench and in the shield lead-out region trench, and the gate oxide layer and the gate polysilicon are sequentially stacked in the upper half of the active region trench; the active region trench provided with the first gate polysilicon is a first trench, and the active region trench provided with the second gate polysilicon is a second trench, and the first trench and the second trench are spaced apart; A body region and the source ion implantation layer are sequentially stacked outside the upper half of the active region trench and the shield lead-out region trench in the epitaxial layer; the body region of the active region structure includes a plurality of low-Vth regions and high-Vth regions that are alternately spaced, and the body region of the shield polysilicon lead-out region includes a low-Vth region; The low-temperature oxide layer and the borophosphosilicate glass layer are sequentially stacked on the top of the source ion implantation layer.

6. The shield gate trench MOSFET structure according to claim 5, wherein It further includes a second contact hole, a first contact hole, and a third contact hole that are vertically provided from the borophosphosilicate glass layer to the body region; The second contact hole is located in the active region structure and is used to connect to the source metal located outside the borophosphosilicate glass layer; The first contact hole is located in the active region structure and is used to connect the source metal to the second gate polysilicon in the second trench; the first gate polysilicon in the first trench is connected to the gate metal by an external lead; The third contact hole is located in the shield polysilicon extraction region and is used to connect the source metal to the shield polysilicon in the trench of the shield extraction region.

7. The shielded gate trench MOSFET structure according to claim 5, characterized in that, The second trench is arranged at an interval of one or more of the first trenches.

8. A preparation method of the shield gate trench MOSFET structure according to claim 5, characterized in that, The method includes: Combining with a first mask plate, etching the epitaxial layer surface inward in the depth direction to form the active region trench and the shield extraction region trench; Removing the first mask plate, and generating an inner pad oxide layer on the active region trench, the shield extraction region trench and the upper surface of the epitaxial layer; Depositing and generating the shield polysilicon above the inner pad oxide layer in the active region trench and the shield extraction region trench, and the upper surface of the shield polysilicon is flush with the top opening of the shield extraction region trench; Combining with a second mask plate, etching away the inner pad oxide layer and the shield polysilicon in the upper half of the active region trench; Generating the gate oxide layer on the inner sidewall of the upper half of the active region trench and the top of the shield polysilicon, the upper surface of the epitaxial layer, and the upper surface of the shield polysilicon in the shield extraction region trench; Depositing the gate polysilicon above the gate oxide layer in the upper half of the active region trench; Combining with a third mask plate, in the upper part of the epitaxial layer and outside the active region trench and the shield extraction region trench, through two body region ion implantations, obtaining a body region composed of the low Vth region and the high Vth region; Combining with a fourth mask plate, performing source ion implantation above the body region to obtain the source ion implantation layer; Removing the fourth mask plate, depositing and forming the low-temperature oxide layer on the top of the gate oxide layer, and arranging the borophosphosilicate glass layer on the top of the low-temperature oxide layer.

9. The manufacturing method of the shield gate trench MOSFET structure according to claim 8, characterized in that, The step of combining with a third mask plate, in the upper part of the epitaxial layer and outside the active region trench and the shield extraction region trench, through two body region ion implantations, obtaining a body region composed of the low Vth region and the high Vth region specifically includes: Using the third mask plate to protect the low Vth region, and performing the first body region ion implantation in the upper part of the epitaxial layer and outside the active region trench and the shield extraction region trench; Removing the third mask plate, and performing the second body region ion implantation in the upper part of the epitaxial layer and outside the active region trench and the shield extraction region trench to obtain a body region composed of the low Vth region and the high Vth region.

10. The manufacturing method of the shield gate trench MOSFET structure according to claim 8, characterized in that, The step of combining with a third mask plate, in the upper part of the epitaxial layer and outside the active region trench and the shield extraction region trench, through two body region ion implantations, obtaining a body region composed of the low Vth region and the high Vth region specifically includes: Performing the first body region ion implantation in the upper part of the epitaxial layer and outside the active region trench and the shield extraction region trench; Using the third mask plate to protect the low Vth region, and performing the second body region ion implantation in the upper part of the epitaxial layer and outside the active region trench and the shield extraction region trench to obtain a body region composed of the low Vth region and the high Vth region.

Images