LED chip, LED chip preparation method and light-emitting equipment

Abstract

According to the LED chip, the preparation method of the LED chip and the light-emitting equipment provided by the invention, an atomic-scale metal oxide passivation layer is deposited in a conventional nonmetal oxide passivation layer and an interlayer of an LED chip electrode, so that the adhesiveness among the conventional nonmetal oxide passivation layer, the LED chip electrode and the interlayer is improved, and the reliability of the chip is improved; by combining the chemical characteristics of the non-metal oxide passivation layer and the atomic-scale metal oxide passivation layer, the LED chip has the advantages of acid resistance and alkali resistance, and specifically, the risk of chip electrode exposure can be greatly reduced through the LED chip structure.

Description

Technical Field

[0001] The present invention relates to the technical field of LEDs, and particularly relates to an LED chip, a method for preparing an LED chip, and a lighting device. Background Art

[0002] LED (light Emitting Diode) is a lighting fixture widely used in the world market at present, and has the advantages of small volume, high brightness, low power consumption, less heat generation, long service life, environmental protection, etc., and has a rich variety of colors, and is deeply loved by consumers.

[0003] Among them, the reliability of LEDs is one of the important indicators for evaluating the quality of LEDs that are widely concerned. In order to improve the reliability of LEDs in terms of bonding ability, water vapor intrusion, etc., usually in the chip manufacturing process, SiO2 is deposited on the chip electrode surface by PECVD to protect the chip electrode.

[0004] However, the reliability of traditional single protective film chips is poor. The reasons are as follows: 1) Since SiO2 is a covalent compound and has a different crystal structure from that of metals, the chemical bonding force between the two is weak and the adsorption between the two is poor; 2) SiO2 is an acidic oxide and will undergo a chemical reaction in an alkaline environment, resulting in electrode exposure; 3) The density of SiO2 deposited by PECVD is poor, and there is a problem of water vapor intrusion; 4) Limited by the occurrence mode of PECVD, the passivation layer prepared by this method cannot achieve full coverage of the steps during the production of high aspect ratio LED chips. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide an LED chip, a method for preparing an LED chip, and a lighting device, aiming to protect the LED electrode by using a composite dielectric protective film structure and avoid the problem of LED chip failure caused by electrode exposure due to the single traditional protective film structure.

[0006] The first aspect of the present application provides an LED chip, which includes: a substrate and an epitaxial stack disposed on the surface of the substrate; An electrode disposed on the surface of the epitaxial stack facing away from the substrate; A passivation layer disposed on the surface of the epitaxial stack facing away from the substrate and extending to the side wall of the electrode; the passivation layer includes a first passivation layer and a second passivation layer, the first passivation layer includes a metal oxide passivation layer obtained by ALD deposition, and the second passivation layer includes a non-metal oxide passivation layer.

[0007] Further, the first passivation layer serves as the bottom contact layer of the passivation layer.

[0008] Further, the first passivation layer serves as the top layer of the passivation layer.

[0009] Further, the passivation layer also covers a partial surface of the electrode facing away from the substrate.

[0010] Further, the first passivation layer and / or the second passivation layer covers the surface of the epitaxial stack facing away from the substrate.

[0011] Further, an adhesion layer is further included; The adhesion layer is disposed between the passivation layer and the electrode.

[0012] Further, a groove is provided on the surface of the electrode facing away from the substrate.

[0013] Further, the material of the first passivation layer includes Al2O3.

[0014] Further, the material of the second passivation layer includes one or more of SiO2 and Si3N4.

[0015] Further, the material of the adhesion layer includes Ti.

[0016] Further, the material of the electrode includes Au.

[0017] Further, the epitaxial stack includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer stacked in sequence; the electrode includes a first electrode and a second electrode; the first electrode is electrically connected to the first-type semiconductor layer, and the second electrode is electrically connected to the second-type semiconductor layer.

[0018] Further, the thickness of the first passivation layer is 50 nm to 200 nm, including the end values; the thickness of the second passivation layer is 50 nm to 500 nm, including the end values.

[0019] Further, the thickness of the adhesion layer is 5 Å to 100 Å, including the end values.

[0020] Further, the LED chip is a vertical structure, a horizontal structure, or a flip-chip structure.

[0021] In a second aspect of the present application, a method for manufacturing an LED chip is provided, which is used to manufacture the LED chip described in the first aspect of the present application. The method includes: Providing a substrate; Forming an epitaxial stack on the substrate; Forming an electrode on a surface of the epitaxial stack facing away from the substrate; A passivation layer is fabricated, which is disposed on the surface of the epitaxial stack facing away from the substrate and extends to the sidewalls of the electrodes; the passivation layer includes a metal oxide passivation layer obtained by ALD deposition.

[0022] A third aspect of the present application provides a light-emitting device, including the LED chip described in the first aspect of the present application.

[0023] Furthermore, the light-emitting device at least includes a display device.

[0024] By means of the above technical solutions, the present application provides an LED chip, a method for manufacturing an LED chip, and a light-emitting device. The LED chip forms a metal oxide passivation layer by ALD deposition. The passivation layer can have good metal bonding with the electrodes and has the advantage of no pinholes on the surface, and can excellently isolate water vapor.

[0025] By depositing an atomic-level metal oxide passivation layer in the interlayer between the conventional non-metal oxide passivation layer and the LED chip electrodes, the adhesion among the three is improved, thereby enhancing the reliability of the chip. Additionally, combining the chemical properties of the non-metal oxide passivation layer and the atomic-level metal oxide passivation layer endows the LED chip with the advantages of being resistant to both acids and alkalis. Specifically, the risk of exposure of the chip electrodes can be greatly reduced through the above LED chip structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In combination with the drawings and with reference to the following specific embodiments, the above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic, and the original components and elements are not necessarily drawn to scale.

[0027] Figure 1 It is a schematic structural diagram of an LED chip provided by an embodiment of the present invention; Figure 2 It is a flowchart showing the implementation of a method for manufacturing an LED chip provided by an embodiment of the present invention; Figure 3 It is a schematic structural diagram of a substrate; Figure 4 It is a schematic structural diagram of a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, and a current blocking layer; Figure 5 It is a schematic structural diagram of a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, a current blocking layer, and electrodes; Figure 6 It is a schematic structural diagram of a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, a current blocking layer, electrodes, and an adhesion layer; Figure 7Schematic structural diagram of a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, a current blocking layer, an electrode, an adhesion layer, and a first passivation layer; Figure 8 Schematic structural diagram of an LED chip provided in Comparative Example 1. Specific embodiments

[0028] The embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. The terms used in the embodiments part of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application. Those of ordinary skill in the art will know that with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0029] It should be noted that the orientation terms in the present invention are based on the relative positional relationship shown in the drawings and cannot be an absolute limitation to the present application.

[0030] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0031] Specifically, the LED chip includes: a substrate and an epitaxial stack disposed on the surface of the substrate; An electrode disposed on the surface of the epitaxial stack facing away from the substrate; A passivation layer disposed on the surface of the epitaxial stack facing away from the substrate and extending to the sidewall of the electrode; the passivation layer includes a metal oxide passivation layer obtained by ALD (Atomic Layer Deposition) deposition. Among them, the ALD deposition method is a thin film deposition technology based on self-limiting chemical reactions. By pulse-feeding a gas-phase precursor into the reaction chamber and chemically adsorbing it on the surface of the substrate, precise control of the film with atomic-level thickness can be achieved.

[0032] In some embodiments of the present invention, the passivation layer includes a first passivation layer and a second passivation layer, and the first passivation layer includes the metal oxide passivation layer obtained by ALD deposition, and the second passivation layer includes a non-metal oxide passivation layer.

[0033] In some embodiments of the present invention, the first passivation layer serves as the bottom contact layer of the passivation layer.

[0034] In some embodiments of the present invention, the first passivation layer serves as the top layer of the passivation layer.

[0035] In some embodiments of the present invention, the passivation layer further covers a partial surface of the electrode facing away from the substrate. Additionally, it can also be understood that the first passivation layer and / or the second passivation layer covers a partial surface of the electrode facing away from the substrate.

[0036] In some embodiments of the present invention, the first passivation layer and / or the second passivation layer covers the surface of the epitaxial stack facing away from the substrate.

[0037] In some embodiments of the present invention, an adhesion layer is further included; The adhesion layer is disposed between the passivation layer and the electrode.

[0038] In some embodiments of the present invention, a groove is provided on the surface of the electrode facing away from the substrate.

[0039] In some embodiments of the present invention, the material of the first passivation layer includes Al2O3.

[0040] In some embodiments of the present invention, the material of the second passivation layer includes one or more of SiO2 and Si3N4.

[0041] In some embodiments of the present invention, the material of the adhesion layer includes Ti.

[0042] In some embodiments of the present invention, the material of the electrode includes Au.

[0043] In some embodiments of the present invention, the epitaxial stack includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer stacked in sequence; the electrode includes a first electrode and a second electrode; the first electrode is electrically connected to the first-type semiconductor layer, and the second electrode is electrically connected to the second-type semiconductor layer. It should be noted that the material of the epitaxial stack includes AlxInyGa (1-x-y) N or AlxInyGa (1-x-y) P of III-V group semiconductor materials, where 0 ≤ x, y ≤ 1; x + y ≤ 1. When the material of the epitaxial stack is of the AlInGaP series, it can emit red light with a wavelength between 610 nm and 650 nm or yellow light with a wavelength between 550 nm and 570 nm. When the material of the epitaxial stack is of the InGaN series, it can emit blue light or deep blue light with a wavelength between 400 nm and 490 nm or green light with a wavelength between 490 nm and 550 nm. When the material of the epitaxial stack is of the AlGaN series, it can emit UV light with a wavelength between 400 nm and 250 nm.

[0044] In some embodiments of the present invention, the thickness of the first passivation layer is 50 nm to 200 nm, including the end values; the thickness of the second passivation layer is 50 nm to 500 nm, including the end values.

[0045] In some embodiments of the present invention, the thickness of the adhesion layer is 5 Å to 100 Å, including the end values.

[0046] In some embodiments of the present invention, the LED chip is a vertical structure, a horizontal structure or a flip-chip structure. When the LED chip is a horizontal structure and a flip-chip structure, the substrate can be a substrate. When the LED chip is a vertical structure, the substrate can be a conductive substrate.

[0047] For the convenience of understanding this solution, please refer to Figure 1 , which is a schematic structural diagram of an LED chip provided by an embodiment of the present invention. The LED chip includes a substrate 1; An epitaxial wafer located on one side of the substrate 1. The epitaxial wafer includes an N-type semiconductor layer 2, an active layer 3, and a P-type semiconductor layer 4 sequentially stacked on the substrate 1. In the embodiments of the present invention, the materials of the N-type semiconductor layer 2 and the P-type semiconductor layer 4 are taken as gallium nitride as an example, but are not limited thereto. It can be understood that in the embodiments of the present invention, the N-type semiconductor layer 2 is the first-type semiconductor layer, and the P-type semiconductor layer 4 is the second-type semiconductor layer; The epitaxial wafer has a first groove 11, and the first groove 11 exposes a part of the surface of the N-type semiconductor layer 2. It can be understood that etching is performed from the surface of the P-type semiconductor layer 4 towards the substrate until a part of the surface of the N-type semiconductor layer 2 is exposed, and finally the first groove 11 is formed; An N electrode 6, an adhesion layer 8, a first passivation layer 9, and a second passivation layer 10 sequentially stacked in the first groove 11; A current blocking layer 5, a P electrode 7, the adhesion layer 8, the first passivation layer 9, and the second passivation layer 10 sequentially stacked on the P-type semiconductor layer 4. The materials of the N electrode 6 and the P electrode 7 are Au. It can be understood that after the conductive metal layer is processed, the N electrode 6 and the P electrode 7 are formed at the corresponding positions of the N-type semiconductor layer 2 and the P-type semiconductor layer 4. That is, the N electrode 6 is the first electrode, and the P electrode 7 is the second electrode; Among them, the P electrode 7 fills the through hole 12 formed by the current blocking layer 5, and a second groove 13 with the same shape as the through hole 12 is formed in the P electrode 7. It can be understood that after a layer of current blocking layer material is deposited on the P-type semiconductor layer 4, the current blocking layer material is etched to form a current blocking layer with a through hole 12, wherein the side wall of the through hole 12 forms a certain angle with the surface of the P-type semiconductor layer 4. To a certain extent, the shape of the through hole 12 can be understood as that the side wall of the through hole 12 forms a certain angle with the surface of the P-type semiconductor layer 4, and the opening size of the through hole 12 gradually decreases in the direction pointing to the substrate 1. Subsequently, on the basis of the current blocking layer 5 having the through hole 12, the P electrode 7 and the adhesion layer 8 are deposited, and the designed circuit pattern is copied from the mask to the surface of the P electrode 7 to form a second groove 13 on the P electrode 7. The angle formed by the side wall of the second groove 13 is consistent with the angle formed by the side wall of the through hole 12 and the surface of the P-type semiconductor layer 4. In addition, there is a certain distance between the adhesion layer 8 and the opening of the second groove 13. It should be noted that the advantage of forming the second groove 13 is that it can effectively improve the wire bonding capability. Specifically, since the electrode is etched with the second groove 13, which can also be called a step, the contact area between the solder ball and the electrode can be increased, and the push-pull force can be improved. Furthermore, the second groove 13 can effectively prevent the solder ball extrusion process from extending to the edge of the PAD, thereby avoiding the abnormal electrode falling caused by the fragmentation of the current blocking layer at the edge of the PAD. Similarly, a third groove 15 is formed on the N electrode 6.

[0048] Specifically, the adhesion layer 8, the first passivation layer 9, and the second passivation layer 10 are respectively arranged in a stepped manner on the surface of the N electrode 6 away from the N-type semiconductor layer and the surface of the P electrode 7 away from the P-type semiconductor layer to form a V-shaped opening located above the second groove 13, and the V-shaped opening exposes the second groove 13. The adhesion layer 8, the first passivation layer 9, and the second passivation layer 10 respectively wrap the corresponding side walls of the P electrode 7 and the side walls of the N electrode 6 layer by layer.

[0049] It should be noted that, since the first passivation layer 9 is deposited by ALD technology, it has the advantage of having no pinholes on the surface, can effectively isolate water vapor, and by using Al2O3 as the first passivation layer 9, the chemical properties of Al2O3 itself can effectively make up for the disadvantage that SiO2 is easily corroded by alkali. In addition, Al2O3 is a high-K (dielectric constant) dielectric with a large band gap and high potential barrier, which can reduce tunneling current, and it has low defect state density and fixed charge density, which can effectively inhibit metal migration.

[0050] In an embodiment of the present invention, the material of the adhesion layer 8 is Ti. It can be understood that by adding the highly adhesive metal Ti on the Au coating on the chip electrode surface, the overall adhesion between the metal electrode and the passivation layer protective film is improved. At the same time, by depositing an atomic-level passivation layer, i.e., the first passivation layer 9, in the interlayer between the PECVD passivation layer and the LED electrode, and this passivation layer is a metal oxide passivation layer, which can not only have good metal bonding with the LED electrode but also have good covalent bonding with the non-metal oxide passivation layer deposited by PECVD, i.e., the second passivation layer 10, thereby improving the adhesion between the three film layers.

[0051] Finally, for a flip-chip with backlight emission, the increase in the reflectivity of the metal electrode is beneficial to improving the light utilization rate of the chip; since the refractive index of the second passivation layer 10 is greater than that of the first passivation layer 9, the passivation layer forms an antireflection film structure, which can improve the overall light extraction efficiency of the chip to a certain extent.

[0052] In an optional embodiment of the present invention, the thickness of the adhesion layer 8 is 5 Å to 100 Å. Exemplarily, the thickness of the adhesion layer 8 is 5 Å, 10 Å, 20 Å, 30 Å, 40 Å, 50 Å, 60 Å, 70 Å, 80 Å, 90 Å or 100 Å, etc., but not limited thereto.

[0053] In an optional embodiment of the present invention, the thickness of the first passivation layer 9 is 50 nm to 200 nm. Exemplarily, the thickness of the first passivation layer 9 is 50 nm, 100 nm, 150 nm or 200 nm, etc., but not limited thereto.

[0054] In an optional embodiment of the present invention, the thickness of the second passivation layer 10 is 50 nm to 500 nm. Exemplarily, the thickness of the second passivation layer 10 is 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm or 500 nm, etc., but not limited thereto.

[0055] Correspondingly, an embodiment of the present invention further provides a method for manufacturing an LED chip, and the method includes: Providing a substrate; Forming an epitaxial stack on the substrate; Forming an electrode on the surface of the epitaxial stack facing away from the substrate; Fabricating a passivation layer, the passivation layer is disposed on the surface of the epitaxial stack facing away from the substrate and extends to the sidewall of the electrode; the passivation layer includes a metal oxide passivation layer obtained by an ALD deposition method.

[0056] To fabricate the above LED chip, refer to Figure 2, is a flowchart for implementing a method for fabricating an LED chip provided by an embodiment of the present invention, which specifically includes the following steps: S1: As Figure 3 shown, provide a substrate 1.

[0057] S2: As Figure 4 shown, epitaxially grow an N-type semiconductor layer 2, an active layer 3, a P-type semiconductor layer 4, and a current blocking layer 5 on the substrate 1 in sequence, and etch to expose a part of the N-type semiconductor layer 2.

[0058] Specifically, the materials of the N-type semiconductor layer 2 and the P-type semiconductor layer 4 are both gallium nitride as an example, but are not limited thereto.

[0059] S3: As Figure 5 shown, deposit corresponding electrodes on the exposed part of the N-type semiconductor layer 2 and the P-type semiconductor layer 4.

[0060] Among them, etch from the surface of the P-type semiconductor layer 4 towards the substrate 1 until a part of the surface of the N-type semiconductor layer 2 is exposed, finally forming a first groove 11, and deposit an N electrode 6 in the first groove 11. In addition, after depositing a layer of current blocking layer material on the P-type semiconductor layer 4, etch the current blocking layer material to form a current blocking layer 5 provided with a through hole 12, and on the basis of the current blocking layer 5 having the through hole 12, deposit a P electrode 7 integrally. The materials of the N electrode 6 and the P electrode 7 include Au.

[0061] S4: As Figure 6 shown, deposit an adhesion layer 8 on the electrodes.

[0062] Specifically, the material of the adhesion layer 8 is Ti.

[0063] S5: As Figure 7 shown, deposit a first passivation layer 9 on the electrodes and the adhesion layer 8 after the electrode pattern transfer, and the material of the first passivation layer 9 is Al2O3.

[0064] Among them, the first passivation layer 9 is deposited by ALD (atomic layer deposition) technology, and electrode pattern transfer refers to precisely transferring the geometric pattern on the mask to the electrodes through a series of physical or chemical methods.

[0065] S6: As Figure 1 shown, deposit a second passivation layer 10 on the first passivation layer 9, and perform pattern transfer on the first passivation layer 9 and the second passivation layer 10. The materials of the second passivation layer 10 include one or more of SiO2 and Si3N4.

[0066] Among them, the pattern transfer of the first passivation layer 9 and the second passivation layer 10 refers to precisely transferring the geometric pattern on the mask to the first passivation layer 9 and the second passivation layer 10 through a series of physical or chemical methods. It should be noted that the above steps are all completed in an MOCVD (Metal-Organic Chemical Vapor Deposition) device. The MO sources used include metal sources such as trimethylgallium (TEGa), triethylgallium (TEGa), trimethylindium (TMIn), bis(cyclopentadienyl)magnesium (Cp2Mg), trimethylaluminum (TMAl). TEGa and TEGa are used as Ga sources, and gaseous sources include silane (SiH4), ammonia (NH3), H2, and N2. Among them, NH3 is the N source, and H2 and N2 are carrier gases. The N-type and P-type doping sources are silane SiH4 and bis(cyclopentadienyl)magnesium CP2Mg respectively.

[0067] In summary, the present invention provides an LED chip, an LED chip manufacturing method, and a lighting device. By depositing an atomic-level metal oxide passivation layer in the interlayer between a conventional non-metal oxide passivation layer and the electrodes of the LED chip, the adhesion between the three is improved, thereby enhancing the reliability of the chip. Additionally, combining the chemical properties of the non-metal oxide passivation layer and the atomic-level metal oxide passivation layer endows the LED chip with the advantages of being resistant to both acids and alkalis. Specifically, the risk of electrode exposure on the chip can be significantly reduced through the above LED chip structure.

[0068] The following further illustrates the present invention with specific embodiments: Example 1 The LED chip in this Example 1 includes: A substrate; An epitaxial wafer on one side of the substrate. The epitaxial wafer includes an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked in sequence on the substrate. The materials of both the N-type semiconductor layer and the P-type semiconductor layer are gallium nitride; The epitaxial wafer has a first groove that exposes a part of the surface of the N-type semiconductor layer; An N electrode, an adhesion layer, a first passivation layer, and a second passivation layer stacked in sequence in the first groove. The material of the first passivation layer is Al2O3, the material of the second passivation layer includes at least one or more of SiO2 and Si3N4, the material of the adhesion layer is Ti, and the first passivation layer is deposited by ALD technology; A current blocking layer, a P electrode, the adhesion layer, the first passivation layer, and the second passivation layer stacked in sequence on the P-type semiconductor layer. The materials of the N electrode and the P electrode are Au; Among them, the P electrode fills the through hole formed by the current blocking layer, and a second groove having the same shape as the through hole is formed in the P electrode. The adhesion layer, the first passivation layer, and the second passivation layer are arranged in a stepped manner on the surface of the N electrode facing away from the N-type semiconductor layer and the surface of the P electrode facing away from the P-type semiconductor layer, respectively, to form a V-shaped opening above the second groove, and the V-shaped opening exposes the second groove. The adhesion layer, the first passivation layer, and the second passivation layer respectively wrap the side walls of the corresponding P electrode and the N electrode layer by layer.

[0069] In a specific embodiment, the thickness of the adhesion layer is 5 Å.

[0070] In a specific embodiment, the thickness of the first passivation layer is 50 nm.

[0071] In a specific embodiment, the thickness of the second passivation layer is 50 nm.

[0072] Embodiment 2 This Embodiment 2 also provides an LED chip. The difference from Embodiment 1 is that the thickness of the adhesion layer is 50 Å.

[0073] Embodiment 3 This Embodiment 3 also provides an LED chip. The difference from Embodiment 1 is that the thickness of the adhesion layer is 100 Å.

[0074] Embodiment 4 This Embodiment 4 also provides an LED chip. The difference from Embodiment 1 is that the thickness of the adhesion layer is 50 Å and the thickness of the second passivation layer is 100 nm.

[0075] Embodiment 5 This Embodiment 5 also provides an LED chip. The difference from Embodiment 1 is that the thickness of the adhesion layer is 50 Å and the thickness of the second passivation layer is 300 nm.

[0076] Embodiment 6 This Embodiment 6 also provides an LED chip. The difference from Embodiment 1 is that the thickness of the adhesion layer is 50 Å and the thickness of the second passivation layer is 500 nm.

[0077] Embodiment 7 This Embodiment 7 also provides an LED chip. The difference from Embodiment 1 is that the thickness of the adhesion layer is 50 Å and the thickness of the first passivation layer is 100 nm.

[0078] Embodiment 8 Embodiment 8 also provides an LED chip, which is different from Embodiment 7 in that the thickness of the second passivation layer is 100 nm.

[0079] Embodiment 9 Embodiment 9 also provides an LED chip, which is different from Embodiment 7 in that the thickness of the second passivation layer is 300 nm.

[0080] Embodiment 10 Embodiment 10 also provides an LED chip, which is different from Embodiment 7 in that the thickness of the second passivation layer is 500 nm.

[0081] Embodiment 11 Embodiment 11 also provides an LED chip, which is different from Embodiment 10 in that the thickness of the first passivation layer is 200 nm and the thickness of the second passivation layer is 50 nm.

[0082] Embodiment 12 Embodiment 12 also provides an LED chip, which is different from Embodiment 11 in that the thickness of the second passivation layer is 100 nm.

[0083] Embodiment 13 Embodiment 13 also provides an LED chip, which is different from Embodiment 11 in that the thickness of the second passivation layer is 300 nm.

[0084] Embodiment 14 Embodiment 14 also provides an LED chip, which is different from Embodiment 11 in that the thickness of the second passivation layer is 500 nm.

[0085] Embodiment 15 Embodiment 15 also provides an LED chip, which is different from Embodiment 14 in that the thickness of the adhesion layer is 100 Å.

[0086] Comparative Example 1 Comparative Example 1 provides an LED chip structure. Please refer to Figure 8 , which is different from Embodiment 1 of the present invention in that after corresponding electrodes are formed on the N-type semiconductor layer 2 and the P-type semiconductor layer 4 respectively, an SiO2 passivation layer 14 is deposited on the electrode surface. Among them, the SiO2 passivation layer 14 can be understood as the second passivation layer in Embodiment 1 of the present invention, and the thickness of the SiO2 passivation layer 14 is 50 nm.

[0087] Comparative Example 2 Comparative Example 2 provides an LED chip structure, which is different from Comparative Example 1 in that the thickness of the SiO2 passivation layer 14 is 100 nm.

[0088] Comparative Example 3 Comparative Example 3 provides an LED chip structure, which is different from that of Comparative Example 1 in that the thickness of the SiO2 passivation layer 14 is 200 nm.

[0089] Comparative Example 4 Comparative Example 4 provides an LED chip structure, which is different from that of Comparative Example 1 in that the thickness of the SiO2 passivation layer 14 is 300 nm.

[0090] The LED chips finally prepared in Examples 1 to [Example number] and the LED chips in Comparative Example 1 were subjected to reliability tests under the same conditions, and the results are shown in the following table:

[0091] It can be found from the table that the bonding push-pull force at the electrodes of the LED chips prepared in the embodiments of the present invention is better than that of the LED chips in the comparative examples. At the same time, the chip failure rate of the LED chips prepared in the embodiments of the present invention is lower than that of the LED chips in the comparative examples.

[0092] Based on the above embodiments of the present invention, in another embodiment of the present invention, a light-emitting device is further provided. The light-emitting device includes the LED chip described in the above embodiments, and the light-emitting device includes at least a display device. The above has introduced in detail an LED chip, a method for preparing an LED chip, and a light-emitting device provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention. It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method part. It should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that the elements inherent in a process, method, article or device comprising a series of elements, or those further comprising elements inherent in these process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element. The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip, characterized in that, The LED chip includes: a substrate and an epitaxial stack disposed on the surface of the substrate; An electrode, which is disposed on the surface of the epitaxial stack facing away from the substrate; A passivation layer, which is disposed on the surface of the epitaxial stack facing away from the substrate and extends to the sidewall of the electrode; the passivation layer includes a first passivation layer and a second passivation layer, the first passivation layer includes a metal oxide passivation layer obtained by ALD deposition, and the second passivation layer includes a non-metal oxide passivation layer.

2. The LED chip according to claim 1, characterized in that, The first passivation layer serves as the bottom contact layer of the passivation layer.

3. The LED chip according to claim 1, characterized in that, The first passivation layer serves as the top layer of the passivation layer.

4. The LED chip according to claim 1, characterized in that, The passivation layer also covers a part of the surface of the electrode facing away from the substrate.

5. The LED chip according to claim 1, wherein The first passivation layer and / or the second passivation layer covers the surface of the epitaxial stack facing away from the substrate.

6. The LED chip according to claim 1, wherein It further includes an adhesion layer; The adhesion layer is disposed between the passivation layer and the electrode.

7. The LED chip according to claim 1, wherein, A groove is provided on the surface of the electrode facing away from the substrate.

8. The LED chip according to claim 1, wherein The material of the first passivation layer includes Al2O3.

9. The LED chip according to claim 1, wherein The material of the second passivation layer includes one or more of SiO2 and Si3N4.

10. The LED chip according to claim 6, wherein The material of the adhesion layer includes Ti.

11. The LED chip according to claim 1, characterized in that, The material of the electrode includes Au.

12. The LED chip according to claim 1, wherein The epitaxial stack includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer stacked in sequence; the electrode includes a first electrode and a second electrode; the first electrode is electrically connected to the first-type semiconductor layer, and the second electrode is electrically connected to the second-type semiconductor layer.

13. The LED chip according to claim 1, wherein The thickness of the first passivation layer is 50 nm to 200 nm, including the end values; the thickness of the second passivation layer is 50 nm to 500 nm, including the end values.

14. The LED chip according to claim 6, wherein The thickness of the adhesion layer is 5 Å to 100 Å, including the end values.

15. The LED chip according to any one of claims 1 to 14, characterized in that, The LED chip is of a vertical structure, a horizontal structure, or a flip-chip structure.

16. A method for preparing an LED chip, characterized in that, For manufacturing the LED chip according to any one of claims 1-15, the method includes: Providing a substrate; Forming an epitaxial stack on the substrate; Forming an electrode on the surface of the epitaxial stack facing away from the substrate; Fabricating a passivation layer, which is disposed on the surface of the epitaxial stack facing away from the substrate and extends to the sidewall of the electrode; the passivation layer includes a metal oxide passivation layer obtained by ALD deposition.

17. A light-emitting device, characterized in that, Includes the LED chip according to any one of claims 1-15.

18. A light-emitting device according to claim 17, wherein, The light-emitting device at least includes a display device.

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