Three-dimensional memory device with channel cap structure and method of forming same

Abstract

A semiconductor structure includes an alternating stack of insulating layers and conductive layers, a memory opening extending vertically through the alternating stack, and a memory opening fill structure in the memory opening. A Group IV material-containing portion is formed by selective deposition on an end portion of the vertical semiconductor channel. Alternatively, a backside semiconductor cap layer structure can be formed directly on the bottom surface of the vertical semiconductor channel by selective or non-selective deposition of semiconductor material.

Description

[0001] Related Applications

[0002] This application claims the priority benefit of U.S. Provisional Patent Application No. 63 / 496,653, filed on April 17, 2023, and U.S. Provisional Patent Application No. 63 / 496,660, filed on April 17, 2023. The entire contents of these U.S. Provisional Patent Applications are incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three-dimensional memory devices including a channel capping layer structure and methods of forming the same. Background Art

[0004] A three-dimensional vertical NAND string having one bit per cell is disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell" (IEDM Proc. (2001) pages 33 - 36). Summary of the Invention

[0005] According to one aspect of the present disclosure, there is provided a semiconductor structure including: an alternating stack of insulating layers and conductive layers; a memory opening extending vertically through the alternating stack; a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel, the vertical semiconductor channel laterally surrounding a core cavity containing no solid-phase material therein; a Group-IV material portion contacting an end portion of the vertical semiconductor channel and exposed in the core cavity; and a source contact structure contacting a bottom surface of the Group-IV material portion and a bottom surface of the lowermost layer in the alternating stack.

[0006] According to another aspect of the present disclosure, there is provided a method of forming a semiconductor structure. The method includes: forming an alternating stack of insulating layers and spacer material layers over a carrier substrate, wherein the spacer material layer is formed as a conductive layer or is subsequently replaced by a conductive layer; forming a memory opening through the alternating stack; forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure includes a memory film and a vertical semiconductor channel; removing the carrier substrate; removing an end portion of the memory opening fill structure to expose an end portion of the vertical semiconductor channel; selectively growing a Group-IV material portion from a physically exposed surface of the vertical semiconductor channel; and forming a source contact structure over the Group-IV material portion.

[0007] According to another aspect of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising: an alternating stack of an insulating layer and a conductive layer; a memory opening extending vertically through the alternating stack; a memory opening filling structure located in the memory opening and comprising a memory film and a vertical semiconductor channel; and a back semiconductor capping layer structure having a top surface in contact with a bottom surface of the vertical semiconductor channel, wherein the entire top surface of the back semiconductor capping layer structure is located in a horizontal plane including a bottom surface of the bottommost insulating layer within the alternating stack.

[0008] According to yet another aspect of the present disclosure, a method of forming a semiconductor structure is provided, the method comprising; forming an alternating stack of an insulating layer and a spacer material layer over a carrier substrate, wherein the spacer material layer is formed as a conductive layer or is subsequently replaced by a conductive layer; forming a memory opening extending vertically through the alternating stack; forming a memory opening filling structure in the memory opening, wherein the memory opening filling structure comprises a memory film and a vertical semiconductor channel; removing the carrier substrate; exposing a bottom surface of the vertical semiconductor channel in a horizontal plane including a bottom surface of the bottommost insulating layer within the alternating stack; and forming a back semiconductor capping layer structure by directly depositing a semiconductor material on the bottom surface of the vertical semiconductor channel. Description of the Drawings

[0009] Figure 1 is a schematic vertical cross-sectional view of a first exemplary structure after forming an alternating stack of an insulating layer and a sacrificial material layer over a carrier substrate according to a first embodiment of the present disclosure.

[0010] Figure 2 is a schematic vertical cross-sectional view of a first exemplary structure after forming a stepped surface and a stepped dielectric material portion according to a first embodiment of the present disclosure.

[0011] Figure 3 is a schematic vertical cross-sectional view of a first exemplary structure after forming a support opening according to a first embodiment of the present disclosure.

[0012] Figure 4 is a vertical cross-sectional view of a first exemplary structure after forming a support pillar structure according to a first embodiment of the present disclosure.

[0013] Figure 5A is a schematic vertical cross-sectional view of a first exemplary structure after forming a memory opening according to a first embodiment of the present disclosure.

[0014] Figure 5B is Figure 5ATop view of the first exemplary structure. The vertical plane A-A is Figure 5A the cutting plane of the vertical sectional view of

[0015] Figures 6A to 6F Sequential vertical sectional views of a memory opening during the formation of a memory opening filling structure according to an embodiment of the present disclosure.

[0016] Figure 7A Schematic vertical sectional view of the first exemplary structure after the formation of a memory opening filling structure according to the first embodiment of the present disclosure.

[0017] Figure 7B is Figure 7A Top view of the first exemplary structure of Figure 7A The vertical plane A-A is the cutting plane of the vertical sectional view of

[0018] Figure 8A Vertical sectional view of the first exemplary structure after the formation of a lateral isolation trench according to the first embodiment of the present disclosure.

[0019] Figure 8B is Figure 8A Top view of the first exemplary structure of Figure 8A The vertical plane A-A is the cutting plane of the vertical sectional view of

[0020] Figure 9 Vertical sectional view of the first exemplary structure after the formation of a laterally extending cavity according to the first embodiment of the present disclosure.

[0021] Figure 10 Schematic vertical sectional view of the first exemplary structure after the formation of a conductive layer according to the first embodiment of the present disclosure.

[0022] Figure 11A Vertical sectional view of the first exemplary structure after the formation of a lateral isolation trench filling structure, a layer contact via structure, and a drain contact via structure according to the first embodiment of the present disclosure.

[0023] Figure 11B is Figure 11A Top view of the first exemplary structure of Figure 11A The vertical plane A-A is the cutting plane of the vertical sectional view of

[0024] Figure 12 Vertical sectional view of the first exemplary structure after the formation of a memory die according to the first embodiment of the present disclosure.

[0025] Figure 13 Vertical sectional view of a logic die according to the first embodiment of the present disclosure.

[0026] Figure 14 is a vertical cross-sectional view of a first exemplary structure after attaching a logic die to a memory die according to a first embodiment of the present disclosure.

[0027] Figure 15A is a vertical cross-sectional view of a first exemplary structure after removing a carrier substrate according to a first embodiment of the present disclosure.

[0028] Figure 15B is Figure 15A an enlarged view of region B of

[0029] Figures 16A to 16F is a sequential vertical cross-sectional view of regions of a first configuration of a first exemplary structure during formation of a channel capping layer structure according to a first embodiment of the present disclosure.

[0030] Figures 17A to 17D is a sequential vertical cross-sectional view of regions of a second configuration of a first exemplary structure during formation of a channel capping layer structure according to a first embodiment of the present disclosure.

[0031] Figures 18A to 18C is a sequential vertical cross-sectional view of regions of a third configuration of a first exemplary structure during formation of a backside semiconductor capping layer structure according to a first embodiment of the present disclosure.

[0032] Figure 19 is a vertical cross-sectional view of a first exemplary structure after forming a source contact structure according to a first embodiment of the present disclosure.

[0033] Figure 20A is a schematic vertical cross-sectional view of a second exemplary structure after forming a memory opening according to a second embodiment of the present disclosure.

[0034] Figure 20B is Figure 20A a top view of the second exemplary structure of. Vertical plane A-A is Figure 20A the cutting plane of the vertical cross-sectional view of

[0035] Figures 21A to 21D is a sequential vertical cross-sectional view of a memory opening during formation of a memory opening fill structure according to an embodiment of the present disclosure.

[0036] Figure 22A is a schematic vertical cross-sectional view of a second exemplary structure after forming a memory opening fill structure according to a second embodiment of the present disclosure.

[0037] Figure 22B is Figure 22A a top view of the second exemplary structure of. Vertical plane A-A is Figure 22A the cutting plane of the vertical cross-sectional view of

[0038] Figure 23A is a vertical cross-sectional view of a second exemplary structure after forming a lateral isolation trench according to a second embodiment of the present disclosure.

[0039] Figure 23B is Figure 23A a top view of a second exemplary structure of. The vertical plane A-A is Figure 23A the cutting plane of the vertical cross-sectional view of.

[0040] Figure 24 is a vertical cross-sectional view of a second exemplary structure after forming a laterally extending cavity according to a second embodiment of the present disclosure.

[0041] Figure 25 is a schematic vertical cross-sectional view of a second exemplary structure after forming a conductive layer according to a second embodiment of the present disclosure.

[0042] Figure 26A is a vertical cross-sectional view of a second exemplary structure after forming a lateral isolation trench filling structure, a layer contact via structure, and a drain contact via structure according to a second embodiment of the present disclosure.

[0043] Figure 26B is Figure 26A a top view of a second exemplary structure of. The vertical plane A-A is Figure 26A the cutting plane of the vertical cross-sectional view of.

[0044] Figure 27 is a vertical cross-sectional view of a second exemplary structure after forming a memory die according to a second embodiment of the present disclosure.

[0045] Figure 28 is a vertical cross-sectional view of a second exemplary structure after attaching a logic die to a memory die according to a second embodiment of the present disclosure.

[0046] Figure 29A is a vertical cross-sectional view of a second exemplary structure after removing a carrier substrate according to a second embodiment of the present disclosure.

[0047] Figure 29B is Figure 29A an enlarged view of region B of.

[0048] Figure 30A is a vertical cross-sectional view of a second exemplary structure after performing a chemical mechanical polishing process according to a second embodiment of the present disclosure.

[0049] Figure 30B is Figure 30A an enlarged view of region B of.

[0050] Figures 31A to 31D is a sequential vertical cross-sectional view of regions of a first configuration of a second exemplary structure during formation of a backside semiconductor cap layer structure and a source contact structure, according to a second embodiment of the present disclosure.

[0051] Figure 31E is an alternative embodiment of the first configuration of the second exemplary structure.

[0052] Figure 32A and Figure 32B is a sequential vertical cross-sectional view of regions of a second configuration of a second exemplary structure during formation of a backside semiconductor cap layer structure and a source contact structure, according to a second embodiment of the present disclosure.

[0053] Figure 32C is an alternative embodiment of the second configuration of the second exemplary structure.

[0054] Figures 33A to 33D is a sequential vertical cross-sectional view of regions of a third configuration of a second exemplary structure during formation of a backside semiconductor cap layer structure and a source contact structure, according to a second embodiment of the present disclosure.

[0055] Figure 33E is an alternative embodiment of the third configuration of the second exemplary structure.

[0056] Figure 34A and Figure 34B is a sequential vertical cross-sectional view of regions of a fourth configuration of a second exemplary structure during formation of a backside semiconductor cap layer structure and a source contact structure, according to a second embodiment of the present disclosure.

[0057] Figure 34C is an alternative embodiment of the fourth configuration of the second exemplary structure.

[0058] Figures 35A to 35C is a sequential vertical cross-sectional view of regions of a fifth configuration of a second exemplary structure during formation of a backside semiconductor cap layer structure and a source contact structure, according to a second embodiment of the present disclosure.

[0059] Figure 35D is an alternative embodiment of the fifth configuration of the second exemplary structure.

[0060] Figure 36 is a vertical cross-sectional view of a second exemplary structure after formation of a source contact structure, according to a second embodiment of the present disclosure.

[0061] Figure 37 is a vertical cross-sectional view of an alternative embodiment of a second exemplary structure after formation of a source contact structure, according to a second embodiment of the present disclosure. Detailed Description

[0062] As discussed above, embodiments of the present disclosure relate to three-dimensional memory devices including a channel capping layer structure and methods of forming the same, and various aspects of the three-dimensional memory devices are described below. Embodiments of the present disclosure can be used to form various structures including multi-level memory structures, non-limiting examples of which include three-dimensional memory devices that include a plurality of memory strings.

[0063] The drawings are not drawn to scale. In the case of illustrating a single instance of an element, multiple instances of the element may be replicated unless otherwise explicitly described or clearly indicated that there is no replication of the element. Ordinal numbers such as "first", "second", and "third" are used only to identify similar elements, and different ordinal numbers may be employed in the specification and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0064] Like reference numerals represent like or similar elements. Unless otherwise indicated, elements having the same reference numerals are considered to have the same composition and the same function. Unless otherwise indicated, "contact" between elements refers to direct contact that provides an edge or surface shared by the elements. If two or more elements do not directly contact each other or are not in direct contact with each other, the two elements are "separated" from each other or are "separated" from each other. As used herein, an element located "on" a second element can be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, an element is "directly" located "on" a second element if there is physical contact between the surface of the element and the surface of the second element. As used herein, an element is "electrically connected to" a second element if there is an electrical conduction path between the element and the second element composed of at least one conductive material. As used herein, a "prototype" structure or a "structure in process" is an instantaneous structure in which the shape or composition of at least one component is subsequently modified.

[0065] As used herein, a "layer" refers to a portion of a material including a region having a thickness. The layer can extend over the entirety of a structure below or above, or the extent of the layer can be less than the extent of the structure below or above. Additionally, a layer can be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of a continuous structure or between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, or can have one or more layers on, above, and / or below it.

[0066] Generally speaking, a semiconductor die or semiconductor package may include a memory chip. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (usually one or two). The same, concurrent operations can occur on each plane, but there are some limitations. Each plane contains multiple blocks, which are the smallest units that can be erased in a single erase operation. Each block contains multiple pages, which are the smallest units that can be programmed, i.e., the smallest units on which a read operation can be performed.

[0067] As used herein, "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m in the absence of an electrical dopant, and capable of producing a doped material having a conductivity in the range of 1.0 S / m to 1.0×10 7 S / m when appropriately doped with an electrical dopant. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" refers to a material having a conductivity greater than 1.0×10 5 S / m. As used herein, "insulator material" or "dielectric material" refers to a material having a conductivity less than 1.0×10 -5 S / m. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrical dopant at a high enough atomic concentration to become a conductive material (i.e., provide a conductivity greater than 1.0×10 5 S / m) when formed as a crystalline material or when transformed into a crystalline material by an annealing process (e.g., from an initial amorphous state). A "doped semiconductor material" can be a heavily doped semiconductor material, or can be a semiconductor material having a concentration of electrical dopants (i.e., p-type dopants and / or n-type dopants) that provides a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 7 S / m. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semi-conductive or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semi-conductive or conductive, depending on the atomic concentration of the electrical dopants therein. As used herein, "metal material" refers to a conductive material that includes at least one metal element. All conductivity measurements are made under standard conditions.

[0068] Reference Figure 1 , illustrates a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a carrier substrate 9, which may be a semiconductor substrate or a conductive substrate. For example, the carrier substrate 9 may include a commercially available silicon wafer. Alternatively, the carrier substrate 9 may include any material that can be selectively removed with respect to the material of the insulating layer 32 and a dielectric material portion to be formed subsequently.

[0069] An alternating stack of a first material layer and a second material layer may be formed over the carrier substrate 9. The first material layer may be an insulating layer, and the second material layer may be a spacer material layer. In one embodiment, the spacer material layer may include a sacrificial material layer 42. In this case, an alternating stack (32, 42) of the insulating layer 32 and the sacrificial material layer 42 may be formed over the carrier substrate 9. The insulating layer 32 includes an insulating material such as undoped silicate glass or doped silicate glass, and the sacrificial material layer 42 includes a sacrificial material such as silicon nitride or a silicon-germanium alloy. In one embodiment, the insulating layer 32 (i.e., the first material layer) may include a silicon oxide layer, and the sacrificial material layer 42 (i.e., the second material layer) may include a silicon nitride layer.

[0070] The alternating stack (32, 42) may include multiple repetitions of a unit layer stack including the insulating layer 32 and the sacrificial material layer 42. The total number of repetitions of the unit layer stack within the alternating stack (32, 42) may be, for example, in the range of 8 to 1024 (such as 32 to 256), but smaller and larger numbers of repetitions may also be employed. The topmost one of the insulating layers 32 is hereinafter referred to as the top insulating layer 32T. The bottommost one of the insulating layers 32 is the insulating layer 32 closest to the carrier substrate 9, which is referred to herein as the bottom insulating layer 32B.

[0071] Each of the insulating layers 32 other than the top insulating layer 32T may have a thickness in the range of 20 nm to 100 nm (such as 30 nm to 60 nm), but smaller and larger thicknesses may also be employed. Each of the sacrificial material layers 42 may have a thickness in the range of 20 nm to 100 nm (such as 30 nm to 60 nm), but smaller and larger thicknesses may also be employed. In one embodiment, the top insulating layer 32 may have a thickness approximately half of the thickness of the other insulating layers 32.

[0072] The first exemplary structure includes a memory array region 100 in which a three-dimensional array of memory elements will be formed subsequently, and a contact region 300 in which a layer contact via structure for contacting word lines will be formed subsequently.

[0073] While embodiments have been described in which the spacer material layer is formed as a sacrificial material layer 42, in alternative embodiments, the spacer material layer may be formed as a conductive layer. Generally speaking, the spacer material layer of the present disclosure may be formed as a conductive layer or may subsequently be at least partially replaced with a conductive layer.

[0074] Reference Figure 2 , an optional stepped surface is formed in the contact region 300. As used herein, a "stepped surface" refers to a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is contiguous with a first vertical surface extending upward from a first edge of the horizontal surface and with a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within a volume from which multiple portions of the alternating stack (32, 42) are removed by forming the stepped surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0075] The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity varies stepwise according to the vertical distance from the top surface of the carrier substrate 9. In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process that vertically increases the depth of the cavity by one or more levels, and a second type of etching process that laterally expands the region to be vertically etched in a subsequent first type of etching process. As used herein, a "level" of a structure including an alternating plurality is defined as the relative positioning of a pair of a first material layer and a second material layer within the structure.

[0076] Each sacrificial material layer 42 within the alternating stack (32, 42) other than the topmost sacrificial material layer 42 extends further laterally in the platform region than any of the overlying sacrificial material layers 42 within the alternating stack (32, 42). The stepped surface of the alternating stack (32, 42) extends continuously from the lowermost layer (such as the bottommost insulating layer 32B) within the alternating stack (32, 42) to the topmost layer (such as the topmost insulating layer 32T) within the alternating stack (32, 42).

[0077] A stepped dielectric material portion 65 (i.e., an insulating fill material portion) can be formed in the stepped cavity by depositing a dielectric material in the stepped cavity. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. The excess portion of the deposited dielectric material can be removed from above the top surface of the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material that fills the stepped cavity constitutes the stepped dielectric material portion 65. As used herein, a "stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases or decreases stepwise according to the vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the stepped dielectric material portion 65, the silicon oxide of the stepped dielectric material portion 65 can be doped or may not be doped with dopants such as B, P, and / or F.

[0078] Reference Figure 3 , an optional first etch mask layer (such as a photoresist layer) can be formed over the alternating stack (32, 42) and can be lithographically patterned to form openings in the contact region 300. An anisotropic etch process can be performed to transfer the pattern of the openings in the first etch mask layer through the stepped dielectric material portion 65 and the alternating stack (32, 42). Support openings 19 can optionally be formed in the contact region 300 through the stepped dielectric material portion 65 and the alternating stack (32, 42). Each of the support openings 19 can extend vertically into the carrier substrate 9. In one embodiment, the bottom surface of the support openings 19 can be formed at or below the top surface of the carrier substrate 9. The support openings 19 can have a diameter in the range of 60 nm to 400 nm (such as 120 nm to 300 nm), but smaller and larger thicknesses can be employed.

[0079] Reference Figure 4 , a dielectric fill material (such as silicon oxide) can be deposited in the support openings 19 by a conformal deposition process. The excess portion of the dielectric fill material can be removed from above the top surface of the topmost insulating layer 32T, for example, by a trench etch process. Each portion of the dielectric fill material that fills the corresponding support opening 19 constitutes a support pillar structure 20, which can be used to provide structural support to the insulating layer 32 and the stepped dielectric material portion 65 during replacement of the sacrificial material layer 42 with a conductive layer. Alternatively, the support openings 19 can be formed simultaneously with the memory openings at a later step, and the support pillar structures 20 can be formed in the support openings 19 while the memory opening fill structures are formed in the memory openings, as will be described below.

[0080] Reference Figure 5A and Figure 5B, a second etch mask layer (such as a photoresist layer) may be formed over the alternating stack (32, 42) and may be lithographically patterned to form openings in the memory array region 100. An anisotropic etch process may be performed to transfer the pattern of the openings in the second etch mask layer through the alternating stack (32, 42). Memory openings 49 may be formed through the alternating stack (32, 42) in the memory array region 100. Each of the memory openings 49 may extend at least vertically to the top surface of the carrier substrate 9. In one embodiment, the bottom surface of the memory openings 49 may be formed at or below the top surface of the carrier substrate 9. Each cluster of the memory openings 49 may include multiple rows of memory openings 49. Each row of memory openings 49 may include a plurality of memory openings 49 arranged at a uniform pitch along a first horizontal direction hd1. The multiple rows of memory openings 49 may be laterally spaced apart from each other along a second horizontal direction hd2, which may be perpendicular to the first horizontal direction hd2. In one embodiment, each cluster of the memory openings 49 may be formed as a two-dimensional periodic array of the memory openings 49. The memory openings 49 may have a diameter in the range of 60 nm to 400 nm (such as 120 nm to 300 nm), but smaller and larger thicknesses may be employed. In an alternative embodiment, support openings 19 may be formed simultaneously with the memory openings 49 using the same patterned photoresist layer.

[0081] Figures 6A to 6F is a sequential vertical cross-section of the memory openings 49 during the formation of the memory opening fill structure 58 according to an embodiment of the present disclosure.

[0082] Reference Figure 6A , a sacrificial pedestal structure 11 may be formed at the bottom of each of the memory openings 49. In an embodiment where the carrier substrate 9 includes a semiconductor material (such as single-crystalline silicon), the sacrificial pedestal structure 11 may include a semiconductor material, such as single-crystalline silicon, and may be formed by selectively growing the semiconductor material from the physically exposed surface of the carrier substrate 9. A selective semiconductor deposition process (such as selective epitaxy) may be employed to form the sacrificial pedestal structure 11.

[0083] Reference Figure 6B, a layer stack including a memory material layer 54 can be conformally deposited. In an illustrative example, the layer stack may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner layer 56. The memory material layer 54 includes a memory material, i.e., a material in which data bits can be stored. The memory material layer 54 may include a charge storage material (such as silicon nitride), a ferroelectric material, a phase change memory material, or any other memory material that can store data bits by inducing a change in resistivity, ferroelectric polarization, or any other measurable physical property. In the case where the memory material layer 54 includes a charge storage material, the optional dielectric liner layer 56 may include a tunneling dielectric layer.

[0084] Reference Figure 6C , a semiconductor channel material layer 60L can be deposited over each memory film 50 by performing a conformal deposition process. If the semiconductor channel material layer 60L is doped, the semiconductor channel material layer 60L may have a doping of a first conductivity type, which can be p-type or n-type.

[0085] Reference Figure 6D , a dielectric core layer 62L containing a dielectric fill material (such as silicon oxide) can be deposited in the remaining volume of the memory opening 49. Although a conformal deposition process (such as a chemical vapor deposition process) can be used to deposit the dielectric core layer 62L, the conformality of the conformal deposition process may not be perfect. Therefore, the thickness of the bottom portion of the dielectric core layer 62L at the bottom of each memory opening 49 may be less than the thickness of the upper portion of the dielectric core layer 62L at the top of each memory opening 49. A cavity or seam may be formed in the bottom portion of each memory opening 49 that is not filled with the dielectric fill material of the dielectric core layer 62L. The cavity is referred to herein as the core cavity 69. The core cavity 69 may extend vertically through a subset of the layers of the alternating stack (32, 42) located at the bottom portion of the alternating stack (32, 42), and may have a variable lateral extent that generally decreases with the vertical distance from a horizontal plane including the top surface of the carrier substrate 9.

[0086] Reference Figure 6E , the dielectric core layer 62L can be vertically recessed such that each remaining portion of the dielectric core layer has a top surface at or near a horizontal plane including the bottom surface of the topmost insulating layer 32. Each remaining portion of the dielectric core layer constitutes the dielectric core 62.

[0087] Reference Figure 6F , a doped semiconductor material having a doping of a second conductivity type can be deposited in each recessed region above the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be at 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 within the range, but smaller or larger dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.

[0088] Excess portions of the deposited semiconductor material doped with the second conductivity type and horizontal portions of the semiconductor channel layer 60L can be removed above the horizontal plane of the top surface including the top insulating layer 32T, for example, by chemical mechanical planarization (CMP) or a recess etching process. Each remaining portion of the doped semiconductor material doped with the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel layer 60L (doped with the first conductivity type) constitutes a vertical semiconductor channel 60.

[0089] Each portion of the layer stack including the memory material layer 54 retained in the corresponding memory opening 49 constitutes a memory film 50. In one embodiment, the memory film 50 can include an optional barrier dielectric layer 52, the memory material layer 54, and an optional dielectric liner layer 56. Each adjacent combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each combination of the sacrificial pedestal structure 11 (if present), the memory stack structure 55, the dielectric core 62, the optional core cavity 69 (if present), and the drain region 63 within the memory opening 49 constitutes a memory opening fill structure 58. Each memory opening fill structure 58 includes a corresponding vertical stack of memory elements, and the corresponding vertical stack can include multiple portions of the memory material layer 54 at the level of the sacrificial material layer 42 (or generally, at the level of a spacer material layer that can be formed as a conductive layer or subsequently at least partially replaced with a conductive layer). In an alternative embodiment, the support pillar structure 20 can be formed in the support opening 19 while the memory opening fill structure 58 is formed in the memory opening 49. In this case, the support pillar structure 20 includes the same materials as the memory opening fill structure 58.

[0090] Reference Figure 7A and Figure 7B illustrates a first exemplary structure after the memory opening fill structure 58 is formed within the memory opening 49. The memory opening fill structure 58 is located within the memory opening 49. Each of the memory opening fill structures 58 includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60.

[0091] Reference Figure 8A and Figure 8B, a dielectric material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) can be deposited over the alternating stack (32, 42) to form a contact-level dielectric layer 80. The thickness of the contact-level dielectric layer 80 can be in the range of 100 nm to 600 nm (such as 200 nm to 400 nm), but smaller and larger thicknesses can also be employed.

[0092] A photoresist layer (not shown) can be applied over the contact-level dielectric layer 80 and can be lithographically patterned to form elongated openings that extend laterally along a first horizontal direction hd1 between adjacent clusters of the memory opening fill structure 58. An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stack (32, 42), and the stepped dielectric material portion 65 and at least to the top surface of the carrier substrate 9. Lateral isolation trenches 79 that extend laterally along the first horizontal direction hd1 can be formed through the alternating stack (32, 42), the stepped dielectric material portion 65, and the contact-level dielectric layer 80. Each of the lateral isolation trenches 79 can include a respective pair of longitudinal sidewalls that are parallel to the first horizontal direction hd1 and extend vertically from the carrier substrate 9 to the top surface of the contact-level dielectric layer 80. The surface of the carrier substrate 9 can be physically exposed under each lateral isolation trench 79. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0093] Reference Figure 9 , an etchant that selectively etches the material of the sacrificial material layer 42 relative to the material of the insulating layer 32 can be introduced into the access trenches 79, for example, by using an isotropic etching process. Lateral grooves 43 are formed in the volume from which the sacrificial material layer 42 is removed. The removal of the sacrificial material layer 42 can be selective to the material of the insulating layer 32, the stepped dielectric material portion 65, and the outermost layer of the memory film 50. In one embodiment, the sacrificial material layer 42 can include silicon nitride, and the material of the insulating layer 32 and the stepped dielectric material portion 65 can include silicon oxide.

[0094] The etching process that selectively removes the second material with respect to the first material and the outermost layer of the memory film 50 can be a wet etching process using a wet etching solution, or can be a gas-phase (dry) etching process in which the etchant is introduced into the access trenches 79 in a gas phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process can be a wet etching process in which a first exemplary structure is immersed in a wet etching bath including phosphoric acid that selectively etches silicon nitride with respect to silicon oxide, silicon, and various other materials employed in the art. The support pillar structure 20, the stepped dielectric material portion 65, and the memory stack structure 55 provide structural support while the lateral grooves 43 are present in the volume previously occupied by the sacrificial material layer 42.

[0095] Each lateral groove 43 can be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each lateral groove 43 can be greater than the height of the lateral groove 43. A plurality of lateral grooves 43 can be formed in the volume of the second material from which the sacrificial material layer 42 has been removed. The memory opening in which the memory stack structure 55 is formed is referred to herein as a front opening or a front cavity as compared to the lateral groove 43.

[0096] Each of the plurality of lateral grooves 43 can extend substantially parallel to the top surface of the carrier substrate 9. The lateral groove 43 can be vertically defined by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each lateral groove 43 can have a uniform height throughout.

[0097] Reference Figure 10 , an outer barrier dielectric layer can optionally be formed ( Figure 10 not explicitly illustrated in). The outer barrier dielectric layer, if present, comprises a dielectric material that serves as a control gate dielectric for a control gate to be subsequently formed in the lateral groove 43. The outer barrier dielectric layer is optional in the case where the barrier dielectric layer 52 is present in each memory opening. In the case where the barrier dielectric layer 52 is omitted, the outer barrier dielectric layer is present.

[0098] At least one conductive material can be deposited in the lateral groove 43 by providing at least one reactive gas into the lateral groove 43 via the access trench 79. A metal barrier layer can be deposited in the lateral groove 43. The metal barrier layer comprises a conductive metal material that can serve as a diffusion barrier layer and / or an adhesion promoting layer for a subsequently deposited metal fill material. The metal barrier layer can comprise a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or can comprise a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer can be in the range of 2 nm to 8 nm (such as 3 nm to 6 nm), but smaller and larger thicknesses can also be employed. In one embodiment, the metal barrier layer can consist essentially of a conductive metal nitride such as TiN.

[0099] A metal fill material is deposited in the plurality of lateral grooves 43, on the sidewalls of at least one access trench 79, and over the top surface of the contact-level dielectric layer 80 to form a metal fill material layer. The metal fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal fill material layer can consist essentially of at least one elemental metal. The at least one elemental metal of the metal fill material layer can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal fill material layer can consist essentially of a single elemental metal. In one embodiment, a fluorine-containing precursor gas such as WF6 can be used to deposit the metal fill material layer. In one embodiment, the metal fill material layer can be a tungsten layer including a residual level of fluorine atoms as impurities. The metal fill material layer is spaced apart from the insulating layer 32 and the memory stack structure 55 by a metal barrier layer, which is a metal barrier layer that blocks the diffusion of fluorine atoms therethrough.

[0100] A plurality of conductive layers 46 can be formed in the plurality of lateral grooves 43, and a continuous metal material layer can be formed on the sidewalls of each access trench 79 and over the contact-level dielectric layer 80. Each conductive layer 46 includes a portion of the metal barrier layer and a portion of the metal fill material layer that are located between a vertically adjacent pair of dielectric material layers, such as a pair of insulating layers 32. The continuous metal material layer includes a continuous portion of the metal barrier layer and a continuous portion of the metal fill material layer that are located in the access trench 79 or above the contact-level dielectric layer 80.

[0101] By performing an isotropic etching process that etches at least one of the conductive materials of the continuous conductive material layer, the deposited metal material of the continuous conductive material layer is etched back from the sidewalls of each access trench 79 and from above the contact-level dielectric layer 80. Each remaining portion of the deposited metal material in the lateral grooves 43 constitutes a conductive layer 46. Each conductive layer 46 can be a wire structure. Thus, the sacrificial material layer 42 is replaced by the conductive layer 46. Generally, the conductive layer 46 can be formed by supplying a metal precursor gas into the lateral isolation trenches 79 and into the lateral grooves 43.

[0102] At least one topmost conductive layer 46 can include a drain-side select gate electrode. At least one bottommost conductive layer 46 can include a source-side select gate electrode. The remaining conductive layers 46 can include word lines. Each word line serves as a common control gate electrode for a plurality of vertical NAND strings (e.g., the memory opening fill structures 58).

[0103] Reference Figure 11A and Figure 11B, a dielectric fill material such as silicon oxide may be deposited in the lateral isolation trenches 79. The excess portion of the dielectric fill material may be removed from above the contact-level dielectric layer 80. Each remaining portion of the dielectric fill material that fills a corresponding one of the lateral isolation trenches 79 constitutes a lateral isolation trench fill structure 76, which may be a dielectric wall structure. In an alternative embodiment, an insulating spacer having a tubular configuration may be formed in the peripheral portion of each of the lateral isolation trenches 79, and a through-stack conductive via structure may be formed within a corresponding one of the insulating spacers. In this case, each lateral isolation trench fill structure 76 may include a combination of a through-stack conductive via structure and an insulating spacer that laterally surrounds the through-stack conductive via structure.

[0104] Contact via structures (88, 86) may be formed through the contact-level dielectric layer 80 and optionally through the stepped dielectric material portion 65. For example, a drain contact via structure 88 may be formed through the contact-level dielectric layer 80 over each drain region 63. A layer contact via structure 86 may be formed through the contact-level dielectric layer 80 and through the stepped dielectric material portion 65 over the conductive layer 46.

[0105] Reference Figure 12 , additional dielectric material layers and additional metal interconnect structures may be formed over the contact-level dielectric layer 80. The additional dielectric material layers may include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and / or at least one additional line-and-via-level dielectric layer. The additional metal interconnect structures may include metal via structures, metal line structures, and / or integrated metal line-and-via structures. The additional dielectric material layers formed over the contact-level dielectric layer 80 are referred to herein as the memory-side dielectric material layer 960. The additional metal interconnect structures are collectively referred to as the memory-side dielectric material layer 960. The memory-side dielectric material layer 960 includes a bit-line-level dielectric material layer that embeds bit lines, which are a subset of the memory-side metal interconnect structures 980.

[0106] Metal bonding pads (which are referred to herein as upper bonding pads 988) may be formed at the topmost level of the memory-side dielectric material layer 960. The upper bonding pads 988 may be electrically connected to the memory-side metal interconnect structures 980 and various nodes of the three-dimensional memory array including the conductive layer 46 and the memory opening fill structure 58. Thus, a memory die 900 may be provided.

[0107] A memory - side dielectric material layer 960 is formed over the alternating stack (32, 46). A memory - side metal interconnect structure 980 is embedded in the memory - side dielectric material layer 960. A memory - side bonding pad 988 may be embedded within the memory - side dielectric material layer 960, and specifically, within the top - most layer among the memory - side dielectric material layers 960. The memory - side bonding pad 988 may be electrically connected to the memory - side metal interconnect structure 980.

[0108] In one embodiment, the memory die 900 may include: a three - dimensional memory array located below a first dielectric material layer 110 and including an alternating stack (32, 46) of insulating layers 32 and conductive layers 46; a two - dimensional array of memory openings 49 that vertically extend through the alternating stack (32, 46); and a two - dimensional array of memory - opening fill structures 58 located in the two - dimensional array of memory openings 49 and including corresponding vertical stacks of memory elements and corresponding vertical semiconductor channels 60; and a two - dimensional array of contact via structures (such as drain contact via structures 88) located above the three - dimensional memory array and electrically connected to a corresponding one of the vertical semiconductor channels 60.

[0109] Reference Figure 13 , a logic die 700 may be provided. The logic die 700 includes a logic - side substrate 709, a peripheral circuit 720 located on the logic - side substrate 709 and including logic - side semiconductor devices (such as field - effect transistors), a logic - side metal interconnect structure 780 embedded within a logic - side dielectric material layer 760, and a logic - side bonding pad 778. The peripheral circuit 720 may be configured to control the operation of the memory array within the memory die 900. Specifically, the peripheral circuit 720 may be configured to drive various electrical components within the memory array, including but not limited to the conductive layer 46, the drain region 63, and source contact structures to be formed later. The peripheral circuit 720 may be configured to control the operation of the vertical stacks of memory elements in the memory array within the memory die 900.

[0110] Reference Figure 14 , the logic die 700 may be attached to the memory die 900, for example, by bonding the logic - side bonding pad 788 to the memory - side bonding pad 988 at a bonding interface. A wafer - to - wafer bonding process may be employed to perform the bonding between the memory die 900 and the logic die 700, in which a two - dimensional array of memory dies 900 is bonded to a two - dimensional array of logic dies 700 through a die - to - bond process or through a die - to - die bonding process. The logic - side bonding pad 788 within each logic die 700 may be bonded to the memory - side bonding pad 988 within a corresponding memory die 900.

[0111] Reference Figure 15A and Figure 15B, the carrier substrate 9 and the sacrificial base structure 11 may be removed, for example, by grinding, polishing, cleaving, an isotropic etching process and / or an anisotropic etching process. If a polishing process such as a chemical mechanical polishing process is used to remove the carrier substrate 9, the bottom insulating layer 32B may be used as a polishing stop material layer. If an etching process such as a wet etching process is used to remove the carrier substrate 9 and the sacrificial base structure 11, the bottom insulating layer 32B may be used as an etching stop material layer.

[0112] In one embodiment, at least the final step of at least one removal process for removing the carrier substrate 9 and the sacrificial base structure 11 may include a selective wet etching process that has selectivity to the dielectric material of the memory film 50 and the dielectric core 62 to etch the semiconductor material (e.g., silicon). In an illustrative example, the final step of at least one removal process may include a wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide ("hot TMY") or tetramethylammonium hydroxide (TMAH). The entirety of the carrier substrate 9 and the entirety of each of the sacrificial base structures 11 may be removed by the selective wet etching process. The back end surface of the support pillar structure 20 may be physically exposed when removing the carrier substrate 9.

[0113] In general, the process of removing the carrier substrate 9 may remove the first end portion of each of the memory opening filling structures 58. The first end portion of each memory opening filling structure 58 that is removed in conjunction with the process of removing the carrier substrate 9 may include the removal of the sacrificial base structure 11 in conjunction with the process. The entirety of the sacrificial base structure 11 may be removed in conjunction with the process of removing the carrier substrate 9. A recess 49R including the bottom portion of the memory opening 49 is formed after the sacrificial base structure 11 is removed. After the selective wet etching process, the end surface of the memory film 50 may be physically exposed in the recess 49R.

[0114] Figures 16A to 16F 1 is a sequential vertical cross-sectional view of a region of a first exemplary structure in a first configuration during formation of a channel cap layer structure according to a first embodiment of the present disclosure. The first exemplary structure is illustrated upside down, so that the bottom portion of each structural element is illustrated above the top portion of the corresponding structural element.

[0115] refer to Figure 16A The second end portion of each memory opening filling structure 58 exposed in the recess 49R may be removed by any suitable etch-back process. The width of the recess 49R may also be increased during the etch-back process. For example, the sidewalls of the recess 49R may become tapered so that the recess 49R is narrower at the memory opening filling structure 58 than at the exposed bottom surface of the bottommost insulating layer 32B.

[0116] Generally speaking, the end portions of each vertical semiconductor channel 60 can be removed such that each vertical semiconductor channel 60 has a tubular configuration with an opening at its end portion. The annular end face of the vertical semiconductor channel 60 can be fully formed between a first horizontal plane including the top surface of the bottommost insulating layer 32B and a second horizontal plane including the bottom surface of the bottommost insulating layer 32B.

[0117] Reference Figure 16B , an optional dielectric spacer layer 91 is formed over the bottom surface of the bottommost insulating layer 32B, the sidewalls of the grooves 49R in the bottommost insulating layer 32B, and the bottom surface of the memory opening filling structure 58 exposed in the grooves 49R. The dielectric spacer layer 91 can include any suitable insulating layer formed by a conformal deposition process, such as a silicon oxide layer.

[0118] Reference Figure 16C , the third end portion of each memory opening filling structure 58 and the dielectric spacer layer 91 can be removed by performing at least one etching process. The at least one etching process can include a reactive ion etching process followed by one or more wet etching processes. The at least one etching process removes the horizontal portion of the dielectric core 62 to expose the core cavity 69 in the groove. Each core cavity 69 is laterally surrounded by the remaining portion of the corresponding dielectric core 62 and is laterally surrounded by the corresponding vertical semiconductor channel 60. The dielectric spacer layer 91 helps to provide a tapered shape of the groove 49R extending into the core cavity 69. In one embodiment, the steps described above with respect to Figure 16B and Figure 16C can be cycled two or more times to achieve the structure shown in Figure 16C .

[0119] Reference Figure 16D , a selective semiconductor deposition process can be performed to grow semiconductor material from the physically exposed semiconductor surface of the vertical semiconductor channel 60. The selective semiconductor deposition process employs a concurrent or alternating flow of a reactive gas and an etchant gas during the deposition process. The reactive gas includes semiconductor precursor gases such as SiH4, SiH2Cl2, SiHCl3, Si2H6, Ge2H6, etc. In one embodiment, the reactive gas can include at least one silicon-containing precursor gas and the deposited semiconductor material can include silicon. In another embodiment, the reactive gas can include at least one germanium-containing precursor gas and the deposited semiconductor material can include germanium. In another embodiment, the reactive gas can include at least one silicon-containing precursor gas and at least one germanium-containing precursor gas, and the deposited semiconductor material can include silicon-germanium. Suitable doping gases (such as diborane, phosphine, or arsine) can optionally flow as needed. Thus, the semiconductor material can be intrinsic, p-type doped, or n-type doped.

[0120] During a selective semiconductor deposition process, the reaction rate of the reaction gas can be limited by the deposition temperature. In one embodiment, the deposition temperature is below 400 degrees Celsius, and a temperature such as 180 to 375 degrees Celsius can be used to avoid damage to the bonding pads in the bonding assembly of the logic die 700 and the memory die 900, and to limit the reaction rate. For example, in the art, epitaxial silicon growth on underlying silicon has been achieved at 180 degrees Celsius by PECVD deposition using silane and hydrogen as source gases. The nucleation rate of a semiconductor material on a semiconductor surface is higher than the nucleation rate of the semiconductor material on a dielectric surface because the incubation time of semiconductor atom clusters on the dielectric surface is longer than the incubation time of semiconductor atom clusters on the semiconductor surface (the incubation time is nearly zero). Therefore, the deposition rate of the semiconductor material on the semiconductor surface is higher than the deposition rate of the semiconductor material on the dielectric surface. The etching rate of an etchant gas is generally proportional to the flow rate of the etchant gas. According to one aspect of the present disclosure, the flow rate of the etchant gas is set such that the etching rate of the etchant gas is less than the deposition rate of the semiconductor material on the semiconductor surface and greater than the deposition rate of the semiconductor material on the dielectric surface. Under such process conditions, the deposited semiconductor material grows only from the physically exposed semiconductor surfaces of the vertical semiconductor channels 60 and not from any dielectric surfaces. Therefore, the semiconductor material can selectively grow only from the physically exposed surfaces of the vertical semiconductor channels 60.

[0121] The duration of the selective semiconductor deposition process can be selected such that the deposited portion of the semiconductor material plugs the bottom end of the corresponding vertical semiconductor channel 60 and forms the corresponding semiconductor portion 114. Generally speaking, the selective semiconductor deposition process can grow the semiconductor material from the physically exposed surfaces of each vertical semiconductor channel 60 while suppressing the growth of the semiconductor material from the dielectric surfaces. In one embodiment, each semiconductor portion 114 includes a portion of Si, Ge, or SiGe material that at least contacts the cylindrical surface segment of the inner sidewall of the corresponding vertical semiconductor channel 60.

[0122] In one embodiment, each vertical semiconductor channel 60 has a doping of a first conductivity type, and each semiconductor material portion (i.e., each semiconductor portion 114) may be undoped or may have a doping of the first conductivity type. In the case where the semiconductor portion 114 comprises an intrinsic semiconductor material or a semiconductor material having a doping of the first conductivity type and / or consists essentially of an intrinsic semiconductor material or a semiconductor material having a doping of the first conductivity type, the semiconductor portion 114 may act as a channel capping layer structure formed at the bottom end of the corresponding vertical semiconductor channel 60. In the case where the semiconductor portion 114 comprises a semiconductor material having a doping of a second conductivity type and / or consists essentially of a semiconductor material having a doping of the second conductivity type, the semiconductor portion 114 may act as a doped source region. The atomic concentration of the dopant of the first conductivity type or the second conductivity type may be in the range of 1.0×10 14 / cm 3 to 1.0×10 18 / cm 3 , but smaller or larger atomic concentrations may also be employed.

[0123] In one embodiment, each semiconductor portion 114 may plug an opening at the bottom end of the corresponding vertical semiconductor channel 60 such that the remaining portion of the core cavity 69 is surrounded by the corresponding dielectric core 62 and the semiconductor portion 114. Thus, the semiconductor portion 114 separates the core cavity 69 from the groove 49R. In one embodiment, each semiconductor portion 114 may contact an end segment of the corresponding dielectric core 62 that is exposed to the inner sidewall of the corresponding core cavity 69. In one embodiment, each semiconductor portion 114 may contact the corresponding memory film 50 and may be laterally spaced apart from each of the insulating layers 32 in the alternating stack (32, 46) except for the bottommost insulating layer 32B through the corresponding memory film 50.

[0124] Generally, each memory opening filling structure 58 may be located in a corresponding memory opening 49 and includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60 that laterally surrounds a corresponding core cavity 69 that does not contain any solid-phase material therein. In one embodiment, each vertical semiconductor channel 60 may have a tubular configuration, and each semiconductor portion 114 may be formed within an end portion of a cylindrical cavity 69 within the corresponding vertical semiconductor channel 60. Each semiconductor portion 114 may contact an end portion of the corresponding vertical semiconductor channel 60 and may have a top surface 14T that is exposed within the corresponding core cavity 69. In one embodiment, the top surface 14T of the semiconductor portion 114 includes a tapered convex surface that has a lowest point at its central region.

[0125] Reference Figure 16E, a recess etching process may be optionally performed to recess the semiconductor portion 114. The recess etching process may include an isotropic etching process such as a wet etching process, or may include an anisotropic etching process such as a reactive ion etching process. In one embodiment, the recess etching process may include a wet etching process using hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH). In one embodiment, the recess etching process may continue until the bottom surface 14B of the semiconductor portion 114 is positioned parallel to the bottommost conductive layer 46 serving as the bottom source side select gate electrode. For example, the bottom surface 14B of the semiconductor portion 114 may be located between a first horizontal plane HP1 including the bottom surface of the bottommost conductive layer 46S and a second horizontal plane HP2 including the top surface of the bottommost conductive layer 46S. The bottom surface 14B may be flat after the recess etching.

[0126] Reference Figure 16F , a source contact structure 224 may be formed on the bottom surface 14B of the semiconductor portion 114. In one embodiment, the source contact structure 224 may include at least one metal material and / or may be composed of at least one metal material. In an illustrative example, a metal barrier material may be conformally deposited directly on the bottom surface 14B of each of the semiconductor portions 114. The metal barrier material may include a metal nitride material such as titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride, and / or may include a metal carbide material such as titanium carbide, tantalum carbide, or tungsten carbide. The metal barrier material may be deposited by a conformal deposition process such as a chemical vapor deposition process. A metal barrier liner 224B may be formed on the physically exposed end faces of the semiconductor portion 114, the dielectric core 62, the vertical semiconductor channel 60, and the memory film 50, and on top of the bottommost insulating layer 32B.

[0127] A metal layer 224M may be formed on top of the metal barrier liner 224B. The metal layer may comprise any suitable metal such as tungsten, tantalum, titanium, molybdenum, cobalt, ruthenium, copper, etc. Subsequently, the metal layer 224M and the metal barrier liner 224B may be patterned, for example, by applying a photoresist layer on top of the metal layer 224M and patterning the photoresist layer and by removing the portions of the metal layer 224M and the metal barrier liner 224B not masked by the patterned portions of the photoresist layer. The source contact structure 224 may be formed. Subsequently, the photoresist layer may be removed, for example, by ashing.

[0128] In a first configuration, a source contact structure 224 may be formed on a semiconductor portion 114. In one embodiment, the source contact structure 224 may contact the bottom surface 14B of the semiconductor portion 114 and the bottom surface of the lowermost layer in the alternating stack (32, 46) (i.e., the bottom surface of the lowermost insulating layer 32B). In one embodiment, each of the vertical semiconductor channels 60 may have an annular end face contacting the source contact structure 224.

[0129] Figures 17A to 17D is a sequential vertical cross-sectional view of regions of a first exemplary structure during formation of a channel capping layer structure in a second configuration according to a first embodiment of the present disclosure.

[0130] Reference Figure 17A , illustrates regions of a first exemplary structure in a second configuration. The second configuration of the first exemplary structure at this processing step may be the same as the first configuration of the first exemplary structure illustrated in Figure 16D .

[0131] Reference Figure 17B , an ion implantation process may be performed to implant dopants of a first conductivity type or a second conductivity type into the semiconductor portion 114 and into an end portion of the vertical semiconductor channel 60 near the lowermost insulating layer 32B. The implanted ions may be activated by annealing (such as laser annealing). The entirety of each semiconductor portion 114 and an optional portion of the vertical semiconductor channel 60 near the semiconductor portion 114 are converted into a doped semiconductor portion 124 doped with a first conductivity type or a second conductivity type.

[0132] Reference Figure 17C , a recess etching process of Figure 16E is performed on the doped semiconductor portion 124.

[0133] Reference Figure 17D , the source contact structure 224 is formed on the doped semiconductor portion 124 as described above with respect to Figure 16F .

[0134] Figures 18A to 18C is a sequential vertical cross-sectional view of regions of a first exemplary structure during formation of a channel capping layer structure in a third configuration according to a first embodiment of the present disclosure.

[0135] Reference Figure 18A , the source contact structure 224 may be formed from Figure 16EThe first configuration of the first exemplary structure illustrated in [reference] results in a third configuration of the first exemplary structure. For example, a metal layer 231 comprising at least one metal selected from titanium, tungsten, nickel, cobalt, molybdenum, platinum, and / or palladium and / or consisting essentially of at least one metal selected from titanium, tungsten, nickel, cobalt, molybdenum, platinum, and / or palladium may be deposited on the bottom surface of 14B of the semiconductor portion 114 and on the bottom surface of the lowermost layer in the alternating stack (32, 46). The metal layer 231 may be deposited by a non-conformal deposition process such as a physical vapor deposition process or by a conformal deposition process such as a chemical vapor deposition process.

[0136] Reference Figure 18B , a thermal annealing process may be performed to induce a reaction between the semiconductor material (e.g., Si, Ge, or SiGe) of the semiconductor portion (114 or 124) and the metal in the metal layer 231. A metal-semiconductor alloy portion such as a metal silicide, metal germanide, or metal silicide-germanide may be formed by the reaction of the semiconductor material of the semiconductor portion 114 with the metal in the metal layer 231. Thus, the semiconductor portion 114 is transformed into a metal-semiconductor alloy portion 134. The portion 134 includes titanium, tungsten, nickel, cobalt, molybdenum, platinum, or palladium silicide, germanite, or silicogermanide.

[0137] Subsequently, the unreacted portion of the metal layer 231 may be removed by performing an etching process (such as a wet etching process) that selectively etches the metal layer 231 with respect to the metal-semiconductor alloy portion 134.

[0138] Reference Figure 18C , the processing steps described in [reference] may be performed to form a source contact structure 224 on the metal-semiconductor alloy portion 134. Figure 16F

[0139] In an alternative embodiment, the metal-semiconductor alloy portion 134 is formed by selective deposition. In this alternative embodiment, the metal deposition step, annealing step, and metal removal step described above with respect to [reference] and [reference] are omitted. Instead, at the step of [reference], a metal silicide, germanide, or silicide-germanide is selectively grown from the exposed portion of the vertical semiconductor channel rather than from the semiconductor portion 114. Subsequently, a recess etching step of [reference] is performed on the metal silicide, germanide, or silicide-germanide to form the metal-semiconductor alloy portion 134. Then, the processing steps described in [reference] may be performed to form a source contact structure 224 on the metal-semiconductor alloy portion 134, as shown in [reference]. Figure 18A and Figure 18B Figure 16D Figure 16E Figure 16F Figure 18C

[0140] Reference Figure 19 ​​​​​​, illustrates a first exemplary structure after the formation of the source contact structure 224. The Group-IV material portions (114, 124, 134) are located between the source contact structure 224 and the vertical semiconductor channel 60. The Group-IV material portions may include at least one element from Group IVA (also known as Group 14) of the periodic table, such as silicon and / or germanium. In one embodiment, the Group-IV material portions (114, 124, 134) include an intrinsic Si, Ge, or SiGe semiconductor portion 114. In another embodiment, the Group-IV material portions (114, 124, 134) include a doped Si, Ge, or SiGe doped semiconductor portion 124. In another embodiment, the Group-IV material portions (114, 124, 134) include a metal silicide, metal germanide, or metal silicide-germanide metal-semiconductor alloy portion 134.

[0141] Reference Figures 1 to 19 And according to a first embodiment of the present disclosure, a semiconductor structure includes: an alternating stack (32, 46) of an insulating layer 32 and a conductive layer 46; a memory opening 49 that vertically extends through the alternating stack (32, 46); a memory opening filling structure 58 that is located in the memory opening 49 and includes a memory film 50 and a vertical semiconductor channel 60 that laterally surrounds a core cavity 69 that does not contain any solid-phase material therein; a Group-IV material portion (114, 124, 134) that contacts an end portion of the vertical semiconductor channel 60 and is exposed in the core cavity 69; and a source contact structure 224 that contacts a bottom surface 14B of the Group-IV material portion (114, 124, 134) and a bottom surface of the lowermost layer in the alternating stack (32, 46).

[0142] In one embodiment, the memory opening filling structure 58 further includes a dielectric core 62 that laterally surrounds the core cavity 69 and is laterally surrounded by the vertical semiconductor channel 60. In one embodiment, the Group-IV material portion (114, 124, 134) contacts an end segment of an inner sidewall of the dielectric core 62 that is exposed to the core cavity 69. In one embodiment, a lateral thickness of the dielectric core 62 measured between an inner sidewall and an outer sidewall of the dielectric core 62 increases with a vertical distance from the source contact structure 224 around an end portion of the core cavity 69.

[0143] In one embodiment, a top surface 14T of the Group-IV material portion (114, 124, 134) includes a tapered convex surface that has a lowest point at its central region.

[0144] In one embodiment, the vertical semiconductor channel 60 has a tubular configuration, and the Group-IV material-containing portions (114, 124, 134) are located within end portions of a cylindrical cavity within the vertical semiconductor channel 60.

[0145] In one embodiment, the Group-IV material-containing portion comprises at least one of silicon or germanium. In one embodiment, the Group-IV material-containing portion includes a semiconductor portion 114 consisting essentially of silicon, germanium, or silicon-germanium.

[0146] In another embodiment, the Group-IV material-containing portion includes a doped semiconductor portion 124 consisting essentially of silicon, germanium, or silicon-germanium doped with at least one p-type or n-type dopant. In one embodiment, the vertical semiconductor channel 60 has a doping of a first conductivity type; and the doped semiconductor portion 124 has a doping of the first conductivity type. Alternatively, the vertical semiconductor channel 60 has a doping of a first conductivity type; and the doped semiconductor portion 124 has a doping of a second conductivity type opposite to the first conductivity type.

[0147] In another embodiment, the Group-IV material-containing portion includes a metal-semiconductor alloy portion 134. The metal-semiconductor alloy portion 134 comprises a metal silicide, a metal germanide, or a metal silicide-germanide. In one embodiment, the annular end face of the vertical semiconductor channel 60 contacts the source contact structure 224.

[0148] In a first embodiment, the Group-IV material-containing portions (114, 124, 134) (e.g., the channel capping layer structure) can be formed at a relatively low temperature (e.g., below 400 degrees Celsius) to avoid negatively affecting the quality of the bond between the bonding pads and the bond between the logic die 700 and the memory die 900. The channel capping layer structure provides a low contact resistance between the source contact structure 224 and the vertical semiconductor channel 60. Further, the channel capping layer structure extends into the alternating stack at least to the vertical level of the bottommost source-side select gate electrode 46 to improve hole injection from the source contact structure 224 into the vertical semiconductor channel 60 during a gate-induced leakage-type erase operation of the memory device.

[0149] Reference Figure 20A and Figure 20B According to a second exemplary structure of a second embodiment of the present disclosure, it can be associated with Figure 5A and Figure 5Bis the same as the first exemplary structure illustrated therein. In one embodiment, the etch distance of the memory opening 49 into the recess in the carrier substrate 9 may be no greater than the sum of the thicknesses of the memory film 50 and the vertical semiconductor channel 60 to be formed subsequently in each memory opening 49. Alternatively, the etch distance of the memory opening 49 into the recess in the carrier substrate 9 may be greater than the sum of the thicknesses of the memory film 50 and the vertical semiconductor channel 60 to be formed subsequently in each memory opening 49.

[0150] Reference Figures 21A to 21D , the processing steps described therein may be executed to form a memory opening fill structure 58 within each memory opening 49, but not to form the sacrificial pedestal structure 11. Figures 6B to 6F

[0151] Reference Figure 21A Figure 20A illustrates Figure 20B and the memory opening 49 in the second exemplary structure illustrated in

[0152] Figure 22B Reference Figure 6B , the processing steps described therein may be executed to sequentially deposit an optional barrier dielectric layer 52, a memory material layer 54, an optional dielectric liner layer 56, a semiconductor channel material layer 60L, and a dielectric core layer 62L. During the processing steps for forming the second exemplary structure, Figure 6C Figure 6D the formation of the sacrificial pedestal structure 11 illustrated in Figure 6A is omitted.

[0153] Reference to FIG. 22C, the processing steps described therein may be executed to form a dielectric core 62 within each memory opening 49. Figure 6E

[0154] Reference to FIG. 22D, the processing steps described therein may be executed to form a memory opening fill structure 58 within each memory opening 49. Figure 6F

[0155] Reference Figure 22A and Figure 22B illustrates the second exemplary structure after the formation of the memory opening fill structure 58.

[0156] Reference Figure 23A and Figure 23B Figure 8A Figure 8B the processing steps described therein may be executed to form a contact-level dielectric layer 80 and a lateral isolation trench 79.

[0157] Reference Figure 24 Figure 9 ​​​​​​​​The described processing steps are performed to form the laterally extending cavity 43.

[0158] Reference Figure 25 and Figure 10 The described processing steps are performed to form the conductive layer 46.

[0159] Reference Figure 26A and Figure 26B and Figure 11A and Figure 11B The described processing steps are performed to form the lateral isolation trench fill structure 76, the layer contact via structure 86, and the drain contact via structure 88.

[0160] Reference Figure 27 and Figure 12 The described processing steps are performed to form the memory die 900.

[0161] Reference Figure 28 and Figure 14 The described processing steps are performed to form the bonding assembly of the logic die 700 to the memory die 900.

[0162] Reference Figure 29A and Figure 29B and Figure 15A and Figure 15B The described processing steps are performed to selectively remove the carrier substrate 9 with respect to the bottommost insulating layer 32B. In one embodiment, the carrier substrate 9 can be removed, for example, by grinding, polishing, cleaving, isotropic etching processes, and / or anisotropic etching processes. In one embodiment, at least the final step of at least one removal process for removing the carrier substrate 9 can include a selective wet etching process that selectively etches semiconductor materials with respect to the dielectric materials of the bottommost insulating layer 32B, the memory film 50, and the dielectric core 62. In an illustrative example, the final step of at least one removal process can include a wet etching process using hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH). The entire carrier substrate 9 can be removed by the selective wet etching process. The back end face of the support pillar structure 20 can be physically exposed when the carrier substrate 9 is removed. The end face of the memory film 50 can be physically exposed after the selective wet etching process. The end portions of the memory opening fill structure 58 can protrude outward from a horizontal plane of the physically exposed planar bottom surface including the bottommost insulating layer 32B.

[0163] Reference Figure 30A and Figure 30B, an optional chemical mechanical polishing process may be performed to remove any portion of the memory opening fill structure 58 that protrudes outward from a horizontal plane of the physically exposed planar bottom surface including the bottommost insulating layer 32B. The remaining portion of the memory opening fill structure 58 may have a physically exposed planar surface coplanar with the bottom surface of the bottommost insulating layer 32B. According to an embodiment of the present disclosure, the physically exposed surface of the memory opening fill structure 58 may include the end face of the vertical semiconductor channel 60. In one embodiment, each physically exposed end face of the vertical semiconductor channel 60 may include a planar horizontal surface that does not contain any openings therein. For example, each physically exposed end face of the vertical semiconductor channel 60 may be a circular horizontal surface.

[0164] Figures 31A to 31D is a sequential vertical cross-sectional view of a region of a first configuration of a second exemplary structure during the formation of the backside semiconductor capping layer structure 111 and the source contact structure according to a second embodiment of the present disclosure.

[0165] Reference Figure 31A , a selective semiconductor deposition process may be performed to grow semiconductor material from the physically exposed semiconductor surface of the vertical semiconductor channel 60. The selective semiconductor deposition process employs a concurrent or alternating flow of a reactive gas and an etchant gas during the deposition process. The reactive gas includes semiconductor precursor gases such as SiH4, SiH2Cl2, SiHCl3, Si2H6, Ge2H6, etc. In one embodiment, the reactive gas may include at least one silicon-containing precursor gas, and the deposited semiconductor material may include silicon. Suitable doping gases (such as diborane, phosphine, or arsine) may optionally flow as needed. In one embodiment, the selective semiconductor deposition process is performed at a temperature below 400 degrees Celsius (such as 180 degrees Celsius to 375 degrees Celsius) to avoid damaging the bonding pads.

[0166] The deposited portion of the silicon-containing semiconductor material forms the corresponding backside semiconductor capping layer structure 111. The backside semiconductor capping layer structure 111 may comprise a Group IV (i.e., Group IVA) semiconductor material such as Si, Ge, or SiGe. Generally speaking, the selective semiconductor deposition process may grow silicon-containing semiconductor material from the physically exposed surface of each vertical semiconductor channel 60 while suppressing the growth of semiconductor material from the dielectric surface. In one embodiment, each backside semiconductor capping layer structure 111 includes a semiconductor material portion that contacts the entirety of the end face of the vertical semiconductor channel 60, covers the entirety of the annular end face of the memory film 50, and covers the annular surface segment of the backside surface of the bottommost insulating layer 32B.

[0167] Generally, each back semiconductor cap layer structure 111 is formed by directly depositing a semiconductor material on the bottom surface of the corresponding vertical semiconductor channel 60. In one embodiment, the back semiconductor cap layer structure 111 can be formed by performing a selective semiconductor deposition process that grows the semiconductor material from the bottom surface of the vertical semiconductor channel 60 while suppressing the growth of the semiconductor material from the bottom surface of the bottommost insulating layer within the alternating stack (32, 46). In one embodiment, the bottom surface of each vertical semiconductor channel 60 may be free of any openings therein. In one embodiment, the entirety of the interface between the memory opening fill structure 58 and the back semiconductor cap layer structure 111 lies in a horizontal plane. The thickness of the planar portion of each back semiconductor cap layer structure 111 can be in the range of 20 nm to 200 nm (such as 40 nm to 100 nm), although smaller and larger thicknesses can also be employed.

[0168] In one embodiment, the top surface 111T of each back semiconductor cap layer structure 111 can be in contact with the bottom surface of the vertical semiconductor channel 60. In one embodiment, the entirety of the top surface of each back semiconductor cap layer structure 111 lies in a horizontal plane that includes the bottom surface of the bottommost insulating layer within the alternating stack (32, 46). In one embodiment, the annular bottom surface of each memory film 50 can be in contact with the annular surface segment of the top surface of the corresponding back semiconductor cap layer structure 111. In one embodiment, the contact region between the back semiconductor cap layer structure 111 and the vertical semiconductor channel 60 includes the entire region that is laterally enclosed by the perimeter of the bottom surface of the vertical semiconductor channel 60.

[0169] In one embodiment, each back semiconductor cap layer structure 111 can include a contoured bottom surface 111B. In one embodiment, each point on the contoured bottom surface of the back semiconductor cap layer structure 111 can be equidistant from the corresponding nearest-side point on the bottom surface of the vertical semiconductor channel 60 that is in contact with the back semiconductor cap layer structure 111. In one embodiment, the contoured bottom surface 111B includes a horizontal plane bottom surface segment and a convexly tapered annular surface segment that connects the perimeter of the horizontal plane bottom surface segment to the perimeter of the top surface of the back semiconductor cap layer structure 111.

[0170] In one embodiment, the backside semiconductor cap layer structure 111 may be formed as an extension of the vertical semiconductor channel 60. In this case, the vertical semiconductor channel 60 has a doping of a first conductivity type, and the backside semiconductor cap layer structure 111 has a doping of the first conductivity type. In the case where the backside semiconductor cap layer structure 111 comprises a semiconductor material having a doping of the first conductivity type and / or consists essentially of a semiconductor material having a doping of the first conductivity type, the atomic concentration of the dopant of the first conductivity type in the backside semiconductor cap layer structure 111 may be in the range of 1.0×10 14 / cm 3 to 1.0×10 18 / cm 3 , but smaller and larger atomic concentrations may also be employed.

[0171] In one embodiment, the backside semiconductor cap layer structure 111 may be formed as the semiconductor portion of the source contact structure. In this case, the vertical semiconductor channel 60 has a doping of a first conductivity type, and the backside semiconductor cap layer structure 111 has a doping of a second conductivity type opposite to the first conductivity type. In the case where the backside semiconductor cap layer structure 111 comprises a semiconductor material having a doping of the second conductivity type and / or consists essentially of a semiconductor material having a doping of the second conductivity type, the atomic concentration of the dopant of the second conductivity type in the backside semiconductor cap layer structure 111 may be in the range of 5.0×10 19 / cm 3 to 2.0×10 21 / cm 3 , but smaller and larger atomic concentrations may also be employed.

[0172] Referring Figure 31B , a metal layer 113 may be formed on the bottom surface of each backside semiconductor cap layer structure 111 by performing a selective metal deposition process. The selective metal deposition process is a metal deposition process that grows metal on a semiconductor surface while suppressing the deposition of metal on a dielectric surface. According to an embodiment of the present disclosure, the metal deposited by the selective metal deposition process includes a metal that forms a metal-semiconductor alloy (such as a metal silicide, germanide, or silicide-germanide). For example, the metal may be tungsten, cobalt, titanium, molybdenum, or ruthenium.

[0173] The selective metal deposition process may include a chemical vapor deposition process or an atomic layer deposition process that employs a metal precursor gas that nucleates on a metal surface or a semiconductor surface and does not nucleate on a dielectric surface. In one embodiment, the metal may be ruthenium that can be selectively deposited on silicon at a temperature of 250 degrees Celsius or lower using selective atomic layer deposition. Alternatively, an etchant gas may flow concurrently or alternately with the metal precursor gas to etch back any portion of the metal material that has nucleated in small clusters on a physically exposed dielectric surface, such as the physically exposed back surface of the bottommost insulating layer 32B. The metal precursor gas and the optional etchant gas may be selected depending on the type of metal deposited by the selective metal deposition process. The thickness of the metal layer 113 is selected such that the entirety of the metal layer 113 can be consumed during a subsequent metallization process. For example, the thickness of the metal layer 113 may be in the range of 5 nm to 80 nm, such as 10 nm to 40 nm, although smaller and larger thicknesses may also be employed. A two-dimensional array of discrete metal layers 113 may be formed over a two-dimensional array of memory opening fill structures 58. The discrete metal layers 113 may be laterally spaced apart from each other without direct contact therebetween.

[0174] Reference Figure 31C , an annealing process may be performed to induce a reaction of each metal layer 113 with a surface portion of the backside semiconductor capping layer structure 111. Any suitable annealing may be performed, such as laser annealing, flash lamp annealing, or furnace annealing. In one embodiment, the annealing is performed at a temperature below 450 degrees Celsius. A metal-semiconductor alloy structure 116 is formed on each remaining portion of the backside semiconductor capping layer structure 111. In one embodiment, the metal-semiconductor alloy structure 116 may include tungsten silicide, tungsten germanide, or tungsten silicogermanide, titanium silicide, titanium germanide, or titanium silicogermanide, cobalt silicide, cobalt germanide, or cobalt silicogermanide, molybdenum silicide, molybdenum germanide, or molybdenum silicogermanide, or ruthenium silicide, ruthenium germanide, or ruthenium silicogermanide. The thickness of each metal-semiconductor alloy structure 116 may be in the range of 8 nm to 100 nm, such as 16 nm to 50 nm, although smaller or larger thicknesses may also be employed. In one embodiment, each metal-semiconductor alloy structure 116 includes a contoured bottom surface 111B and an annular top surface 116T that contacts an annular surface segment of the bottom surface of the bottommost insulating layer 32B of the alternating stack (32, 46) in a horizontal plane.

[0175] Reference Figure 31D, a back conductive layer 234 comprising at least one metallic material may be formed over the back surface of the metal-semiconductor alloy structure 116 and the bottommost insulating layer 32B. In one embodiment, the back conductive layer 234 may comprise any material that may be used for the source contact structure 224 described above with reference to the first exemplary structure. In such a case, the back conductive layer 234 may include a stack of a metal barrier layer (such as titanium nitride, tantalum nitride, tungsten nitride or molybdenum nitride, titanium carbide, tantalum carbide or tungsten carbide) and a metal layer (such as tungsten, tantalum, titanium, molybdenum, cobalt, ruthenium, copper, etc.). The back conductive layer 234 may be patterned, for example, by applying a photoresist layer and patterning the photoresist layer to cover the memory array region 100 without covering the contact region 300 and by performing an etching process that etches the back conductive layer 234 using the patterned photoresist layer as an etch mask. The patterned photoresist layer may then be removed, for example, by ashing. A source contact structure is formed that includes the back conductive layer 234 and the metal-semiconductor alloy structure 116. In the case where the back semiconductor capping layer structure 111 is doped with a dopant of a second conductivity type opposite to the first conductivity type of the vertical semiconductor channel 60, the back semiconductor capping layer structure 111 includes a doped source region.

[0176] Reference Figure 31E , illustrates an alternative embodiment of a first configuration of a second exemplary structure, which may be obtained from the first configuration of the second exemplary structure illustrated in Figure 20A and Figure 20B by increasing the over-etch depth of the memory opening 49 at the processing steps of Figure 30A and Figure 30B and / or by increasing the etch depth during the etching step at the processing steps of Figure 31E . In such a case, the planar horizontal bottom portion of each vertical semiconductor channel 60 may be removed at the processing steps of Figure 30A and Figure 30B . Each physically exposed surface of the vertical semiconductor channel 60 may be an annular surface having an inner perimeter and an outer perimeter. In one embodiment, each memory opening fill structure 58 includes a dielectric core 62 that is laterally surrounded by the vertical semiconductor channel 60 and has a bottom surface that contacts a circular segment of the top surface 111T of the back semiconductor capping layer structure 111.

[0177] Figure 32A and Figure 32B are sequential vertical cross-sectional views of regions of a second configuration of a second exemplary structure during the formation of the back semiconductor capping layer structure 111 and the source contact structure according to a second embodiment of the present disclosure.

[0178] Reference Figure 32A, the second configuration of the second exemplary structure can be derived from the first configuration of the second exemplary structure illustrated in Figure 31A by directly forming a metal-semiconductor alloy structure 126 on each back-side semiconductor capping layer structure 111. In this case, the metal-semiconductor alloy structure 126 can be formed by selectively growing a metal-semiconductor alloy material. For example, the metal-semiconductor alloy structure 126 can include molybdenum silicide, molybdenum germanide, or molybdenum silicogermanide, titanium silicide, titanium germanide, or titanium silicogermanide, tungsten silicide, tungsten germanide, or tungsten silicogermanide, or cobalt silicide, cobalt germanide, or cobalt silicogermanide, and / or can consist essentially of molybdenum silicide, molybdenum germanide, or molybdenum silicogermanide, titanium silicide, titanium germanide, or titanium silicogermanide, tungsten silicide, tungsten germanide, or tungsten silicogermanide, or cobalt silicide, cobalt germanide, or cobalt silicogermanide. A combination of a metal precursor gas, a semiconductor precursor gas (such as silane, disilane, germane, etc.), and an optional etchant gas can be used to perform the selective growth of the metal-semiconductor alloy material. For example, molybdenum silicide can be selectively grown on silicon at a temperature of 120 degrees Celsius via atomic layer deposition using a molybdenum hexafluoride source and a disilane source. The thickness of the metal-semiconductor alloy structure 126 can be in the range of 8 nm to 100 nm (such as 16 nm to 50 nm), but smaller or larger thicknesses can also be employed.

[0179] Reference Figure 32B , the processing steps described in Figure 31D can be performed to form the back-side conductive layer 234. A source contact structure is formed, which includes the back-side conductive layer 234 and the metal-semiconductor alloy structure 126.

[0180] Reference Figure 32C , an alternative embodiment of the second configuration of the second exemplary structure is illustrated, which can be derived from the second configuration of the second exemplary structure illustrated in Figure 20A and Figure 20B by increasing the over-etch depth of the memory opening 49 during the processing steps of Figure 30A and Figure 30B and / or by increasing the etch depth during the etching step of the processing steps of Figure 32B . In this case, the planar horizontal bottom portion of each vertical semiconductor channel 60 can be removed during the processing steps of Figure 30A and Figure 30B . Each physically exposed surface of the vertical semiconductor channel 60 can be an annular surface having an inner perimeter and an outer perimeter. In one embodiment, each memory opening fill structure 58 includes a dielectric core 62 that is laterally surrounded by the vertical semiconductor channel 60 and has a bottom surface that contacts a circular segment of the top surface 111T of the back-side semiconductor capping layer structure 111.

[0181] Figures 33A to 33Dis a vertical sectional view of a region of a third configuration of a second exemplary structure during the formation of a back semiconductor cap layer structure 111 and a source contact structure according to a second embodiment of the present disclosure.

[0182] Reference Figure 33A , the third configuration of the second exemplary structure can be derived from the first configuration of the second exemplary structure illustrated in Figure 31A by depositing a metal layer 133 on each back semiconductor cap layer structure 111 via a non-selective deposition process. The metal layer 133 includes any metal that can form a metal-semiconductor alloy when reacting with the semiconductor material of the back semiconductor cap layer structure 111. For example, the metal layer 133 may contain at least one metal selected from tungsten, titanium, cobalt, molybdenum, ruthenium, nickel, platinum, palladium, etc. and / or may consist essentially of at least one metal selected from tungsten, titanium, cobalt, molybdenum, ruthenium, nickel, platinum, palladium, etc. The metal layer 133 can be deposited by a non-selective deposition process (i.e., a deposition process that deposits the same amount of material regardless of the material composition of the underlying surface). For example, the metal layer 133 can be deposited by physical vapor deposition (PVD) or non-selective chemical vapor deposition (CVD). The thickness of the metal layer 133 can be in the range of 5 nm to 80 nm (such as 10 nm to 40 nm), but smaller and larger thicknesses can also be employed. The metal layer 133 can be formed as a continuous metal layer that contacts the back surfaces of a two-dimensional array of back semiconductor cap layer structures 111.

[0183] Reference Figure 33B, the annealing process described above can be performed to react multiple portions of the metal layer 133 with the back semiconductor capping layer structure 111 of the semiconductor capping layer structure 111 to form a metal-semiconductor alloy structure 136 on each remaining portion of the back semiconductor capping layer structure 111. In one embodiment, the metal-semiconductor alloy structure 136 can include tungsten silicide, tungsten germanide, or tungsten silicogermanide, titanium silicide, titanium germanide, or titanium silicogermanide, cobalt silicide, cobalt germanide, or cobalt silicogermanide, ruthenium silicide, ruthenium germanide, or ruthenium silicogermanide, molybdenum silicide, molybdenum germanide, or molybdenum silicogermanide, nickel silicide, nickel germanide, or nickel silicogermanide, platinum silicide, platinum germanide, or platinum silicogermanide, or palladium silicide, palladium germanide, or palladium silicogermanide or a combination thereof. For example, platinum, nickel, and cobalt can react with silicon at temperatures below 450 degrees Celsius (such as 250 degrees Celsius to 400 degrees Celsius for platinum, 300 degrees Celsius to 400 degrees Celsius for cobalt, and 400 degrees Celsius to 440 degrees Celsius for nickel) to form silicides. The thickness of each metal-semiconductor alloy structure 136 can be in the range of 8 nm to 100 nm (such as 16 nm to 50 nm), but smaller or larger thicknesses can also be employed. In one embodiment, each metal-semiconductor alloy structure 136 includes an annular top surface that contacts an annular surface segment of the bottom surface of the bottommost insulating layer 32B of the alternating stack (32, 46) in a horizontal plane. Unreacted portions of the plane of the metal layer 133 can be present on the back surface of the bottommost insulating layer 133.

[0184] Reference Figure 33C , a wet etching process can be performed that selectively etches the remaining portion of the metal layer 133 with respect to the metal-semiconductor alloy material of the metal-semiconductor alloy structure 136 and the bottommost insulating layer 32B. The remaining portion of the metal layer 133 can be removed, and multiple portions of the back surface of the bottommost insulating layer 32B can be physically exposed.

[0185] Reference Figure 33D , the processing steps described in reference Figure 31D can be performed to form the back conductive layer 234. A source contact structure is formed that includes the back conductive layer 234 and the metal-semiconductor alloy structure 136.

[0186] Reference Figure 33E , an alternative embodiment of the third configuration of the second exemplary structure is illustrated, which can be derived from the third configuration of the second exemplary structure illustrated in Figure 20A and Figure 20B by increasing the over-etch depth of the memory opening 49 at the processing steps of Figure 30A and Figure 30B and / or by increasing the etch depth during the etching step at the processing steps of Figure 33D . In this case, it can be atFigure 30A and Figure 30B At the processing step of Figure 30B , the planar horizontal bottom portion of each vertical semiconductor channel 60 is removed. Each physically exposed surface of the vertical semiconductor channel 60 may be an annular surface having an inner perimeter and an outer perimeter. In one embodiment, each memory opening fill structure 58 includes a dielectric core 62 that is laterally surrounded by the vertical semiconductor channels 60 and has a bottom surface that is a circular segment of a top surface that contacts a back semiconductor capping layer structure 111.

[0187] Figure 34A and Figure 34B is a sequential vertical cross-sectional view of a region of a fourth configuration of a second exemplary structure during the formation of a back semiconductor capping layer structure 111 and a source contact structure according to a second embodiment of the present disclosure.

[0188] Referring Figure 34A to Figure 34A , the fourth configuration of the second exemplary structure can be derived from the first configuration of the second exemplary structure illustrated in Figure 31A by depositing a back conductive layer 244 that includes a material that can form a metal-semiconductor alloy when reacted with the semiconductor material of the back semiconductor capping layer structure 111. In this case, the back conductive layer 244 may include at least one metal selected from tungsten, titanium, cobalt, molybdenum, ruthenium, nickel, platinum, palladium, etc. and / or may consist essentially of at least one metal selected from tungsten, titanium, cobalt, molybdenum, ruthenium, nickel, platinum, palladium, etc. The back conductive layer 244 can be deposited by a non-selective deposition process (i.e., a deposition process that deposits the same amount of material regardless of the material composition of the underlying surface). For example, the back conductive layer 244 can be deposited by physical vapor deposition (PVD) or non-selective chemical vapor deposition (CVD). The thickness of the back conductive layer 244 can be in the range of 100 nm to 400 nm (such as 150 nm to 300 nm), but smaller and larger thicknesses can also be employed. The back conductive layer 244 can be formed as a continuous metal layer that contacts the back surface of a two-dimensional array of the back semiconductor capping layer structure 111.

[0189] Referring Figure 34B ​​, the annealing process described above can be performed to react multiple portions of the back conductive layer 244 with corresponding surface portions of the overlying back semiconductor capping layer structure 111 to form a metal-semiconductor alloy structure 146. The metal-semiconductor alloy structure 146 can include tungsten silicide, tungsten germanide, or tungsten silicogermanide, titanium silicide, titanium germanide, or titanium silicogermanide, cobalt silicide, cobalt germanide, or cobalt silicogermanide, ruthenium silicide, ruthenium germanide, or ruthenium silicogermanide, molybdenum silicide, molybdenum germanide, or molybdenum silicogermanide, nickel silicide, nickel germanide, or nickel silicogermanide, platinum silicide, platinum germanide, or platinum silicogermanide, or palladium silicide, palladium germanide, or palladium silicogermanide or a combination thereof. The thickness of each metal-semiconductor alloy structure 146 can be in the range of 8 nm to 100 nm (such as 16 nm to 50 nm), but smaller or larger thicknesses can also be employed. In one embodiment, each metal-semiconductor alloy structure 146 includes an annular top surface that contacts an annular surface segment of the bottom surface of the bottommost insulating layer 32B of the alternating stack (32, 46) in a horizontal plane. The unreacted portions of the back conductive layer 244 constitute a continuous metal layer that contacts the back surface of the bottommost insulating layer 32B. A source contact structure is formed, which includes the back conductive layer 234 and the metal-semiconductor alloy structure 146.

[0190] Reference Figure 34C , an alternative embodiment of the fourth configuration of the second exemplary structure is illustrated, which can be obtained from the fourth configuration of the second exemplary structure illustrated in Figure 20A and Figure 20B by increasing the over-etch depth of the memory opening 49 at the processing steps of Figure 30A and Figure 30B and / or by increasing the etch depth during the etching step at the processing steps of Figure 34B . In this case, the planar horizontal bottom portions of each vertical semiconductor channel 60 can be removed at the processing steps of Figure 30A and Figure 30B . Each physically exposed surface of the vertical semiconductor channel 60 can be an annular surface having an inner perimeter and an outer perimeter. In one embodiment, each memory opening filling structure 58 includes a dielectric core 62 that is laterally surrounded by the vertical semiconductor channel 60 and has a bottom surface that contacts a circular segment of the top surface of the back semiconductor capping layer structure 111.

[0191] Figures 35A to 35C is a sequential vertical cross-sectional view of a region of the fifth configuration of the second exemplary structure during the formation of the back semiconductor capping layer structure 111 and the source contact structure according to a second embodiment of the present disclosure.

[0192] Reference Figure 35A, the back semiconductor cap structure 111 of the fifth configuration of the second exemplary structure can be formed by uniformly non-selectively depositing semiconductor material directly on the physically exposed surfaces of the vertical semiconductor channels 60 and the back surface of the bottommost insulating layer 32B. Therefore, the back semiconductor cap structure 111 of the fifth configuration of the second exemplary structure can be formed as a continuous semiconductor material layer having a uniform thickness throughout, and can have the same composition and optional doping as the back semiconductor cap structures 111 of the other configurations of the second exemplary structure previously described. The back semiconductor cap structure 111 is formed as a semiconductor material layer that covers all physically exposed portions of the bottom surface of the bottommost insulating layer 32B within the alternating stack (32, 46). The thickness of the planar portion of each back semiconductor cap structure 111 can be in the range of 20nm to 200nm (such as 40nm to 100nm), but smaller and larger thicknesses can also be used.

[0193] The metal layer 133 may be deposited on the back surface of the back semiconductor cap structure 111. The metal layer 133 includes any metal that can form a metal-semiconductor alloy when reacting with the semiconductor material of the back semiconductor cap structure 111. For example, the metal layer 133 may include at least one metal selected from tungsten, titanium, cobalt, molybdenum, ruthenium, nickel, platinum, palladium, etc. and / or may be substantially composed of at least one metal selected from tungsten, titanium, cobalt, molybdenum, ruthenium, nickel, platinum, palladium, etc. The metal layer 133 may be deposited by a non-selective deposition process or a selective deposition process. For example, the metal layer 133 may be deposited by physical vapor deposition (PVD) or non-selective chemical vapor deposition (CVD). The thickness of the metal layer 133 may be in the range of 5nm to 80nm (such as 10nm to 40nm), but smaller and larger thicknesses may also be used. The metal layer 133 may be formed as an integral continuous metal layer contacting the back surface of the back semiconductor cap structure 111.

[0194] refer to Figure 35B , executable reference Figure 33B Specifically, the annealing process described above may be performed to react the metal layer 133 with the surface portion of the back semiconductor cap layer structure 111 to form a metal-semiconductor alloy structure 136 on the back semiconductor cap layer structure 111. In one embodiment, the metal-semiconductor alloy structure 136 may include tungsten silicide, tungsten germanium or tungsten germanium silicon, titanium silicide, titanium germanium or titanium germanium silicon, cobalt silicide, cobalt germanium or cobalt germanium silicon, ruthenium silicide, ruthenium germanium or ruthenium germanium silicon, molybdenum silicide, molybdenum germanium or molybdenum germanium silicon, nickel silicide, nickel germanium or nickel germanium silicon, platinum silicide, platinum germanium or platinum germanium silicon, or palladium silicide, palladium germanium or palladium germanium silicon, or a combination thereof.

[0195] In this case, the metal-semiconductor alloy structure 136 includes a planar metal-semiconductor alloy layer that is vertically spaced apart from the bottommost insulating layer 32B by a backside semiconductor capping layer structure 111. In this case, the semiconductor capping layer structure 111 includes a semiconductor material layer having a uniform thickness that contacts a two-dimensional array of vertical semiconductor channels 60. The metal-semiconductor alloy structure 136 can be formed as a continuous layer having a uniform thickness throughout. The thickness of the metal-semiconductor alloy structure 136 can range from 8 nm to 100 nm (such as 16 nm to 50 nm), but smaller or larger thicknesses can also be employed.

[0196] Reference Figure 35C , the reference can be executed Figure 31D The described processing steps to form the backside conductive layer 234. A source contact structure is formed that includes the backside conductive layer 234 and the metal-semiconductor alloy structure 136.

[0197] Reference Figure 35D , illustrates an alternative embodiment of a fifth configuration of a second exemplary structure, which can be obtained by increasing the over-etch depth of the memory opening 49 at the processing steps of Figure 20A and Figure 20B and / or by increasing the etch depth during the etching step at the processing steps of Figure 30A and Figure 30B from the fifth configuration of the second exemplary structure illustrated in Figure 35C . In this case, the planar horizontal bottom portion of each vertical semiconductor channel 60 can be removed at the processing steps of Figure 30A and Figure 30B . Each physically exposed surface of the vertical semiconductor channels 60 can be an annular surface having an inner perimeter and an outer perimeter. In one embodiment, each memory opening fill structure 58 includes a dielectric core 62 that is laterally surrounded by the vertical semiconductor channels 60 and has a bottom surface that contacts a circular segment of the top surface of the backside semiconductor capping layer structure 111.

[0198] Reference Figure 36 , illustrates a second exemplary structure after formation of the source contact structure according to a second embodiment of the present disclosure. Figure 36 Illustrates the first through fourth configurations of the second exemplary structure in which a two-dimensional array of discrete backside semiconductor capping layer structures 111 is employed.

[0199] Reference Figure 37 , illustrates an alternative embodiment of the second exemplary structure after formation of the source contact structure. Figure 37The fifth configuration that illustrates the second exemplary structure in which the back semiconductor cap layer structure 111 is formed as a single continuous semiconductor material layer.

[0200] Reference Figures 1 to 4 and Figures 20A to 37 And according to a second embodiment of the present disclosure, a semiconductor structure includes: an alternating stack (32, 46) of an insulating layer 32 and a conductive layer 46; a memory opening 49 that vertically extends through the alternating stack (32, 46); a memory opening fill structure 58 that is located in the memory opening 49 and includes a memory film 50 and a vertical semiconductor channel 60; and a back semiconductor cap layer structure 111 that has a top surface 111T in contact with a bottom surface of the vertical semiconductor channel 60, wherein an entirety of the top surface 111T of the back semiconductor cap layer structure 111 is located in a horizontal plane that includes a bottom surface of the lowermost insulating layer within the alternating stack (32, 46).

[0201] In one embodiment, an annular bottom surface of the memory film 50 contacts an annular surface segment of the top surface of the back semiconductor cap layer structure 111. In one embodiment, the top surface 111T of the back semiconductor cap layer structure 111 contacts a bottom surface of the lowermost insulating layer within the alternating stack (32, 46) and contacts a planar horizontal surface of the vertical semiconductor channel 60.

[0202] In one embodiment, the back semiconductor cap layer structure 111 includes a contoured bottom surface 111B; and each point on the contoured bottom surface 111B is equidistant from a corresponding nearest-side point on the bottom surface of the vertical semiconductor channel 60. In one embodiment, the contoured bottom surface 111B includes a horizontal planar bottom surface segment and a convexly tapered annular surface segment that connects a perimeter of the horizontal planar bottom surface segment to a perimeter of the top surface of the back semiconductor cap layer structure 111.

[0203] In one embodiment, the semiconductor structure further includes a metal-semiconductor alloy structure (116, 126, 136, 146) that contacts a bottom surface of the backside semiconductor capping layer structure 111. In one embodiment, the metal-semiconductor alloy structure (116, 126, 136, 146) includes an annular top surface that contacts an annular surface segment of a bottom surface of a bottommost insulating layer of the alternating stack (32, 46) in a horizontal plane. In one embodiment, the metal-semiconductor alloy structure 136 includes a planar metal-semiconductor alloy layer that is vertically spaced apart from the bottommost insulating layer by the backside semiconductor capping layer structure 111. In one embodiment, the semiconductor structure further includes a backside conductive layer (234, 244) that includes and / or consists essentially of at least one metal material and contacts a bottom surface of the metal-semiconductor alloy structure (116, 126, 136, 146).

[0204] In one embodiment, the vertical semiconductor channel 60 is doped with a first conductivity type; and the backside semiconductor capping layer structure 111 is doped with a first conductivity type. Alternatively, the vertical semiconductor channel 60 is doped with a first conductivity type; and the backside semiconductor capping layer structure 111 is doped with a second conductivity type opposite to the first conductivity type. In one embodiment, an entirety of an interface between the memory opening fill structure 58 and the backside semiconductor capping layer structure 111 lies in a horizontal plane.

[0205] Various embodiments of the present disclosure can be used to provide various backside semiconductor capping layer structures 111 that can be advantageously used to provide reliable electrical contact between the vertical semiconductor channel 60 and the backside conductive layer (234, 244). Both the semiconductor capping layer structure 111 and the metal-semiconductor alloy structure (116, 126, 136, 146) can be formed at relatively low temperatures (e.g., below 400 degrees Celsius) to avoid negatively affecting the quality of the bond pads and the bond between the logic die 700 and the memory die 900. The metal-semiconductor alloy structure (116, 126, 136, 146) provides a low contact resistance between the source contact structure and the vertical semiconductor channel 60. Additionally, the contact area with the vertical semiconductor channel is increased by forming the semiconductor capping layer structure 111 under the alternating stack (32, 46), which further reduces the contact resistance.

[0206] Notwithstanding the foregoing being directed to particularly preferred embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art will appreciate that various modifications may be made to the disclosed embodiments, and such modifications are intended to be within the scope of the present disclosure. Compatibility is assumed among all embodiments that are not alternatives to one another. Unless expressly stated otherwise, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or "consisting of" replace the words "comprising" or "including". Whenever two or more elements are listed as alternatives in the same paragraph or in different paragraphs, a Markush group encompassing the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb "may" is used in the present disclosure to describe the formation of an element or the performance of a processing step, embodiments in which such element or such processing step is not performed are also expressly contemplated, provided that the resulting device or apparatus can provide an equivalent result. Thus, whenever the omission of the formation of such element or such processing step can provide the same result or an equivalent result (such equivalent results including slightly better results and slightly worse results), the auxiliary verb "may" applied to the performance of the formation of an element or a processing step should also be construed as "may" or "may or may not". In cases where embodiments employing a particular structure and / or configuration are illustrated in the present disclosure, it should be understood that the present disclosure may be practiced using any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise considered impossible by those of ordinary skill in the art. If publications, patent applications, and / or patents are cited herein, the entire text of each such document is incorporated herein by reference.

Claims

1. A semiconductor structure, the semiconductor structure comprising: An alternating stack of an insulating layer and a conductive layer; A memory opening that vertically extends through the alternating stack; A memory opening filling structure that is located in the memory opening and includes a memory film and a vertical semiconductor channel, the vertical semiconductor channel laterally surrounding a core cavity that contains no solid-phase material therein; A Group-IV material portion that contacts an end portion of the vertical semiconductor channel and is exposed in the core cavity; And A source contact structure that contacts a bottom surface of the Group-IV material portion and a bottom surface of the lowermost layer in the alternating stack.

2. The semiconductor structure according to claim 1, wherein the memory opening filling structure further includes a dielectric core, the dielectric core laterally surrounding the core cavity and being laterally surrounded by the vertical semiconductor channel.

3. The semiconductor structure according to claim 2, wherein: The Group-IV material portion contacts an end segment of an inner sidewall of the dielectric core that is exposed in the core cavity; and A lateral thickness of the dielectric core measured between the inner sidewall and an outer sidewall of the dielectric core increases with a vertical distance from the source contact structure around an end portion of the core cavity.

4. The semiconductor structure according to claim 1, the semiconductor structure further including a logic die that is bonded to a memory die that includes the alternating stack.

5. The semiconductor structure according to claim 1, wherein a top surface of the Group-IV material portion includes a tapered convex surface that has a lowest point at a central region thereof.

6. The semiconductor structure according to claim 1, wherein the vertical semiconductor channel has a tubular configuration, and the Group-IV material portion is located within an end portion of a cylindrical cavity within the vertical semiconductor channel.

7. The semiconductor structure according to claim 1, wherein the Group-IV material portion includes at least one of silicon or germanium.

8. The semiconductor structure according to claim 7, wherein the Group-IV material portion includes a semiconductor portion that consists essentially of silicon, germanium, or silicon-germanium.

9. The semiconductor structure according to claim 7, wherein the Group-IV material portion includes a doped semiconductor portion that consists essentially of silicon, germanium, or silicon-germanium doped with at least one p-type dopant or n-type dopant.

10. The semiconductor structure according to claim 9, wherein: The vertical semiconductor channel has a doping of a first conductivity type; and The doped semiconductor portion has a doping of the first conductivity type.

11. The semiconductor structure according to claim 9, wherein: The vertical semiconductor channel has a doping of a first conductivity type; and The doped semiconductor portion has a doping of a second conductivity type opposite to the first conductivity type.

12. The semiconductor structure according to claim 7, wherein the Group-IV material portion includes a metal-semiconductor alloy portion.

13. The semiconductor structure according to claim 12, wherein the metal-semiconductor alloy portion comprises a metal silicide, a metal germanide, or a metal silicide-germanide.

14. The semiconductor structure according to claim 1, wherein an annular end surface of the vertical semiconductor channel contacts the source contact structure.

15. A method of forming a semiconductor structure, the method comprising: forming an alternating stack of an insulating layer and a spacer material layer over a carrier substrate, wherein the spacer material layer is formed as a conductive layer or is subsequently replaced by a conductive layer; forming a memory opening through the alternating stack; forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure comprises a memory film and a vertical semiconductor channel; removing the carrier substrate; removing end portions of the memory opening fill structure to expose end portions of the vertical semiconductor channel; selectively growing a Group-IV material portion from a physically exposed surface of the vertical semiconductor channel; and forming a source contact structure over the Group-IV material portion.

16. The method according to claim 15, wherein removing the end portions of the memory opening fill structure comprises etching end portions of a dielectric core surrounded by the vertical semiconductor channel such that a cylindrical surface segment of an inner sidewall of the vertical semiconductor channel is physically exposed.

17. The method according to claim 16, wherein: the dielectric core surrounds a core cavity that does not contain any solid-phase material; and the Group-IV material portion seals an opening at a bottom end of the vertical semiconductor channel such that a remaining portion of the core cavity is wrapped by the dielectric core and the Group-IV material portion.

18. The method according to claim 15, wherein the Group-IV material portion comprises a semiconductor portion consisting essentially of silicon, germanium, or silicon-germanium.

19. The method according to claim 15, wherein the Group-IV material portion comprises a doped semiconductor portion consisting essentially of silicon, germanium, or silicon-germanium doped with at least one p-type dopant or n-type dopant.

20. The method according to claim 15, wherein the Group-IV material portion comprises a metal-semiconductor alloy portion.

21. A semiconductor structure, the semiconductor structure comprising: an alternating stack of an insulating layer and a conductive layer; a memory opening that extends vertically through the alternating stack; a memory opening fill structure that is located in the memory opening and comprises a memory film and a vertical semiconductor channel; and a backside semiconductor capping layer structure having a top surface that contacts a bottom surface of the vertical semiconductor channel, wherein the entire top surface of the backside semiconductor capping layer structure lies in a horizontal plane that includes a bottom surface of the bottommost insulating layer within the alternating stack.

22. The semiconductor structure according to claim 21, wherein an annular bottom surface of the memory film contacts an annular surface segment of the top surface of the backside semiconductor capping layer structure.

23. The semiconductor structure according to claim 21, wherein a top surface of the back semiconductor cap layer structure contacts a bottom surface of the bottommost insulating layer within the alternating stack.

24. The semiconductor structure according to claim 21, wherein the top surface of the back semiconductor cap layer structure contacts a planar horizontal surface of the vertical semiconductor channel.

25. The semiconductor structure according to claim 21, further comprising a logic die, the logic die being bonded to a memory die including the alternating stack.

26. The semiconductor structure according to claim 21, wherein: the back semiconductor cap layer structure includes a contoured bottom surface; and each point on the contoured bottom surface is equidistant from a corresponding nearest-side point on a bottom surface of the vertical semiconductor channel.

27. The semiconductor structure according to claim 26, wherein the contoured bottom surface includes a horizontal planar bottom surface segment and a convexly tapered annular surface segment, the convexly tapered annular surface segment connecting a perimeter of the horizontal planar bottom surface segment to a perimeter of the top surface of the back semiconductor cap layer structure.

28. The semiconductor structure according to claim 21, further comprising a metal-semiconductor alloy structure, the metal-semiconductor alloy structure contacting a bottom surface of the back semiconductor cap layer structure.

29. The semiconductor structure according to claim 28, wherein the metal-semiconductor alloy structure includes an annular top surface, the annular top surface contacting an annular surface segment of the bottom surface of the bottommost insulating layer of the alternating stack within the horizontal plane.

30. The semiconductor structure according to claim 28, wherein the metal-semiconductor alloy structure includes a planar metal-semiconductor alloy layer, the planar metal-semiconductor alloy layer being vertically spaced apart from the bottommost insulating layer by the back semiconductor cap layer structure.

31. The semiconductor structure according to claim 28, further comprising a back conductive layer, the back conductive layer including at least one metal material and contacting a bottom surface of the metal-semiconductor alloy structure.

32. The semiconductor structure according to claim 21, wherein: the vertical semiconductor channel is doped with a first conduction type; and the back semiconductor cap layer structure is doped with the first conduction type.

33. The semiconductor structure according to claim 21, wherein: the vertical semiconductor channel is doped with a first conduction type; and the back semiconductor cap layer structure is doped with a second conduction type opposite to the first conduction type.

34. The semiconductor structure according to claim 21, wherein an entirety of an interface between the memory opening filling structure and the back semiconductor cap layer structure lies within the horizontal plane.

35. A method of forming a semiconductor structure, the method comprising: forming an alternating stack of insulating layers and spacer material layers over a carrier substrate, wherein the spacer material layer is formed as a conductive layer or is subsequently replaced by a conductive layer; forming memory openings vertically through the alternating stack; A memory opening filling structure is formed in the memory opening, wherein the memory opening filling structure includes a memory film and a vertical semiconductor channel; The carrier substrate is removed; The bottom surface of the vertical semiconductor channel is exposed in a horizontal plane, the horizontal plane including the bottom surface of the bottommost insulating layer within the alternating stack; and A backside semiconductor cap layer structure is formed by directly depositing a semiconductor material on the bottom surface of the vertical semiconductor channel.

36. The method according to claim 35, wherein the backside semiconductor cap layer structure is formed by performing a selective semiconductor deposition process that grows the semiconductor material from the bottom surface of the vertical semiconductor channel while suppressing growth of the semiconductor material from the bottom surface of the bottommost insulating layer within the alternating stack.

37. The method according to claim 36, wherein the bottom surface of the vertical semiconductor channel is free of any openings therein.

38. The method according to claim 35, wherein the backside semiconductor cap layer structure is formed as a layer of semiconductor material that covers all physically exposed portions of the bottom surface of the bottommost insulating layer within the alternating stack.

39. The method according to claim 35, the method further comprising forming a metal-semiconductor alloy structure that contacts the bottom surface of the backside semiconductor cap layer structure.

40. The method according to claim 39, the method further comprising forming a backside conductive layer comprising at least one metal material on the bottom surface of the metal-semiconductor alloy structure.

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