Semiconductor integrated circuit and module thereof

Abstract

The pin electronics (IC400) are formed on the semiconductor chip (500). The pin electron (IC400) is provided with two dummy regions (502, 504) which are located on both sides of the semiconductor chip (500) in the first direction and in which no transistor serving as a heat source is disposed. A main circuit (508) of the pin electronics (IC400) is formed in a region (506) sandwiched between two dummy regions (502, 504).

Description

Technical Field

[0001] The present disclosure relates to semiconductor integrated circuits. Background Art

[0002] An automatic test equipment (ATE) is used in the inspection of various semiconductor devices such as memories and CPUs (Central Processing Units). The ATE supplies a test signal to a semiconductor device to be tested (hereinafter referred to as a device under test (DUT)), measures the response of the DUT to the test signal, determines whether the DUT is good or bad, or identifies a defective part.

[0003] Figure 1 is a block diagram of a conventional ATE10. The ATE10 includes a tester (also referred to as a tester main body) 20, a test head 30, an interface device 40, and a processor 50.

[0004] The tester 20 centrally controls the ATE10. Specifically, the tester 20 executes a test program, controls the test head 30 and the processor 50, and collects measurement results.

[0005] The test head 30 includes hardware that generates a test signal to be supplied to the DUT1 and detects a signal from the DUT (referred to as a device signal). Specifically, the test head 30 includes a pin electronics (PE) 32, a power supply circuit (not shown), etc. The PE32 is an ASIC (Application Specific IC) including a driver and a comparator, etc. Conventionally, the PE32 is mounted on a printed circuit board called a PE board 34 and housed inside the test head 30.

[0006] The interface device 40 is also referred to as a high-fidelity test interface board (HiFix) and relays the electrical connection between the test head 30 and the DUT1. The interface device 40 includes a socket board 42. A plurality of sockets 44 are provided on the socket board 42, and multiple DUT1s can be measured simultaneously. In the case of an ATE for wafer-level testing, a probe card is used instead of the socket board 42.

[0007] The processor 50 loads a plurality of DUT1s into a plurality of sockets 44 and presses the DUT1s against the sockets 44. After the test is completed, the processor 50 unloads the DUT1s and, if necessary, differentiates between qualified and unqualified products.

[0008] The interface device 40 includes a socket board 42 and a plurality of cables 46 connecting the test head 30. The test signal generated by the PE32 is transmitted to the DUT1 via the cables 46, and the device signal generated by the DUT1 is transmitted to the PE32 via the cables 46.

[0009] Prior Art Documents

[0010] Patent document

[0011] Patent document 1: Japanese Patent Application Laid-Open No. 2008-76308

[0012] Patent document 2: International Publication WO2009-034641 Summary of the invention

[0013] Outline of the invention

[0014] Problems to be solved by the invention

[0015] In recent years, the high-speed performance of DRAM (Dynamic Random Access Memory) has been continuously improved. In the GDDR (Graphics Double Data Rate) memory mounted on a graphics board, under the GDDR6X standard, a transmission speed of 21 Gbps is achieved by the NRZ (Non-Return to Zero) method.

[0016] In the next-generation GDDR7, PAM4 (Pulse Amplitude Modulation 4) is adopted, and the transmission speed is increased to 40 Gbps. The NRZ method has also been continuously improved in terms of high speed over the years, and in the next generation, it will be increased to about 28 Gbps.

[0017] With the high-speed performance of the DUT, the heat generation of the PE32 increases, and further consideration for cooling is required.

[0018] The present disclosure is made in view of the above circumstances, and one of its exemplary purposes is to provide a semiconductor integrated circuit capable of testing high-speed devices exceeding 20 Gbps.

[0019] Solutions to solve the problems

[0020] A semiconductor integrated circuit according to one aspect of the present disclosure includes: a semiconductor chip; two dummy areas located on both sides of the semiconductor chip in a first direction and not provided with transistors serving as heat sources; and a main circuit of the semiconductor integrated circuit formed in a region sandwiched by the two dummy areas.

[0021] It should be noted that the forms in which the above components are arbitrarily combined and the forms in which the components and expressions are mutually replaced between methods, devices, systems, etc. are also effective as the forms of the present invention or the present disclosure. In addition, the description of this matter (solutions to solve the problems) is not all the essential features for explaining the present invention, and therefore, sub-combinations of these described features can also be regarded as the present invention.

[0022] Advantages of the invention

[0023] According to one aspect of the present disclosure, heat generation of a semiconductor integrated circuit can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a block diagram of a conventional ATE.

[0025] Figure 2 is a diagram of an ATE showing an embodiment.

[0026] Figure 3 is a cross-sectional view of an interface device of an embodiment.

[0027] Figure 4 is a diagram showing a front-end module of an embodiment.

[0028] Figure 5 is showing Figure 4 a perspective view of a configuration example of the FEU of.

[0029] Figure 6 is showing Figure 4 a cross-sectional view of a configuration example of the FEU of.

[0030] Figure 7 is a cross-sectional view showing an example of the connection between a pin electronic IC and a socket.

[0031] Figure 8 is a cross-sectional view showing a configuration example of a connection portion between an FPC cable and a socket board.

[0032] Figure 9 is an exploded perspective view of a connection portion between an FPC cable and a socket board.

[0033] Figure 10 (a) and (b) of are cross-sectional views illustrating the structure and connection of an interposer.

[0034] Figure 11 is a cross-sectional view showing a configuration example of a connection portion between an FPC cable and a printed circuit board.

[0035] Figure 12 is an exploded perspective view of a connection portion between an FPC cable and a printed circuit board.

[0036] Figure 13 is a diagram showing the layout of a pin electronic PCB.

[0037] Figure 14 is a simplified layout diagram of a pin electronic PCB.

[0038] Figure 15 is a top view showing the layout of a pin electronic IC.

[0039] Figure 16 Is a perspective view of a structure representing a dummy region.

[0040] Figure 17 Is an exploded perspective view of a condensation plate.

[0041] Figure 18 Is a perspective view illustrating the cooling of a semiconductor chip based on a condensation plate.

[0042] Figure 19 Is a cross-sectional view showing the package structure of a lead electronic IC. Detailed implementation mode

[0043] (Summary of the implementation mode)

[0044] Describes the summary of several exemplary implementation modes of the present disclosure. This summary is a prelude to the detailed description below and is for the purpose of a basic understanding of the implementation modes. It simply explains several concepts of one or more implementation modes without limiting the scope of the invention or disclosure. This summary is not an inclusive summary of all the implementation modes, nor does it define the scope of a part or all of the forms by identifying important elements of all the implementation modes. For simplicity, "one implementation mode" is sometimes used to indicate one implementation mode (example, variant) or multiple implementation modes (example, variant) disclosed in this specification.

[0045] A semiconductor integrated circuit according to one implementation mode includes: a semiconductor chip; two dummy regions located on both sides in the first direction of the semiconductor chip and not configured with transistors that become heat sources; and a main circuit of the semiconductor integrated circuit formed in the region sandwiched by the two dummy regions.

[0046] According to this structure, the main circuit that becomes the heat source is sandwiched by the dummy regions, so that the heat generated in the main circuit can escape in the horizontal direction and then be released to the outside through the dummy regions.

[0047] In one implementation mode, the semiconductor chip can be a rectangle with the first direction as the long side.

[0048] In one implementation mode, a power mesh can be formed in the two dummy regions. By configuring the power mesh in the dummy regions, the stability of the power supply voltage can be improved.

[0049] In one implementation mode, a MOS capacitor can be connected to the power mesh. Thereby, the stability of the power supply voltage can be further improved.

[0050] In one implementation mode, the length of each of the two dummy regions in the first direction can be 3 mm or more.

[0051] In one embodiment, the length of each dummy region in the first direction may be longer than 1 / 5 of the length of the main circuit in the first direction.

[0052] A module according to one embodiment includes: any one of the above semiconductor integrated circuits; and a cold plate having a cooling flow path inside and thermally coupled to the semiconductor integrated circuit. The cooling flow path of the cold plate may be parallel to the first direction.

[0053] In one embodiment, the cooling flow path of the cold plate may include a U-shaped portion that faces the first direction and returns in the opposite direction.

[0054] In one embodiment, the semiconductor chip of the semiconductor integrated circuit is not sealed, and the semiconductor chip may be in contact with the cold plate via a heat-conductive material.

[0055] In one embodiment, the semiconductor integrated circuit may be an FC-PGA package and is mounted on a printed circuit board via an interposer.

[0056] (Embodiment)

[0057] Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in the respective drawings are denoted by the same reference numerals, and repeated descriptions are appropriately omitted. Moreover, the embodiments are illustrative rather than limiting the disclosure and the invention, and all the features and combinations thereof described in the embodiments are not necessarily the essential features and combinations of the disclosure and the invention.

[0058] In addition, the dimensions (thickness, length, width, etc.) of each member shown in the drawings are sometimes appropriately enlarged or reduced for easy understanding. In addition, the dimensions of multiple members do not necessarily represent their size relationships. In the drawings, even if a certain member A is depicted as thicker than another member B, it is possible that member A is thinner than member B.

[0059] In this specification, the state where "member A is connected to member B" includes not only the case where member A is physically directly connected to member B, but also the case where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection state or do not impair the functions and effects achieved by their combination.

[0060] Similarly, the state where "member C is connected to (is provided between) member A and member B" includes not only the case where member A and member C, or member B and member C are directly connected, but also the case where they are indirectly connected via other members that do not substantially affect their electrical connection state or do not impair the functions and effects achieved by their combination.

[0061] Figure 2This is a diagram showing the ATE100 of an embodiment. The ATE100 includes a tester 120, a test head 130, a processor 150, and an interface device 200.

[0062] The tester 120 centrally controls the ATE100. Specifically, the tester 120 executes a test program, controls the test head 130 and the processor 150, and collects measurement results.

[0063] The processor 150 supplies (loads) the DUT1 to the interface device 200 and unloads the tested DUT1 from the interface device 200. Moreover, the processor 150 classifies the DUT1 into qualified products and unqualified products.

[0064] The interface device 200 includes a socket board 210, a wiring 220, and a front-end module 300.

[0065] In this embodiment, a plurality of pin electronic ICs (PE-ICs) 400 are provided in the interface device 200 instead of in the test head 130. The pin electronic IC 400 is an application-specific integrated circuit (ASIC: Application Specific IC) that integrates a driver for generating a test signal and a comparator for receiving a device signal. The test signal and the device signal are NRZ signals or PAM4 signals.

[0066] More specifically, a plurality of pin electronic ICs 400 are modularized. This module is called the front-end module 300.

[0067] A plurality of sockets 212 are provided on the socket board 210. The DUT1 is assembled in the socket 212. The front-end module 300 is connected to the socket 212 via the wiring 220.

[0068] The above is the structure of the ATE100.

[0069] According to this ATE100, by incorporating the front-end module 300 formed by modularizing a plurality of pin electronic ICs 400 into the interface device 200, the pin electronic IC 400 can be arranged near the DUT1. As a result, the transmission distance of the test signal and the device signal can be significantly shortened compared to the prior art.

[0070] For example, in a conventional ATE, the pin electronic IC and the socket board are connected by a coaxial cable with a length of about 500 mm to 600 mm, but in this embodiment, the length of the wiring 220 can be shortened to about 100 mm to 150 mm. As a result, the loss of high-frequency components can be significantly reduced, and high-speed test signals and device signals can be transmitted. The ATE100 equipped with this interface device 200 can perform tests on high-speed memories exceeding 20 Gbps.

[0071] The present disclosure relates to various apparatuses and methods that are grasped as block diagrams, circuit diagrams, etc. of Figure 2 or derived from the above description, and are not limited to a specific structure. Hereinafter, in order to facilitate the understanding of the essence and operation of the present disclosure and the present invention, and to clarify them, more specific configuration examples and embodiments will be described without narrowing the scope of the present disclosure.

[0072] Figure 3 It is a cross-sectional view of an interface device 200A according to an embodiment. Figure 3 Only the structure associated with one DUT is shown. In this embodiment, the interface device 200A includes a main board 230 and a socket board 210 that can be detachably attached to the main board 230. The socket board 210 includes a socket 212, a socket printed circuit board (socket PCB) 214, and a socket board side connector 216.

[0073] The front-end module 300A includes a plurality of printed circuit boards (pin electronic PCBs) 310 on which a plurality of pin electronic ICs 400 are mounted. The plurality of pin electronic PCBs 310 are arranged in a direction perpendicular to the surface (front and back surfaces) of the DUT, in other words, the surface S1 of the socket board 210. In the present embodiment, since the socket board 210 is parallel to the ground, the plurality of pin electronic PCBs 310 are arranged parallel to the direction of gravity.

[0074] The front-end module 300A further includes a plate-shaped cooling device (hereinafter referred to as a condensation plate) 320. The condensation plate 320 has a flow path through which a refrigerant flows.

[0075] The plurality of pin electronic PCBs 310a, 310b and the condensation plate 320 are stacked in such a manner that the pin electronic ICs 400 are thermally coupled to the condensation plate 320.

[0076] The main board 230 includes a socket board side connector 232, a spacer frame 234, and a relay connector 236. The front-end module 300A is fixed to the spacer frame 234. The relay connector 236 is electrically and mechanically coupled to the test head side connector 132.

[0077] As will be described in detail later, the wiring 220 can use a cable (also referred to as an FPC cable) made of a flexible printed circuit (FPC) instead of a conventional coaxial cable.

[0078] On the other hand, the wiring 224 between the pin electronic PCB 310 and the relay connector 236 only transmits control signals for the pin electronic ICs 400, and does not transmit test signals or device signals. Therefore, the wiring 224 can use a coaxial cable.

[0079] ​​The multiple-pin electronic IC 400 is mounted on the pin electronic PCB 310 at a position closer to the DUT (closer to the socket board 210) than the center in the up-down direction of the pin electronic PCB 310. Thereby, the transmission distance of the test signal and the device signal on the pin electronic PCB 310 can be shortened, and high-speed signal transmission can be performed.

[0080] For example, the multiple-pin electronic ICs 400 are preferably arranged at positions within 50 mm from one side of the DUT side of the pin electronic PCB 310. If they can be arranged within 30 mm, the transmission distance can be further shortened.

[0081] Figure 4 It is a diagram showing the front-end module 300B of an embodiment.

[0082] 2×M (M≥1) multiple-pin electronic ICs 400 are allocated to one DUT1. Footnotes A to D are given to multiple DUTs and multiple-pin electronic ICs 400 for distinction as needed. In this example, when the DUT1 has 192 I / Os and the multiple-pin electronic IC 400 has 24 I / Os, each DUT is allocated 192 / 24 = 8 (i.e., M = 4) multiple-pin electronic ICs 400.

[0083] The front-end module 300B is configured to be divided into multiple parts according to N (N≥2) DUT1s, and the division unit is called a front-end unit (FEU). In this example, the block corresponding to four DUTs constitutes one FEU, and one FEU has 2×M×N = 2×4×4 = 32 multiple-pin electronic ICs 400.

[0084] Figure 4 Although two FEUs are shown, actually the front-end module 300B can have two or more FEUs. For example, in an ATE capable of simultaneous measurement of 64 channels, 64 / 4 = 16 FEUs are provided, and as the entire front-end module 300B, it has 64×192 I / Os = 12288 I / Os.

[0085] Figure 5 It is showing Figure 4 A three-dimensional diagram of the configuration example of the FEU. The sockets 212A to 212D corresponding to four DUTs are arranged in a two-row and two-column matrix. If we focus on one DUT1A, the eight multiple-pin electronic ICs 400A allocated to it are separately mounted two by two on four pin electronic PCBs 310a to 310d arranged along the X direction. The socket PCB 214 of the mounting socket 212 can be divided according to each DUT, and the socket PCBs 214 corresponding to four DUTs can be integrally formed as one substrate.

[0086] Two pin electronics ICs 400A mounted on a pin electronics PCB 310 are arranged in the Y direction. The two pin electronics ICs 400A are arranged at positions equidistant from the DUT 1A.

[0087] Figure 6 is a cross-sectional view showing Figure 4 a configuration example of the FEU. As Figure 3 shown, a condensation plate 320 is provided between two pin electronics PCBs 310a and 310b. Similarly, a condensation plate 320 is also provided between two pin electronics PCBs 310c and 310d. As described above, the pin electronics IC 400 is mounted on the pin electronics PCB 310 at a position close to the socket board 210. In order to improve the cooling efficiency, the pin electronics IC 400 can be a bare chip, and the pin electronics IC 400 and the condensation plate 320 are thermally coupled via a thermal interface material (TIM) 322.

[0088] In addition, when observing the FEU from above along the Y axis, the center of the DUT, that is, the socket 212A is located at the center position of four (M sheets) pin electronics PCBs 310a to 310d stacked in the X direction.

[0089] The above is the structure of the FEU.

[0090] Explain the advantages of this FEU. Focus on the DUT 1A with footnote A. A plurality of (eight in this example) pin electronics ICs 400A corresponding to one DUT 1A are mounted two by two on four pin electronics PCBs 310a to 310d, thereby enabling the distances from the eight pin electronics ICs 400A to the socket 212A to be uniform. Thereby, the losses of the transmission lines from each pin electronics IC 400A to the socket 212A (DUT 1A) can be made uniform, and accurate tests can be performed.

[0091] Next, explain the electrical connection between the pin electronics IC 400 and the socket 212.

[0092] Figure 7 is a cross-sectional view showing an example of the connection between the pin electronics IC and the socket (DUT 1). The wiring 220 between the pin electronics PCB 310 and the socket board 210, that is, the transmission path for test signals and device signals, uses an FPC cable 222.

[0093] When using a coaxial cable as the wiring 220 between the pin electronic PCB 310 and the socket board 210, the shortest distance between the pin electronic PCB 310 and the socket board 210 is restricted due to the rigidity of the coaxial cable. Moreover, in contrast, by using the FPC cable 222, compared with the case of using a coaxial cable, the distance h between the pin electronic PCB 310 and the socket board 210 can be shortened due to its flexibility, and the transmission distance of the test signal and the device signal can be shortened.

[0094] In a conventional test device, when it is desired to be able to disassemble and assemble the socket board 210, an LIF (Low Insertion Force) connector is usually used. This LIF connector has a non-negligible loss of about -3 dB in a frequency band higher than 14 GHz, and becomes a cause of waveform distortion in high-speed transmission of 28 Gbps or 40 Gbps. By using the FPC cable 222 for the wiring 220, the LIF connector is not required, so that waveform distortion caused by loss (attenuation in the high-frequency band) can be suppressed, and accurate tests can be performed.

[0095] Figure 8 It is a cross-sectional view showing a configuration example of a connection portion between the FPC cable 222 and the socket board 210. Figure 9 It is an exploded perspective view of a connection portion between the FPC cable 222 and the socket board 210.

[0096] The socket board 210 includes sockets 212 and a socket PCB 214. The socket PCB 214 is a multilayer substrate including a wiring layer and an insulating layer. Wirings for moving the signal path in the horizontal direction are formed in the wiring layer, and via holes VH for moving the signal path in the vertical direction are formed in the insulating layer. The paths for transmitting the test signal and the device signal are preferably led out to the back surface of the socket board 210 without moving in the horizontal direction as much as possible.

[0097] The FPC cable 222 and the socket board 210 are connected by a socket board side connector 216. The socket board side connector 216 includes an intermediate layer 218 and a cable clip 219.

[0098] The electrodes exposed on the surface of the intermediate layer 218 are electrically connected to the electrodes exposed on the back surface of the socket PCB 214. The FPC cable 222 is clamped by the cable clip 219 in a state of being in contact with the back surface electrodes of the intermediate layer 218.

[0099] Figure 10 (a) and (b) are cross-sectional views for explaining the structure and connection of the intermediate layer. Figure 10 (a) shows the state before connection, Figure 10Part (b) of [Figure 0] shows the connected state. The intermediate layer 218 has a substrate 250, a non-deformable electrode 252, and a deformable electrode 254. An opening 256 is provided on the first surface S1 of the substrate 250, and the deformable electrode 254 is embedded therein. The deformable electrode 254 has conductivity and elasticity, and protrudes from one surface of the substrate 250 in the state before connection. The deformable electrode 254 can be a conductive gasket or a conductive elastomer. Alternatively, the deformable electrode 254 can be an electrode with a spring like a spring pin.

[0100] The non-deformable electrode 252 is provided on the second surface S2 of the substrate 250. The non-deformable electrode 252 is electrically connected to the deformable electrode 254 inside the substrate 250. The non-deformable electrode 252 has a plurality of protrusions and can perform multi-point connection.

[0101] As Figure 10 shown in part (b) of [Figure 0], if pressure is applied to the socket PCB 214 and the FPC cable 222 with the intermediate layer 218 sandwiched therebetween, the non-deformable electrode 252 of the intermediate layer 218 contacts the electrode 222e of the FPC cable 222. Moreover, the deformable electrode 254 deforms and contacts the back electrode 214e of the socket PCB 214.

[0102] Such an intermediate layer 218 can form a smaller parasitic capacitance compared to a LIF connector or a ZIF connector, and thus is excellent in high-frequency characteristics. From 0 to 40 GHz, a flat pass characteristic (S21 characteristic of S-parameters) can be obtained.

[0103] Figure 11 It is a cross-sectional view showing a configuration example of the connection portion between the FPC cable 222 and the pin electronic PCB 310. Figure 12 It is an exploded perspective view of the connection portion between the FPC cable 222 and the pin electronic PCB 310.

[0104] Refer to Figure 11 . The FPC cable 222 and the pin electronic PCB 310 are connected by an FPC connector 312. The FPC connector 312 is configured in the same way as the socket board side connector 216. Specifically, it includes an intermediate layer 314 and a cable clip 316.

[0105] The deformable electrode 254 exposed on the first surface S1 of the intermediate layer 314 is electrically connected to the electrode on the back of the pin electronic PCB 310. The FPC cable 222 is clamped by the cable clip 316 in a state of being in electrical contact with the non-deformable electrode 252 exposed on the second surface S2 of the intermediate layer 314.

[0106] A via VH is formed in the pin electronic PCB 310. Inside the pin electronic PCB 310, it is also desired to minimize the transmission paths of test signals and device signals. Therefore, the via VH formed in the pin electronic PCB 310 is preferably arranged at a position overlapping the back electrode 402 of the pin electronic IC 400. Thus, inside the pin electronic PCB 310, the transmission path is not led back in the in-plane direction of the printed circuit board, so high-speed signal transmission can be performed.

[0107] Figure 13 FIG. is a diagram showing the layout of the pin electronic PCB 310. A plurality of pin electronic ICs 400, RAM 410, pin controllers 420, non-volatile memories 430, and linear regulators 440 are mounted on the pin electronic PCB 310.

[0108] The test head 130 includes a bus controller 134, a DC / DC converter 136, and an oscillator 138.

[0109] The pin controller 420 is connected to the bus controller 134 via an external bus BUS1. The pin controller 420 comprehensively controls the pin electronic PCB 310 (i.e., the front-end module 300) according to the control signal from the bus controller 134. The pin controller 420 can be composed of an FPGA (Field Programmable Gate Array) or a CPU.

[0110] The pin controller 420 is connected to the pin electronic IC 400 via a local bus BUS2, and can transmit and receive control signals, data, various error signals, etc. The pin controller 420 controls the pin electronic IC 400 to cause the pin electronic IC 400 to generate test signals for the DUT1. The pin electronic IC 400 includes a driver Dr, a comparator Cp, an A / D converter ADC, etc. according to each I / O pin. Moreover, diodes for ESD protection are connected to each I / O pin.

[0111] The pin electronic IC 400 receives device signals from a DUT1 (not shown). The pin electronic IC 400 stores data based on the received device signals in the RAM 410. The RAM 410 is, for example, a DRAM (Dynamic Random Access Memory).

[0112] Configuration data of the pin controller 420, data defining the operating conditions of the pin controller 420 and the entire front-end module 300, etc. are stored in the non-volatile memory 430.

[0113] The pin controller 420 reads data from the RAM 410 and sends it to the bus controller 134.

[0114] The linear regulator 440 is a power supply circuit called an LDO (Low Drop Output). A DC voltage V is supplied to the input node of the linear regulator 440 from the DC / DC converter 136 provided on the test head 130 side. DC to generate a power supply voltage V LDO . The power supply voltage V LDO is supplied to the pin electronic IC 400 and used as the power supply for the driver Dr, comparator Cp, etc.

[0115] The D / A converter 450 receives voltage setting data D from the pin controller 420 REF and converts it into an analog reference voltage V REF . The power supply voltage V generated by the linear regulator 440 LDO is a voltage that is a constant multiple of the reference voltage V REF .

[0116] The digital circuits on the pin electronic PCB 310 side, specifically, a part of the pin controller 420, the pin electronic IC 400, the non-volatile memory 430, and the RAM 410 operate synchronously with the clock signal CLK supplied from the oscillator 138 of the test head 130.

[0117] The above is the structure of the front-end module 300.

[0118] According to this structure, the RAM 410 is installed on the pin electronic PCB 310 on which a plurality of pin electronic ICs 400 are installed. After temporarily storing a large amount of device signals in the RAM 410, they can be sent to the test head 130 through the pin controller 420. Thus, the transfer rate of the external bus BUS1 connecting the test head 130 and the pin electronic PCB 310 is designed to be significantly lower than the transfer rate of the DUT1.

[0119] In the test of high-speed devices, the inventor recognized that the noise contained in the power supply voltage V of the pin electronic IC 400 LDO has a great impact on the performance of the pin electronic IC 400. Based on this recognition, the linear regulator 440 is installed not on the test head 130 but on the Figure 13 pin electronic PCB 310. If the linear regulator 440 is provided on the test head 130, the power supply line becomes longer, so noise is mixed into the power supply voltage V LDO supplied to the pin electronic IC 400, and the performance of the pin electronic IC 400 may deteriorate. In contrast, by installing the linear regulator 440 on the pin electronic PCB 310, the power supply line from the linear regulator 440 to the pin electronic IC 400 can be shortened. Furthermore, the power supply voltage V LDOOnly through the wiring on the pin electronic PCB 310. Thus, the mixing of noise into the pin electronic IC 400 can be suppressed.

[0120] In addition, in Figure 13 the structure, the DC / DC converter 136 that becomes a noise source is arranged inside the test head 130 and separated from the linear regulator 440. Thus, the situation where the noise generated by the DC / DC converter 136 is mixed into the pin electronic IC 400 can be suppressed.

[0121] In addition, the oscillator 138 that generates the clock signal CLK is not arranged on the pin electronic PCB 310 but in the test head 130. Thus, the oscillator 138 as a noise source can be separated from the analog blocks such as the pin electronic IC 400 and the linear regulator 440, and the degradation of the performance of their circuits can be suppressed.

[0122] Figure 14 is a simplified layout diagram of the pin electronic PCB 310. A plurality of pin electronic ICs 400 are mounted along the first side E1 of the pin electronic PCB 310 closest to the DUT 1. Thus, a plurality of pin electronic ICs 400 can be close to the DUT, and the transmission distance of the test signal and the device signal can be shortened.

[0123] When the extending direction of the first side E1 is set as the first direction (Y direction) and the direction perpendicular thereto is set as the second direction (Z direction), the pin controller 420 is arranged at the center of the pin electronic PCB 310 with respect to the first direction (Y direction), and in a region closer to the second side E2 opposite to the first side E1 than the center of the pin electronic PCB 310 with respect to the second direction (Z direction). According to this layout, the pin electronic IC 400 is arranged at a position far from the test head 130 as a heat source and a noise source, and the pin controller 420 is arranged at a position close to the test head 130. Thus, the degradation of the characteristics of the front-end module 300 can be suppressed.

[0124] The interface device 200 has various forms, but the present disclosure can be applied to any form.

[0125] ·SBC (Socket Board Change) type

[0126] The SBC type is an interface device that replaces the socket board 210 according to the type of the DUT.

[0127] ·CLS (Cable Less) type

[0128] The CLS type is an interface device 200 that can be separated into an upper DSA (Device Specific Adapter) and a lower main board, and can replace the type of DSA according to the type of DUT. When applying the interface device 200 of the present embodiment to the CLS type, two methods can be considered.

[0129] One is the method of arranging the front-end module 300 on the main-board side. In this case, the front-end module 300 can be shared in the tests of different DUTs, so it is advantageous from the perspective of cost.

[0130] The other is the method of arranging the front-end module 300 on the DSA side. In this case, the front-end module 300 is set according to each DSA, so the cost of the device increases. On the other hand, the front-end module 300 can be close to the DUT, so it is advantageous from the perspective of high-speed tests.

[0131] ·CCN (Cable Connection) type

[0132] The CCN type is an interface device that replaces the entire interface device 200 according to the type of DUT. If the interface device 200 of the present embodiment is applied to the CCN type, the front-end module 300 can be brought as close as possible to the DUT, so it is advantageous from the perspective of high-speed tests.

[0133] · Wafer main board

[0134] The interface device 200 can be a wafer main board used in wafer-level tests. In this case, the interface device 200 can be equipped with a probe card instead of a socket board.

[0135] Next, the layout of the pin electronic IC 400 will be described. With the high-speed operation of the DUT, the heat generation of the pin electronic IC 400 is very large, and countermeasures are required.

[0136] Figure 15 It is a top view showing the layout of the pin electronic IC 400. The pin electronic IC 400 is integrated on the semiconductor chip (die) 500. The pin electronic IC 400 has two dummy regions 502 and 504 at both ends in the first direction (horizontal in the drawing). No active elements that become heat sources are arranged in the dummy regions 502 and 504. The active elements that become heat sources can include transistors that are always on, transistors that perform switching, etc. Conversely, in the dummy regions 502 and 504, active elements that do not become heat sources, that is, active elements with substantially zero power consumption, such as MOS capacitors, can be arranged.

[0137] In the region sandwiched by dummy regions 502 and 504 (hereinafter, also referred to as the functional region) 506, a main circuit 508 having the function of mounting the pin electronic IC 400 is formed.

[0138] The above is the structure of the pin electronic IC 400. Next, its operation will be described.

[0139] The pin electronic IC 400 operates through the main circuit 508 to generate heat in the functional region 506. This heat diffuses to the two adjacent dummy regions 502 and 504 along the first direction (the plane of the paper, the left - right direction). That is, the dummy regions 502 and 504 function as heat sinks for silicon. Therefore, the temperature rise of the main circuit 508 can be suppressed.

[0140] In the present embodiment, the semiconductor chip 500 is a rectangle with the first direction as the long side. Thus, the width W of the dummy regions 502 and 504 can be increased.

[0141] It should be noted that the dummy regions 502 and 504 should not be confused with the I / O region. In the I / O region, it is used to configure surge and ESD (electro - static discharge) protection elements around the bonding I / O pads, but the width of the I / O region is at most several hundred μm. In contrast, the dummy regions 502 and 504 of the present embodiment each have a width W of at least 1 mm, preferably 3 mm or more, and their sizes and functions are completely different.

[0142] The length W of each of the two dummy regions 502 and 504 in the first direction can be longer than 1 / 5 of the length L of the functional region 506 forming the main circuit 508 in the first direction.

[0143] Preferably, since the pin electronic IC 400 is housed in an FC - PGA package, there are no bonding pads around the semiconductor chip 500.

[0144] Figure 16 It is a perspective view showing the structure of the dummy regions 502 and 504. A power grid can be formed in the two dummy regions 502 and 504. The power grid is a structure in which a plurality of power distribution lines of the power supply (VDD) rail and a plurality of ground distribution lines of the ground (VSS) rail are formed in a grid pattern over multiple layers. It should be noted that although omitted in Figure 16 different - layer power distribution lines are connected to each other by vias, and different - layer ground distribution lines are also connected to each other by vias.

[0145] In each wiring layer, the power distribution line VDD and the ground distribution line VSS are alternately formed in the same direction. Moreover, in adjacent wiring layers, the laying directions of the wirings are orthogonal.

[0146] In a normal LSI, it is difficult to form a power grid over a large area in multiple layers. However, in this embodiment, a wide dummy region 502, 504 can be utilized as a formation region of the power grid. As a result, the impedance of the power supply decreases, and thus the power integrity can be improved. A power grid with a larger area can have a very large parasitic capacitance, which contributes to the stability of the power supply voltage.

[0147] MOS capacitors connected to the power grid can be formed in the dummy regions 502 and 504. As a result, the stability of the power supply voltage can be further improved.

[0148] In addition, the power supply wiring and the ground wiring forming the power grid have a high thermal conductivity. Therefore, the heat generated in the main circuit 508 diffuses outward via the power grid. That is, the power grid provides a cooling mechanism in addition to the stability of the power supply voltage.

[0149] Figure 17 It is an exploded perspective view of the condensation plate 320. The condensation plate 320 has a structure in which two plates formed with a curved groove 321 are bonded. The groove 321 serves as a flow path for the refrigerant.

[0150] Figure 18 It is a perspective view for explaining the cooling of the semiconductor chip 500 based on the condensation plate 320. The condensation plate 320 is joined to the semiconductor chip 500 in a form in which the cooling flow path 321 of the condensation plate 320 is along the first direction of the semiconductor chip 500. That is, the refrigerant in the cooling flow path 321 flows from the dummy region 502 toward 504 or in the opposite direction, crossing the functional region 506. As a result, the heat generated in the functional region 506 can escape toward the dummy regions 502 and 504.

[0151] Figure 19 It is a cross-sectional view showing the package structure of the pin electronic IC 400.

[0152] The pin electronic IC 400 has an FC-PGA (Flip Chip-Pin Grid Array) package. The pin electronic IC 400 includes a semiconductor chip 500 and an interposer 510, and the semiconductor chip 500 is flip chip mounted on the surface of the interposer 510. A ball grid 512 is formed on the back surface of the interposer 510. The pin electronic IC 400 is mounted on the printed circuit board 310.

[0153] The semiconductor chip 500 of the pin electronic IC 400 is a bare chip that is not resin-sealed (molded) and is thermally coupled to the condensation plate 320 via a thermal interface material (TIM) 322.

[0154] Taking the above-described embodiments as examples, those skilled in the art will recognize that various combinations of these components and processing steps include various variations. The following describes such variations.

[0155] (Variation 1)

[0156] It has been described that the intermediate layer is used as the connection interface between the FPC cable 222 and the pin electronic PCB 310, or between the FPC cable 222 and the socket board 210, but the present disclosure is not limited thereto.

[0157] (Variation 2)

[0158] In the embodiment, it has been described that the socket board 210 is the interface device 200 parallel to the ground, but the present disclosure is not limited thereto. For example, the socket board 210 can be perpendicular to the ground. In this case, Figure 5 、 Figure 6 the Y direction in etc. becomes the direction of gravity.

[0159] (Variation 3)

[0160] In the embodiment, as an example of the semiconductor integrated circuit having the Figure 15 structure, the pin electronic IC 400 has been described, but the type of the semiconductor integrated circuit is not limited, and it can also be applied to ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), GPU (Central Processing Unit), MPU (Micro-Processing Unit), DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), etc.

[0161] Regarding the embodiments of the present disclosure, although specific terms have been used for the description, this description is merely an illustrative example for understanding and does not limit the present disclosure or the claims. The scope of the present invention is defined by the claims, and thus, the embodiments, examples, and variations not described herein are also included in the scope of the present invention.

[0162] Industrial Applicability

[0163] The present disclosure relates to a semiconductor integrated circuit.

[0164] Symbol Description

[0165] 1 DUT

[0166] 100ATE

[0167] 120 Tester

[0168] 130 Test Head

[0169] 134 Bus Controller

[0170] 136 DC / DC Converter

[0171] 138 Oscillator

[0172] 140 Local Power Supply

[0173] 200 Interface Device

[0174] 210 Socket Board

[0175] 212 Socket

[0176] 214 Socket PCB

[0177] 216 Socket Board Side Connector

[0178] 218 Interposer

[0179] 219 Cable Clip

[0180] 220 Wiring

[0181] 222 FPC Cable

[0182] 230 Main Board

[0183] 250 Substrate

[0184] 252 Non-Deformable Electrode

[0185] 254 Deformable Electrode

[0186] 256 Opening

[0187] 300 Front-End Module

[0188] 310 Pin Electronic PCB

[0189] 312 FPC Connector

[0190] 314 Interposer

[0191] 316 Cable Clip

[0192] 320 Condensation Plate

[0193] 321 Cooling Flow Path

[0194] 400 Pin Electronic IC

[0195] 410 RAM

[0196] 420 Pin Controller

[0197] 430 Non-volatile Memory

[0198] 440 Linear Regulator

[0199] 450 D / A Converter

[0200] 500 Semiconductor Chip

[0201] 502, 504 dummy regions

[0202] 506 Functional Region

[0203] 508 Main Circuit

Claims

1. A semiconductor integrated circuit, characterized in that, Comprising: A semiconductor chip; Two dummy regions located on both sides of the semiconductor chip in a first direction, without transistors configured as heat sources; and The main circuit of the semiconductor integrated circuit, formed in a region sandwiched by the two dummy regions.

2. The semiconductor integrated circuit according to claim 1, wherein The semiconductor chip is a rectangle with the first direction as the long side.

3. The semiconductor integrated circuit according to claim 1 or 2, wherein A power grid is formed in the two dummy regions.

4. The semiconductor integrated circuit according to claim 3, wherein A MOS capacitor is connected to the power grid.

5. The semiconductor integrated circuit according to any one of claims 1 to 4, wherein The length of each of the two dummy regions in the first direction is 3 mm or more.

6. The semiconductor integrated circuit according to any one of claims 1 to 4, wherein The length of each of the two dummy regions in the first direction is longer than 1 / 5 of the length of the main circuit in the first direction.

7. A module, characterized in that, Comprising: The semiconductor integrated circuit according to any one of claims 1 to 6; and A condensation plate having a cooling flow path inside, the condensation plate being thermally coupled to the semiconductor integrated circuit, The cooling flow path of the condensation plate is parallel to the first direction.

8. The module according to claim 7, wherein The cooling flow path of the condensation plate includes a U-shaped portion facing the first direction and returning in the opposite direction.

9. The module according to claim 7 or 8, wherein The semiconductor chip of the semiconductor integrated circuit is not sealed, and the semiconductor chip is in contact with the condensation plate via a thermal conductive material.

10. The module according to any one of claims 7 to 9, wherein The semiconductor integrated circuit is an FC-PGA (Flip Chip-Pin Grid Array) package, mounted on a printed circuit board via an interposer.

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