Array substrate, color film substrate, display module and manufacturing method thereof

Abstract

The invention provides an array substrate, a color film substrate, a display module and a manufacturing method thereof, the array substrate is used for being in box alignment with the color film substrate, and the color film substrate is provided with a plurality of first alignment marks and a plurality of second alignment marks; the array substrate comprises a first substrate body and a second substrate body, the gate metal layer and the source-drain metal layer are arranged on the first substrate base plate and are arranged in a laminated mode, the gate metal layer comprises a plurality of patterns with third alignment marks, and the source-drain metal layer comprises a plurality of patterns with fourth alignment marks; wherein the third alignment mark is configured to be aligned with the first alignment mark, the fourth alignment mark is configured to be aligned with the second alignment mark, and the orthographic projection of the third alignment mark and the orthographic projection of the fourth alignment mark on the first substrate are at least partially not overlapped. According to the array substrate, the color film substrate, the display module and the manufacturing method of the display module, the quality of display products can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to an array substrate, a color filter substrate, a display module and a manufacturing method thereof. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the advantages of small volume, low power consumption, no radiation, etc., and occupies a dominant position in the current flat panel display market. When manufacturing a thin film transistor liquid crystal display, it is necessary to accurately align the array substrate and the color filter substrate. However, in related technologies, the alignment accuracy between the array substrate and the color filter substrate is poor, resulting in quality problems of the product. Summary of the Invention

[0003] In order to solve at least one technical problem in the prior art, embodiments of the present disclosure provide an array substrate, a color filter substrate, a display module and a manufacturing method thereof.

[0004] The technical solutions provided by the embodiments of the present disclosure are as follows:

[0005] In a first aspect, embodiments of the present disclosure provide an array substrate for being arranged in a cell with a color filter substrate, where a plurality of first alignment marks and a plurality of second alignment marks are arranged on the color filter substrate;

[0006] The array substrate includes:

[0007] A first substrate; and

[0008] A gate metal layer and a source-drain metal layer which are arranged on the first substrate and stacked, where the gate metal layer includes patterns of a plurality of third alignment marks, and the source-drain metal layer includes patterns of a plurality of fourth alignment marks; wherein, the third alignment marks are configured to be aligned with the first alignment marks, the fourth alignment marks are configured to be aligned with the second alignment marks, and at least a part of the orthographic projections of the third alignment marks and the fourth alignment marks on the first substrate do not overlap.

[0009] Exemplarily, the array substrate includes a plurality of pixel units arranged in an array, each pixel unit includes at least two sub-pixels that emit light of different colors, and in one pixel unit, at least two of the sub-pixels are arranged along a first direction;

[0010] Wherein, the fourth alignment marks are configured to be aligned with the second alignment marks at least in the first direction; the third alignment marks are configured to be aligned with the first alignment marks at least in a second direction, where the second direction intersects with the first direction.

[0011] Exemplarily, one of the third alignment marks and the first alignment mark is configured to have a hollow area, and the other is configured to have a solid area. When the array substrate is in a state of being aligned with the color filter substrate, the positive projection of the solid area and the hollow area on the first substrate at least partially overlap; and / or,

[0012] One of the fourth alignment marks and the second alignment mark is configured to have a hollow area, and the other is configured to have a solid area. When the array substrate is in a state of being aligned with the color filter substrate, the positive projection of the solid area and the hollow area on the first substrate at least partially overlap.

[0013] Exemplarily, when the array substrate is in a state of being aligned with the color filter substrate, the positive projection of the solid area on the first substrate is completely located within the positive projection of the hollow area on the first substrate, and in the first direction, the size of the solid area is smaller than the size of the hollow area; in the second direction, the size of the solid area is smaller than the size of the hollow area.

[0014] Exemplarily, the gate metal layer is located on a side of the source-drain metal layer close to the first substrate, and the array substrate further includes an insulating layer on a side of the gate metal layer facing away from the first substrate, and the insulating layer has an opening pattern; the opening pattern at least partially overlaps with the positive projection of the third alignment mark on the first substrate.

[0015] Exemplarily, the array substrate is an array display mother board, including a plurality of single substrate areas and a non-substrate area other than the single substrate areas, and the single substrate areas include a display area and a peripheral area located outside the display area; wherein,

[0016] At least a part of the third alignment marks and the fourth alignment marks are located in the peripheral area;

[0017] and / or, at least a part of the third alignment marks and the fourth alignment marks are located in the non-substrate area.

[0018] In a second aspect, an embodiment of the present disclosure provides a color filter substrate for being aligned and arranged with the above-mentioned array substrate, and a plurality of third alignment marks and a plurality of fourth alignment marks are provided on the array substrate; the color filter substrate includes:

[0019] A second substrate; and

[0020] A color filter layer and a black matrix provided on the second substrate, and the black matrix includes patterns of a plurality of the first alignment marks and a plurality of the second alignment marks.

[0021] In a third aspect, embodiments of the present disclosure provide a display module formed by aligning the above-described array substrate and the above-described color filter substrate; wherein,

[0022] The array substrate is further provided with a plurality of gate lines, a plurality of data lines intersecting with the gate lines, and a plurality of thin film transistors. The thin film transistors include a gate, a source, a drain, and a channel region. The gate metal layer further includes patterns of the gate lines and the gates, and the source-drain metal layer further includes patterns of the data lines, the sources, and the drains. Wherein, the positive projection of the black matrix on the first substrate at least completely covers the positive projections of the gate lines, the channel regions, and the data lines on the first substrate.

[0023] Exemplarily, the display module has a light incident side; wherein, the light incident side is the side of the color filter substrate facing away from the array substrate; or the light incident side is the side of the array substrate facing away from the color filter substrate.

[0024] In a fourth aspect, embodiments of the present disclosure provide a method for manufacturing a display module, the method including:

[0025] Fabricating the above-described array substrate;

[0026] Fabricating the above-described color filter substrate;

[0027] Aligning the array substrate and the color filter substrate. During alignment, the third alignment mark is aligned and matched with the first alignment mark, and the fourth alignment mark is aligned and matched with the second alignment mark.

[0028] The beneficial effects brought by the embodiments of the present disclosure are as follows:

[0029] In the above solution, by providing a third alignment mark on the gate metal layer and a fourth alignment mark on the source-drain metal layer, not only can the fourth alignment mark on the source-drain metal layer be used for alignment and matching with the color filter substrate during alignment, but also the third alignment mark on the gate metal layer can be used for alignment and matching with the color filter substrate. This can ensure both the alignment accuracy between the source-drain metal layer and the color filter substrate and the alignment accuracy between the gate metal layer and the color filter substrate, improve the alignment accuracy during alignment, and avoid product quality problems caused by abnormal alignment during alignment. Description of the Drawings

[0030] Figure 1 A top view schematic diagram showing the array display mother board and the color filter display mother board in an aligned state in some embodiments of the present disclosure;

[0031] Figure 2 A top view schematic diagram showing the array display mother board in some embodiments of the present disclosure;

[0032] Figure 3 A top view schematic diagram of a color filter display mother board in some embodiments of the present disclosure;

[0033] Figure 4 A schematic diagram showing the orthographic projection relationship of alignment marks on a color filter substrate and an array substrate on a first substrate in some embodiments of the present disclosure;

[0034] Figure 5 A schematic diagram of a partial area cross-sectional structure of a display module in some embodiments of the present disclosure. Detailed implementation manners

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0036] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an", or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "include" or "comprise" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0037] The features such as "parallel", "perpendicular", and "same" used in the embodiments of the present disclosure include the strict meanings of "parallel", "perpendicular", "same", etc., as well as the cases of "substantially parallel", "substantially perpendicular", "substantially same", etc. including certain tolerances. Considering the measurement and tolerances related to the measurement of specific quantities (for example, the limitations of the measurement system), it means within the acceptable deviation range for a specific value determined by those of ordinary skill in the art. For example, "substantially" can mean within one or more standard deviations, or within 3% or 5% of the value.

[0038] In addition, in this document, unless otherwise defined, the terms "substantially", "essentially", "about", and "approximately" are used to describe and account for small variations. When used in connection with an event or circumstance, these terms can cover both instances where the event or circumstance occurs precisely and instances where it occurs approximately. For example, when used in connection with a numerical value, these terms can include a variation range of less than or equal to 10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, less than or equal to ±0.05%. The term "substantially coplanar" can mean that two surfaces are arranged in the same plane within a micrometer range, for example, arranged in the same plane within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm.

[0039] It should be understood that in the exemplary embodiments of the present disclosure, when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can also be an intermediate layer between the layer or element and the other layer or substrate. "A and B are arranged on the same layer" means that after A and B are formed into a film layer for forming a specific pattern using the same film-forming process, a layer structure is formed through a single patterning process using the same mask.

[0040] Before providing a detailed description of the array substrate, color filter substrate, display module, and their manufacturing methods provided by the embodiments of the present disclosure, the related technologies are described as follows:

[0041] When manufacturing a Thin Film Transistor Liquid Crystal Display (TFT-LCD), it is necessary to accurately align the array substrate and the color filter substrate. However, in the related technologies, abnormal alignment occurs when the array substrate and the color filter substrate are mated, resulting in quality problems in the product.

[0042] The applicant of the present disclosure has found through research that one of the reasons for the above problems is:

[0043] The display panel is formed by laminating the color filter substrate and the array substrate, and liquid crystal is filled between the two. The deflection of the liquid crystal is controlled by an electric field to achieve the control and adjustment of the transmitted light.

[0044] The color filter substrate includes a color filter layer and a Black Matrix (BM). As an important layer in the color filter substrate, the black matrix mainly plays a role in light shielding and the subsequent production of alignment marks (Marks).

[0045] The array substrate includes a gate metal layer and a source / drain metal layer. The gate metal layer is mainly used to form patterns such as gate lines and gates of thin-film transistors, and the source / drain metal layer is mainly used to form patterns such as data lines, and source and drain electrodes of thin-film transistors. During the fabrication of the array substrate, alignment between the film layers is performed between the gate metal layer and the source / drain metal layer. Alignment marks that are aligned with the black matrix are provided on the source / drain metal layer. When the array substrate is mated with the color filter substrate, the alignment accuracy during mating is controlled by the alignment marks on the source / drain metal layer cooperating with the alignment marks of the black matrix.

[0046] Since the gate metal layer is not directly aligned with the color filter substrate, but the spacing control is performed through the alignment accuracy between the source / drain metal layer and the black matrix. When aligning the film layers between the source / drain metal layer and the gate metal layer, there will be a certain alignment error between the two film layers themselves. And when aligning the source / drain metal layer with the black matrix, there will also be a certain alignment error between the two film layers themselves. This results in that in actual production, the alignment accuracy control between the source / drain metal layer and the black matrix is better, while the alignment deviation between the gate metal layer and the black matrix is larger, thus leading to product quality problems.

[0047] For example, sub-pixels of different colors (such as RGB) in a pixel unit are arranged along a first direction, and the first direction is the color bleeding direction, and the second direction intersecting the first direction is the non-color bleeding direction. For example, the first direction can be the gate line extension direction, and the second direction can be the data line extension direction.

[0048] For the color bleeding direction, precise alignment control can be performed through the cooperation of the alignment marks on the source / drain metal layer and the alignment marks of the black matrix to avoid color bleeding between sub-pixels of different colors. For the non-color bleeding direction, the black matrix needs to block the gate lines and the channel regions of the thin-film transistors. However, due to the large alignment deviation between the black matrix and the gate metal layer, the alignment accuracy control in the non-color bleeding direction is poor, resulting in problems such as insufficient light shielding of the channel regions of the thin-film transistors by the black matrix and the influence on the pixel aperture ratio, thus affecting the product quality.

[0049] For example, the active layer of a low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS for short), and the active layer of an oxide thin-film transistor uses an oxide semiconductor (Oxide). For a display product where the backlight source is incident on the liquid crystal cell from the color filter substrate side, such as a projection display product, if the alignment between the gate metal layer and the black matrix is abnormal, light will irradiate the channel region of the thin-film transistor. When the channel region of the thin-film transistor is irradiated by strong light, the leakage current increases, leading to a high incidence of image sticking, crosstalk, and flicker defects, thereby affecting the display. For example, for a display product where the backlight source is incident on the liquid crystal cell from the array substrate side, if the alignment between the gate metal layer and the black matrix is abnormal, the pixel openings on the array substrate and the pixel openings of the black matrix will be misaligned, and the overlapping area between the pixel openings on the array substrate and the pixel openings of the black matrix will decrease, thereby affecting the pixel aperture ratio.

[0050] Based on this, to solve at least one of the above-mentioned related technical problems, embodiments of the present disclosure provide an array substrate, a color filter substrate, a display module, and a manufacturing method thereof.

[0051] The array substrate provided by the embodiments of the present disclosure is used for setting a cell with the color filter substrate.

[0052] As Figure 1 and Figure 3 shown, a plurality of first alignment marks 101 and a plurality of second alignment marks 102 are provided on the color filter substrate 100.

[0053] For example, please refer to Figure 5 shown, the color filter substrate 100 may include a second substrate 110, and a color filter layer 120 and a black matrix 130 located on the second substrate 110.

[0054] The color filter layer 120 may include color filters corresponding to sub-pixels, such as a red filter, a green filter, and a blue filter. The black matrix 130 may be located between adjacent color filters. The first alignment mark 101 and the second alignment mark 102 may be obtained by patterning the black matrix 130.

[0055] For example, the pattern of the black matrix 130 may include pixel openings 131 for defining sub-pixels, and the color filters are located in the pixel openings 131. The first alignment mark 101 and the second alignment mark 102 may be formed by the same lithography process as the pixel openings 131. However, this is not limited thereto.

[0056] As Figure 5As shown, the array substrate 200 includes: a first substrate 210; and a gate metal layer 220 and a source-drain metal layer 230 which are disposed on the first substrate 210 and stacked. Among them, the gate metal layer 220 may include patterns such as gate lines and gates 221 of thin film transistors, and the source-drain metal layer 230 may include patterns such as data lines and sources 231 and drains 232 of thin film transistors. The gate lines and the data lines may cross each other to define a plurality of pixel openings.

[0057] In addition, the gate metal layer 220 further includes patterns of several third alignment marks 201. For example, as Figure 5 shown, the third alignment marks 201 may be provided on the same layer and made of the same material as the gates 221 and the gate lines. The source-drain metal layer 230 further includes patterns of several fourth alignment marks 202, and the fourth alignment marks 202 may be provided on the same layer and made of the same material as the sources 231, the drains 232, and the data lines.

[0058] The third alignment marks 201 are configured to be aligned with the first alignment marks 101. In other words, during cell alignment, the positive projections of the third alignment marks 201 and the first alignment marks 101 on the first substrate 210 at least partially overlap.

[0059] The fourth alignment marks 202 are configured to be aligned with the second alignment marks 102. In other words, during cell alignment, the positive projections of the fourth alignment marks 202 and the second alignment marks 102 on the first substrate 210 at least partially overlap. Moreover, the positive projections of the third alignment marks 201 and the fourth alignment marks 202 on the first substrate 210 at least partially do not overlap.

[0060] In the above solution, by providing the third alignment marks 201 on the gate metal layer 220 and the fourth alignment marks 202 on the source-drain metal layer 230, not only can the fourth alignment marks 202 on the source-drain metal layer 230 be used for cell alignment with the color filter substrate 100, but also the third alignment marks 201 on the gate metal layer 220 can be used for cell alignment with the color filter substrate 100.

[0061] In this way, the alignment accuracy control of the source-drain metal layer 230 and the color filter substrate 100 can be achieved, and the alignment accuracy of the gate metal layer 220 and the color filter substrate 100 can be ensured. Compared with the related art in which the alignment accuracy of the gate metal layer 220 and the color filter substrate 100 is indirectly controlled by controlling the alignment accuracy of the source-drain metal layer 230 and the color filter substrate 100, in the present disclosure, the third alignment mark 201 is directly aligned with the first alignment mark 101 to control the alignment accuracy between the gate metal layer 220 and the color filter substrate 100, which can improve the alignment accuracy of the cell and avoid product quality problems caused by poor alignment accuracy of the cell.

[0062] In some exemplary embodiments, the array substrate 200 includes a plurality of pixel units arranged in an array, and each pixel unit includes at least two sub-pixels that emit light of different colors. In one pixel unit, at least two of the sub-pixels are arranged along a first direction X. For example, the pixel unit includes a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B), and at least two of the red sub-pixel (R), the green sub-pixel (G), and the blue sub-pixel (B) can be arranged along the first direction X. The first direction X is the color bleeding direction. For example, the first direction X can be the extending direction of the gate line.

[0063] Among them, the fourth alignment mark 202 is configured to be aligned with the second alignment mark 102 at least in the first direction X; the third alignment mark 201 is configured to be aligned with the first alignment mark 101 at least in a second direction Y. The second direction Y intersects with the first direction X. For example, the second direction Y is perpendicular to the first direction X. The second direction Y is the non-color bleeding direction. For example, the second direction Y can be the extending direction of the data line.

[0064] In this way, in the color bleeding direction, at least the alignment accuracy control can be achieved by the fourth alignment mark 202 on the source-drain metal layer 230 and the second alignment mark 102 on the color filter substrate 100 to avoid color bleeding between pixels. And, in the non-color bleeding direction, at least the alignment accuracy control can be achieved by the third alignment mark 201 on the gate metal layer 220 and the first alignment mark 101 on the color filter substrate 100 to solve problems such as insufficient light shielding of the channel region of the thin film transistor by the black matrix 130 on the color filter substrate 100 and the influence on the pixel aperture ratio 131 in the related art, thereby improving product quality.

[0065] For example, for a display product in which the backlight source is incident on the liquid crystal cell from the side of the color filter substrate 100, such as a projection display product, the gate metal layer 220 is accurately aligned with the black matrix 130, which can prevent light from irradiating the channel region of the thin film transistor, thereby avoiding an increase in leakage current when the channel region of the thin film transistor is irradiated by strong light, and reducing the high incidence of image sticking, crosstalk, and flicker defects, and thus improving the display quality. For example, for a display product in which the backlight source is incident on the liquid crystal cell from the side of the array substrate 200, the gate metal layer 220 is accurately aligned with the black matrix 130, which can ensure that the overlapping area of the pixel opening 131 on the array substrate 200 and the pixel opening 131 of the black matrix 130 is larger, thereby increasing the pixel opening 131 rate.

[0066] In addition, it should be noted that in some embodiments, the third alignment mark 201 may be disposed on the same layer and made of the same material as the gate 221 and the gate line, and the fourth alignment mark 202 may be disposed on the same layer and made of the same material as the source 231, the drain 232, and the data line.

[0067] In this way, the third alignment mark 201 can truly reflect the positions of patterns such as the gate 221 and the gate line in the gate metal layer 220, and the fourth alignment mark 202 can truly reflect the positions of patterns such as the source 231, the drain 232, and the data line in the source-drain metal layer 230. Moreover, without adding a new mask, no additional process is required, and the alignment accuracy of the cell can be improved without increasing the cost.

[0068] In some exemplary embodiments, as Figure 4 shown, the third alignment mark 201 and the first alignment mark 101 are configured such that one of them has a hollow area S1 and the other has a solid area S2. When the array substrate 200 is in a state of being aligned with the color filter substrate 100, the solid area S2 and the hollow area S1 overlap at least partially in the positive projection on the first substrate 210.

[0069] In some exemplary embodiments, as Figure 4 shown, the fourth alignment mark 202 and the second alignment mark 102 are configured such that one of them has a hollow area S1 and the other has a solid area S2. When the array substrate 200 is in a state of being aligned with the color filter substrate 100, the solid area S2 and the hollow area S1 overlap at least partially in the positive projection on the first substrate 210.

[0070] It should be noted that the fourth alignment mark 202 is configured to be aligned with the second alignment mark 102 at least in the first direction X. For example, the pattern of the fourth alignment mark 202 can be configured to be aligned with the second alignment mark 102 not only in the first direction X but also in the second direction Y. The third alignment mark 201 is configured to be aligned with the first alignment mark 101 at least in the second direction Y. For example, the pattern of the third alignment mark 201 can be configured to be aligned with the first alignment mark 101 not only in the second direction Y but also in the first direction X.

[0071] In other words, both the third alignment mark 201 and the fourth alignment mark 202 can be configured to achieve alignment control with the color filter substrate 100 in both the first direction X and the second direction Y.

[0072] For example, as Figure 4 shown, the first alignment mark 101 has the hollow area S1, and the third alignment mark 201 has the solid area S2. During cell alignment, the orthographic projection of the solid area S2 of the third alignment mark 201 on the first substrate 210 can be located within the orthographic projection of the hollow area S1 of the first alignment mark 101 on the first substrate 210. At this time, the third alignment mark 201 cooperates with the first alignment mark 101 to achieve the purpose of controlling the alignment accuracy in both the first direction X and the second direction Y.

[0073] Correspondingly, as Figure 4 shown, the second alignment mark 102 has the hollow area S1, and the fourth alignment mark 202 has the solid area S2. During cell alignment, the orthographic projection of the solid area S2 of the fourth alignment mark 202 on the first substrate 210 can be located within the orthographic projection of the hollow area S1 of the second alignment mark 102 on the first substrate 210. At this time, the fourth alignment mark 202 cooperates with the second alignment mark 102 to achieve the purpose of controlling the alignment accuracy in both the first direction X and the second direction Y.

[0074] For example, the orthographic projection shape of the hollow area S1 on the first substrate 210 can be any suitable shape such as a rectangle, a circle, an ellipse, a cross, a T shape, etc. The solid area S2 is adapted to the shape and size of the hollow area S1, and the orthographic projection shape of the solid area S2 on the first substrate 210 can be any suitable shape such as a rectangle, a circle, an ellipse, a cross, a T shape, etc.

[0075] by Figure 4 As shown in the example, the hollow area S1 is a rectangle, and the solid area S2 is a rectangle that matches the hollow area S1.

[0076] For example, see Figure 4 As shown, when the array substrate 200 is in a box-matching state with the color film substrate 100, the orthographic projection of the entity area S2 on the first base substrate 210 is completely located within the orthographic projection of the hollow area S1 on the first base substrate 210, and in the first direction X, the size of the entity area S2 is smaller than the size of the hollow area S1; in the second direction Y, the size of the entity area S2 is smaller than the size of the hollow area S1.

[0077] In the first direction X, the size of the gap between the physical area S2 and the hollow area S1 depends on the alignment deviation threshold allowed by the process in the first direction X; in the second direction Y, the size of the gap between the physical area S2 and the hollow area S1 depends on the alignment deviation threshold allowed by the process in the second direction Y.

[0078] It should be noted that the above is an exemplary description of the alignment mark patterns on the color filter substrate 100 , the source / drain metal layer 230 , and the gate metal layer 220 . However, the patterns of the alignment marks are not limited thereto.

[0079] Furthermore, in some exemplary embodiments, Figure 5 As shown, the gate metal layer 220 is located on the side of the source-drain metal layer 230 close to the first base substrate 210. For example, the thin film transistor may be a bottom gate structure. The array substrate 200 may further include an insulating layer 240 located on the side of the gate metal layer 220 away from the first base substrate 210, and an opening pattern 241 may be provided on the insulating layer 240; wherein the opening pattern 241 at least partially overlaps with the orthographic projection of the third alignment mark 201 on the first base substrate 210, so that the third alignment mark 201 can be exposed on the surface of the array substrate 200, so that the third alignment mark 201 can be identified and aligned.

[0080] In some exemplary embodiments, Figures 1 to 3As shown, the array substrate 200 provided by the present disclosure may be an array display mother board, which may include a plurality of single substrate regions P and a non-substrate region other than the single substrate region P. The single substrate region P includes a display region AA and a peripheral region B located outside the display region AA. At least part of the third alignment mark 201 and the fourth alignment mark 202 are located in the peripheral region B; and / or at least part of the third alignment mark 201 and the fourth alignment mark 202 are located in the non-substrate region.

[0081] In the above solution, the third alignment mark 201 and the fourth alignment mark 202 may be arranged in the peripheral region B of the single substrate region P or in the non-substrate region on the mother board of the array substrate 200. In practical applications, the specific positions of the third alignment mark 201 and the fourth alignment mark 202 can be reasonably selected based on the layout design of the mother board of the array substrate 200.

[0082] For example, in some embodiments, several of the third alignment marks 201 and several of the fourth alignment marks 202 can be distributed in the non-substrate region of the array substrate mother board and are located at the four corner positions of the array substrate mother board. For example, in some other embodiments, several of the third alignment marks 201 and several of the fourth alignment marks 202 can be distributed in the non-substrate region of the array substrate mother board, and the non-substrate region includes a first side region extending along the first direction X and a second side region extending along the second direction Y. Several of the third alignment marks 201 and several of the fourth alignment marks 202 can be distributed in the first side region and / or the second side region.

[0083] For example, in some other embodiments, several of the third alignment marks 201 and several of the fourth alignment marks 202 can be distributed in the peripheral region B and are located at the four corner positions of the single substrate region P. For example, in some other embodiments, several of the third alignment marks 201 and several of the fourth alignment marks 202 can be distributed in the peripheral region B and are located on at least one side of the display region AA in the first direction X and / or the second direction Y.

[0084] Correspondingly, the color filter substrate 100 may be a color filter display mother board, which may include a plurality of the single substrate regions P. The positions of the first alignment mark 101 and the second alignment mark 102 correspond to the positions of the third alignment mark 201 and the fourth alignment mark 202 respectively, which will not be elaborated here.

[0085] There is a cutting line area between adjacent single substrate areas P. After the mother board of the array substrate 200 and the mother board of the color filter substrate 100 are aligned and combined, the mother board of the liquid crystal cell is obtained. Along the cutting line area, the mother board of the liquid crystal cell is cut to obtain a single liquid crystal cell.

[0086] It should be noted that, in some other exemplary embodiments, the array substrate 200 provided by the embodiments of the present disclosure may also refer to a single substrate obtained by cutting the above-mentioned mother board of the array substrate 200. The array substrate 200 includes a display area AA and a peripheral area B located outside the display area AA. At least part of the third alignment marks 201 and the fourth alignment marks 202 are located in the peripheral area B.

[0087] Since the array substrate 200 provided by the embodiments of the present disclosure can not only ensure the alignment accuracy between the source-drain metal layer 230 and the color filter substrate 100, but also directly control the alignment accuracy between the gate metal layer 220 and the color filter substrate 100. In the display module obtained by aligning and combining the array substrate 200 provided by the embodiments of the present disclosure and the color filter substrate 100, a plurality of gate lines, a plurality of data lines intersecting with the gate lines, and a plurality of thin film transistors are provided on the array substrate 200. The thin film transistors include a gate 221, a source 231, a drain 232, and a channel region. The gate metal layer 220 further includes the patterns of the gate lines and the gate 221. The source-drain metal layer 230 further includes the patterns of the data lines, the source 231, and the drain 232. Wherein the positive projection of the black matrix 130 on the first substrate 210 at least completely covers the positive projections of the gate lines, the channel region, and the data lines on the first substrate 210.

[0088] In addition, the embodiments of the present disclosure provide a color filter substrate 100 for aligning and combining with the array substrate 200 of the embodiments of the present disclosure. A plurality of third alignment marks 201 and a plurality of fourth alignment marks 202 are provided on the array substrate 200; the color filter substrate 100 includes:

[0089] A second substrate 110; and

[0090] A color filter layer 120 and a black matrix 130 provided on the second substrate 110. The black matrix 130 includes the patterns of a plurality of the first alignment marks 101 and a plurality of the second alignment marks 102.

[0091] Since the principle of solving problems by this color filter substrate 100 is similar to that of the above-mentioned array substrate 200, therefore, the embodiments of the color filter substrate 100 provided by the embodiments of the present disclosure can refer to the embodiments of the above-mentioned array substrate 200 provided by the embodiments of the present disclosure, and will not be described in detail here.

[0092] An embodiment of the present disclosure provides a display module. Figure 5 The following shows a schematic cross-sectional view of a partial area of the display module provided by the embodiment of the present disclosure, where liquid crystal, pixel electrodes, common electrodes, etc. are not shown. As Figure 5 shown, the display module is formed by aligning the array substrate 200 of the embodiment of the present disclosure and the color filter substrate 100 of the embodiment of the present disclosure. Among them, a plurality of gate lines, a plurality of data lines intersecting with the gate lines, and a plurality of thin film transistors are provided on the array substrate 200. The thin film transistor includes a gate 221, a source 231, a drain 232, and a channel region. The gate metal layer 220 further includes patterns of the gate lines and the gate 221. The source-drain metal layer 230 further includes patterns of the data lines, the source 231, and the drain 232. Wherein, the positive projection of the black matrix 130 on the first substrate 210 at least completely covers the positive projections of the gate lines, the channel region, and the data lines on the first substrate 210.

[0093] The display module includes, but is not limited to, devices with display functions such as projectors, smartphones, monitors, laptop computers, tablet computers, electronic photo frames, dash cams, and smart wearable devices. Other essential components of the display module (such as a driving chip) should be understood by those of ordinary skill in the art and will not be elaborated here, nor should it be regarded as a limitation to the present disclosure. Since the principle of solving problems by this display module is similar to that of the above-mentioned array substrate 200, therefore, the embodiments of this display module provided by the embodiments of the present disclosure can refer to the embodiments of the above-mentioned array substrate 200 provided by the embodiments of the present disclosure and will not be elaborated here.

[0094] In some exemplary embodiments, the display module includes a display area AA and a peripheral area B located outside the display area AA. Among them, in the peripheral area B, a first alignment mark 101 and a second alignment mark 102 are provided on the color filter substrate 100, and a third alignment mark 201 and a fourth alignment mark 202 are provided on the array substrate 200.

[0095] In some exemplary embodiments, the display module has a light incident side; the light incident side is the side of the color filter substrate 100 facing away from the array substrate 200. For example, the display module can be a projection display module. In some other exemplary embodiments, the display module has a light incident side; the light incident side is the side of the array substrate 200 facing away from the color filter substrate 100.

[0096] In addition, an embodiment of the present disclosure provides a manufacturing method of a display module, the method includes:

[0097] Step S01: Fabricate the array substrate 200 of the present disclosure embodiment;

[0098] Step S02: Fabricate the color filter substrate 100 of the present disclosure embodiment;

[0099] Step S03: Align the array substrate 200 with the color filter substrate 100. During alignment, the third alignment mark 201 is in alignment cooperation with the first alignment mark 101, and the fourth alignment mark 202 is in alignment cooperation with the second alignment mark 102.

[0100] Among them, in the above step S01, when fabricating the array substrate 200, the third alignment mark 201 can be formed with other patterns such as the gate 221 and gate lines on the gate metal layer 220 through the same lithography process.

[0101] In the above step S02, when fabricating the color filter substrate 100, the fourth alignment mark 202 can be formed with other patterns such as the source electrode 231, drain electrode 232, and data lines on the source-drain metal layer 230 through the same lithography process.

[0102] The following points need to be explained:

[0103] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the conventional designs.

[0104] (2) For clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn to actual scale. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element or there can be intervening elements.

[0105] (3) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0106] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. An array substrate, characterized in that, Used for aligning with a color film substrate, the color film substrate is provided with a plurality of first alignment marks and a plurality of second alignment marks; the array substrate comprises: a first base substrate; and A gate metal layer and a source-drain metal layer are arranged on the first substrate and are stacked, the gate metal layer includes a pattern of a plurality of third alignment marks, and the source-drain metal layer includes a pattern of a plurality of fourth alignment marks; wherein the third alignment mark is configured to be aligned with the first alignment mark, the fourth alignment mark is configured to be aligned with the second alignment mark, and the orthographic projections of the third alignment mark and the fourth alignment mark on the first substrate at least partially do not overlap.

2. The array substrate according to claim 1, wherein The array substrate comprises a plurality of pixel units distributed in an array, each pixel unit comprises at least two sub-pixels emitting light of different colors, and in one of the pixel units, at least two of the sub-pixels are arranged along a first direction; The fourth alignment mark is configured to be aligned with the second alignment mark at least in the first direction; the third alignment mark is configured to be aligned with the first alignment mark at least in the second direction, wherein the second direction intersects the first direction.

3. The array substrate according to claim 2, wherein The third alignment mark and the first alignment mark are constructed such that one of them has a hollowed-out area and the other has a solid area, and when the array substrate is in a box-aligned state with the color filter substrate, the orthographic projections of the solid area and the hollowed-out area on the first base substrate at least partially overlap; and / or, The fourth alignment mark and the second alignment mark are constructed so that one of them has a hollowed-out area and the other has a solid area. When the array substrate is in a box-aligned state with the color film substrate, the orthographic projections of the solid area and the hollowed-out area on the first base substrate at least partially overlap.

4. The array substrate according to claim 3, wherein When the array substrate is in a box-matching state with the color film substrate, the orthographic projection of the entity area on the first base substrate is completely located within the orthographic projection of the hollow area on the first base substrate, and in the first direction, the size of the entity area is smaller than the size of the hollow area; in the second direction, the size of the entity area is smaller than the size of the hollow area.

5. The array substrate according to claim 1, characterized in that, The gate metal layer is located on a side of the source / drain metal layer close to the first substrate, and the array substrate also includes an insulating layer located on a side of the gate metal layer away from the first substrate, and the insulating layer has an opening pattern; the opening pattern at least partially overlaps with the orthographic projection of the third alignment mark on the first substrate.

6. The array substrate according to claim 1, wherein The array substrate is an array display motherboard, including a plurality of single substrate areas and non-substrate areas other than the single substrate areas, wherein the single substrate area includes a display area and a peripheral area located outside the display area; wherein, At least part of the third alignment mark and the fourth alignment mark is located in the peripheral area; and / or at least part of the third alignment mark and the fourth alignment mark is located in the non-substrate area.

7. A color film substrate, characterized in that, For use in alignment with an array substrate as described in any one of claims 1 to 6, wherein a plurality of third alignment marks and a plurality of fourth alignment marks are provided on the array substrate; the color filter substrate includes: A second substrate; and A color filter layer and a black matrix provided on the second substrate, the black matrix including patterns of a plurality of the first alignment marks and a plurality of the second alignment marks.

8. A display module, characterized in that, Formed by aligning an array substrate as described in any one of claims 1 to 6 and a color filter substrate as described in claim 7; wherein, A plurality of gate lines, a plurality of data lines intersecting with the gate lines, and a plurality of thin film transistors are further provided on the array substrate, the thin film transistors including a gate, a source, a drain, and a channel region, the gate metal layer further including patterns of the gate lines and the gate, the source-drain metal layer further including patterns of the data lines, the source, and the drain, wherein the orthographic projection of the black matrix on the first substrate at least completely covers the orthographic projections of the gate lines, the channel region, and the data lines on the first substrate.

9. The display module according to claim 8, wherein The display module has a light incident side; wherein, the light incident side is the side of the color filter substrate facing away from the array substrate; or the light incident side is the side of the array substrate facing away from the color filter substrate.

10. A manufacturing method of a display module, characterized in that, The method includes: Fabricating an array substrate as described in any one of claims 1 to 6; Fabricating a color filter substrate as described in claim 7; Aligning the array substrate with the color filter substrate, and during alignment, the third alignment marks are in alignment cooperation with the first alignment marks, and the fourth alignment marks are in alignment cooperation with the second alignment marks.

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