High-voltage pre-modulation circuit

Abstract

The invention discloses a high-voltage pre-modulation circuit. The high-voltage pre-modulation circuit comprises a port protection circuit, a self-starting biasing circuit, a reference circuit and a step-down modulation circuit, the port protection circuit has a negative voltage protection function, when the port voltage is negative voltage, voltage transmission can be blocked, and internal devices are prevented from being damaged; the self-starting bias circuit is quickly conducted when the power supply is powered on, provides bias current for the port protection circuit and provides bias voltage for the step-down modulation circuit; the reference circuit takes the output voltage of the step-down modulation circuit as the power supply voltage, and the output reference voltage of the reference circuit is the reference level of the step-down modulation circuit; the step-down modulation circuit can realize the function of converting high power supply voltage into low voltage VOUT, and provides stable power supply voltage for other modules in the integrated circuit. The high-voltage pre-modulation circuit with the negative-voltage protection function has the negative-voltage protection function, only one path of power supply voltage is needed, high reliability is achieved, and meanwhile the system design difficulty is lowered.

Description

Technical Field

[0001] The present invention belongs to the field of integrated electronic technology, and particularly relates to a high-voltage pre-modulation circuit. Background Art

[0002] As an important module for voltage conversion, the high-voltage pre-modulation circuit is widely used in analog and power integrated circuits such as power management and drivers. Power management circuits are usually designed using processes such as BiCMOS and BCD. They have high-voltage modules inside to ensure voltage withstand and functional requirements, and also include low-voltage analog and digital modules to meet the requirements of high precision, high response speed, and high integration of the circuit. The high-voltage pre-modulation circuit can convert a high power supply voltage into a low supply voltage to supply power to low-voltage domain modules such as digital logic circuits, amplifiers, and comparators inside the chip, which is the key to ensuring the function and performance of the circuit.

[0003] With the development of automotive electronics, aerospace, and new-generation information technology, electronic systems such as power control and high-order intelligent driving have put forward higher requirements for the performance and reliability of power management chips. How to improve the performance, reliability, and usability of chips is the main problem faced by current power management chips. The high-voltage pre-modulation circuit, as a voltage conversion module inside the chip, is a prerequisite for ensuring the overall circuit function and performance. In today's increasingly complex application scenarios, a high-voltage pre-modulation circuit with port protection and single-power supply has become an important development trend in the design of high-performance power management chips. Summary of the Invention

[0004] In order to overcome the deficiencies of the prior art, the present invention provides a high-voltage pre-modulation circuit, including: a port protection circuit, a self-starting bias circuit, a reference circuit, and a buck modulation circuit. The port protection circuit has a negative voltage protection function. When the port voltage is negative, it can block voltage transmission to prevent damage to internal devices. The self-starting bias circuit quickly conducts when the power is turned on, provides a bias current for the port protection circuit, and provides a bias voltage for the buck modulation circuit. The reference circuit uses the output voltage of the buck modulation circuit as the supply voltage, and its output reference voltage is the reference level for the buck modulation circuit. The buck modulation circuit can achieve the function of converting a high power supply voltage into a low voltage VOUT to provide a stable supply voltage for other modules inside the integrated circuit. The high-voltage pre-modulation circuit designed by the present invention with negative voltage protection has a negative voltage protection function, only requires one power supply voltage, reduces the system design difficulty while achieving high reliability, and can be widely used in power management and protection control chips in fields such as automotive electronics, aerospace, and industrial control.

[0005] The technical solution adopted by the present invention to solve its technical problems is as follows:

[0006] A high-voltage pre-modulation circuit, comprising: a port protection circuit, a self-starting bias circuit, a reference circuit, and a buck modulation circuit.

[0007] The port protection circuit adopts a back-to-back P-type LDMOS design for the negative voltage protection port involved in the power input, which can block the negative voltage path and prevent device damage caused by intrusion into the internal circuit.

[0008] The self-starting bias circuit conducts when the power is turned on, providing a bias current IB1 for the port protection circuit, a bias current IB2 and a bias voltage VB1 for the buck modulation circuit, enabling the buck modulation circuit to quickly break away from the degeneracy point and perform a steady-state output.

[0009] The reference circuit superimposes the positive temperature coefficient voltage generated by the transistor operating at different current densities and the negative temperature coefficient voltage between the base and emitter of the transistor to obtain a bandgap reference voltage, providing a reference level for the buck modulation circuit, and introducing a negative feedback loop to maintain the stability of the reference voltage.

[0010] The buck modulation circuit forms a negative feedback closed-loop system through an error amplifier, a power transistor, and a feedback resistor network. When the input voltage or load current changes, the change in the output voltage is suppressed through the feedback regulation of the negative feedback closed-loop system, providing a stable operating voltage for other modules.

[0011] Preferably, the port protection circuit includes: PMOS transistors MP1, MP2; NMOS transistors MN1, MN2, MN3, MN4; and a resistor R1.

[0012] The drain of the PMOS transistor MP1 serves as the input terminal of the port protection circuit, connected to the external power supply voltage VIN; the gate of MP1 is connected to the gates of the PMOS transistor MP2, the gate and source of the NMOS transistor MN1, the source of the NMOS transistor MN4, and the positive pole of the resistor R1, and the source of MP1 is connected to the source of the PMOS transistor MP2, the drain of the NMOS transistor MN1, and the gate and drain of the NMOS transistor MN2.

[0013] The drain of the PMOS transistor MP2 serves as the output terminal of the port protection circuit, providing a power supply voltage VP for the buck modulation circuit.

[0014] The source of the NMOS transistor MN2 is connected to the gate and drain of the NMOS transistor MN3.

[0015] The source of the NMOS transistor MN3 is connected to the gate and drain of the NMOS transistor MN4.

[0016] The negative pole of the resistor R1 is connected to the bias current IB1 provided by the self-starting bias circuit.

[0017] Preferably, the self-starting bias circuit includes: NPN transistors Q1, Q2, Q3, Q4, Q5; NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8; PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6; resistors R1, R2, R3, R4;

[0018] The positive electrode of the resistor R1 is connected to the power supply voltage VDD after passing through the diode; the source electrodes of the PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6 are connected to the power supply voltage VDD after passing through the diode;

[0019] The emitters of the NPN transistors Q1, Q4, Q5 are grounded; the negative electrodes of the resistors R2, R3, R4 are grounded; the source electrodes of the NMOS transistors MN6, MN8 are grounded;

[0020] The negative electrode of the resistor R1 is connected to the gate and drain of the NMOS transistor MN1, and the gates of the NMOS transistors MN2 and MN3;

[0021] The source of the NMOS transistor MN1 is connected to the base and collector of the transistor Q1 and the base of the transistor Q2;

[0022] The gate of the PMOS transistor MP1 is connected to the gate and drain of the PMOS transistor MP2, and the drain of the NMOS transistor MN3; the drain of MP1 is connected to the drain of the NMOS transistor MN2 and the gates of the PMOS transistors MP3, MP4, MP5, MP6;

[0023] The source of the NMOS transistor MN2 is connected to the collectors of the transistors Q2 and Q3;

[0024] The emitter of the NPN transistor Q2 is connected to the emitter of the transistor Q3 and the positive electrode of the resistor R2;

[0025] The source of the NMOS transistor MN3 is connected to the collector of the transistor Q4;

[0026] The base of the NPN transistor Q4 is connected to the base of the transistor Q3, the base and collector of the transistor Q5, the drain of the PMOS transistor MP3, and the positive electrode of the resistor R3; the collector of Q4 is connected to the source of the NMOS transistor MN3;

[0027] The drain of the PMOS transistor MP4 is connected to the gate and drain of the NMOS transistor MN4, and a voltage VB is generated at this point to provide a bias voltage for the buck modulation circuit;

[0028] The source of the NMOS transistor MN4 is connected to the positive electrode of the resistor R4;

[0029] The drain of the PMOS transistor MP5 is connected to the gates and drains of the NMOS transistors MN5, and the gates of the NMOS transistors MN6, MN7, and MN8.

[0030] The drain of the PMOS transistor MP6 provides the bias current IB2 for the buck modulation circuit.

[0031] The source of the NMOS transistor MN5 is connected to the drain of the NMOS transistor MN6.

[0032] The source of the NMOS transistor MN7 is connected to the drain of the NMOS transistor MN8. The drain of MN7 provides the bias current IB1 for the port protection circuit.

[0033] Preferably, the reference circuit includes: PMOS transistors MP1, MP2, MP3, MP4; NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6; PNP transistors Q1, Q2, Q3, Q4, Q5; NPN transistors Q6, Q7; resistors R1, R2, R3, R4, R5, R6, R7, R8, R9; capacitor C1; inverter INV1.

[0034] The positive electrodes of the resistors R1, R2, R3, and R4 are connected to the stable voltage VOUT output by the buck modulation circuit; the emitters of the PNP transistors Q2, Q3, and Q4 are connected to the stable voltage VOUT output by the buck modulation circuit; the sources of the PMOS transistors MP2, MP3, and MP4 are connected to the stable voltage VOUT output by the buck modulation circuit.

[0035] The sources of the NMOS transistors MN1, MN2, MN3, MN4, MN5, and MN6 are grounded; the negative electrode of the resistor R8 is grounded; the collector of the transistor Q5 is grounded.

[0036] The negative electrode of the resistor R1 is connected to the input terminal of the inverter INV1 and the drain of the NMOS transistor MN2.

[0037] The output terminal of the inverter IN1 is connected to the gate of the PMOS transistor MP1.

[0038] The source of the PMOS transistor MP1 is connected to the negative electrode of the resistor R2, and the drain of MP1 is connected to the collector of the transistor Q1, the drain of the NMOS transistor MN3, and the gates of the NMOS transistors MN4 and MN5.

[0039] The base of the PNP transistor Q1 is connected to the negative electrode of the resistor R4, the drain of the MNOS transistor MN5, the bases and collectors of the transistors Q2 and Q3, and the bases of Q4. The emitter of Q1 is connected to the negative electrode of the resistor R3.

[0040] The collector of the PNP transistor Q3 provides a bias current IB3 for the buck modulation circuit;

[0041] The collector of the PNP transistor Q4 is connected to the gate and drain of the NMOS transistor MN1 and the gates of the NMOS transistors MN2 and MN3;

[0042] The drain of the NMOS transistor MN4 is connected to the gate and drain of the PMOS transistor MP2 and the gates of the PMOS transistors MP3 and MP4;

[0043] The drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN6, the base of the transistor Q5, and the positive electrode of the capacitor C1;

[0044] The drain of the PMOS transistor MP4 is connected to the emitter of the transistor Q5, the positive electrodes of the resistors R5 and R6, and a reference voltage VREF is generated at this point;

[0045] The negative electrode of the resistor R5 is connected to the base and collector of the transistor Q6 and the inverting input terminal of the amplifier AMP1;

[0046] The negative electrode of the resistor R6 is connected to the positive electrode of the resistor R7 and the non-inverting input terminal of the amplifier AMP1;

[0047] The negative electrode of the resistor R7 is connected to the base and collector of the transistor Q7;

[0048] The emitter of the NPN transistor Q6 is connected to the emitter of the transistor Q7 and the positive electrode of the resistor R8;

[0049] The output terminal of the amplifier AMP1 is connected to the gate of the NMOS transistor MN6 and the negative electrode of the resistor R9;

[0050] The negative electrode of the capacitor C1 is connected to the positive electrode of the resistor R9.

[0051] Preferably, the buck modulation circuit includes: NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12; PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6; resistors R1, R2, R3.

[0052] The positive electrode of the resistor R1 is connected to the output voltage VP of the port protection circuit; the sources of the PMOS transistors MP1, MP2, MP3, and MP6 are connected to the output voltage VP of the port protection circuit;

[0053] The sources of the NMOS transistors MN1, MN2, MN3, MN4, and MN8 are grounded; the negative electrode of the resistor R3 is grounded;

[0054] The gate and drain of the NMOS transistor MN1 are connected to the bias current IB3 of the reference circuit and are also connected to the gates of the NMOS transistors MN2, MN3, and MN4.

[0055] The gate and drain of the NMOS transistor MN5 are connected to the bias current IB2 of the self-starting bias circuit and are also connected to the gates of the NMOS transistors MN6, MN7, and MN8.

[0056] The negative pole of the resistor R1 is connected to the drain of the NMOS transistor MN6 and the gate of the PMOS transistor MP1.

[0057] The drain of the PMOS transistor MP1 is connected to the drains of the NMOS transistors MN7, MN12, the drain of the PMOS transistor MP3, and the gate of the PMOS transistor MP6.

[0058] The drain of the NMOS transistor MN2 is connected to the sources of the NMOS transistors MN7, MN9, and MN10 and the drain of the NMOS transistor MN8.

[0059] The gate of the NMOS transistor MN9 is connected to the output voltage VREF of the reference circuit. The drain of the NMOS transistor MN9 is connected to the drain of the PMOS transistor MP5, the source of the NMOS transistor MN12, and the drain of the NMOS transistor MN4.

[0060] The gate of the NMOS transistor MN10 is connected to the negative pole of the resistor R2 and the positive pole of the resistor R3. The drain of the NMOS transistor MN10 is connected to the drain of the PMOS transistor MP4, the source of the NMOS transistor MN11, and the drain of the NMOS transistor MN3.

[0061] The gate and drain of the PMOS transistor MP2 are connected to the drain of the NMOS transistor MN11.

[0062] The gate of the NMOS transistor MN11 is connected to the gates of the NMOS transistor MN12, the gates and sources of the PMOS transistors MP4 and MP5, and is connected to the bias voltage VB provided by the self-starting bias circuit.

[0063] The drain of the PMOS transistor MP6 is connected to the positive pole of the resistor R2 and serves as the output terminal of the buck modulation circuit with the voltage VOUT.

[0064] The negative pole of the resistor R3 is connected to GND.

[0065] The beneficial effects of the present invention are as follows:

[0066] The present invention adopts a port protection design, enabling the high-voltage pre-modulation circuit to have a negative voltage protection function and improving the reliability of the circuit. At the same time, by adopting the loop design of the self-starting bias circuit, the reference circuit, and the buck modulation circuit, the buck modulation function under single power supply is realized, reducing the system complexity. Description of the Drawings

[0067] Figure 1 It is the structural diagram of the high-voltage pre-modulation circuit provided by the embodiment of the present invention;

[0068] Figure 2 It is the circuit diagram of the port protection module of the present invention;

[0069] Figure 3 It is the circuit diagram of the self-starting bias module of the present invention;

[0070] Figure 4 It is the circuit diagram of the reference module of the present invention;

[0071] Figure 5 It is the circuit diagram of the buck modulation module of the present invention;

[0072] Figure 6 It is the simulation result of the comparison between the input and output voltages of the high-voltage pre-modulation circuit. Detailed implementation manners

[0073] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0074] Figure 1 It is the structural diagram of a high-voltage pre-modulation circuit provided by the embodiment of the present invention. It is characterized by including: a port protection circuit, a self-starting bias circuit, a reference circuit, and a buck modulation circuit.

[0075] The port protection circuit adopts a back-to-back P-type LDMOS design for the negative voltage protection port involved in the power input, which can block the negative voltage path and prevent it from being introduced into the internal circuit to cause device damage;

[0076] The self-starting bias circuit conducts quickly when the power is turned on, providing a bias current IB1 for the port protection circuit; providing a bias current IB2 and a bias voltage VB1 for the buck modulation circuit, enabling it to quickly get out of the degeneracy point and perform steady-state output;

[0077] The reference circuit superimposes the positive temperature coefficient voltage generated by making the transistor work at different current densities and the negative temperature coefficient voltage between the base and emitter of the transistor to obtain a bandgap reference voltage, providing a reference level for the buck modulation circuit; and introducing a negative feedback loop to maintain the stability of the reference voltage;

[0078] The buck modulation circuit consists of an error amplifier, a power transistor, and a feedback resistor network to form a negative feedback closed-loop system. When the input voltage or load current changes, the negative feedback regulation of its control loop suppresses the change of the output voltage, providing a stable working voltage for other modules.

[0079] Such as Figure 2As shown, the port protection circuit includes: PMOS transistors MP1 and MP2; NMOS transistors MN1, MN2, MN3, and MN4; and resistor R1.

[0080] The drain of the PMOS transistor MP1 serves as the input terminal of the port protection circuit and is connected to the external power supply voltage VIN. The gate of MP1 is connected to the gates of PMOS transistor MP2, NMOS transistor MN1's gate and source, NMOS transistor MN4's source, and the positive terminal of resistor R1. The source of MP1 is connected to the sources of PMOS transistor MP2, NMOS transistor MN1's drain, and NMOS transistor MN2's gate and drain.

[0081] The drain of the PMOS transistor MP2 serves as the output terminal of the port protection circuit and provides the power supply voltage VP for the buck modulation circuit.

[0082] The source of the NMOS transistor MN2 is connected to the gate and drain of NMOS transistor MN3.

[0083] The source of the NMOS transistor MN3 is connected to the gate and drain of NMOS transistor MN4.

[0084] The negative terminal of the resistor R1 is connected to the bias current IB1 provided by the self-starting bias circuit.

[0085] As Figure 3 As shown, the self-starting bias circuit includes: NPN transistors Q1, Q2, Q3, Q4, and Q5; NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, and MN8; PMOS transistors MP1, MP2, MP3, MP4, MP5, and MP6; and resistors R1, R2, R3, and R4.

[0086] The positive terminal of the resistor R1 is connected to the power supply voltage VDD after passing through a diode. The sources of PMOS transistors MP1, MP2, MP3, MP4, MP5, and MP6 are connected to the power supply voltage VDD after passing through a diode.

[0087] The emitters of the NPN transistors Q1, Q4, and Q5 are grounded. The negative terminals of the resistors R2, R3, and R4 are grounded. The sources of the NMOS transistors MN6 and MN8 are grounded.

[0088] The negative terminal of the resistor R1 is connected to the gate and drain of NMOS transistor MN1 and the gates of NMOS transistors MN2 and MN3.

[0089] The source of the NMOS transistor MN1 is connected to the base and collector of transistor Q1 and the base of transistor Q2.

[0090] The gate of the PMOS transistor MP1 is connected to the gates and drains of the PMOS transistors MP2, and the drain of the NMOS transistor MN3. The drain of MP1 is connected to the drain of the NMOS transistor MN2 and the gates of the PMOS transistors MP3, MP4, MP5, and MP6.

[0091] The source of the NMOS transistor MN2 is connected to the collectors of the transistors Q2 and Q3.

[0092] The emitter of the NPN transistor Q2 is connected to the emitters of the transistors Q3 and the positive pole of the resistor R2.

[0093] The source of the NMOS transistor MN3 is connected to the collector of the transistor Q4.

[0094] The base of the NPN transistor Q4 is connected to the bases of the transistors Q3, the base and collector of the transistor Q5, the drain of the PMOS transistor MP3, and the positive pole of the resistor R3. The collector of Q4 is connected to the source of the NMOS transistor MN3.

[0095] The drain of the PMOS transistor MP4 is connected to the gate and drain of the NMOS transistor MN4, and a voltage VB is generated at this point to provide a bias voltage for the buck modulation circuit.

[0096] The source of the NMOS transistor MN4 is connected to the positive pole of the resistor R4.

[0097] The drain of the PMOS transistor MP5 is connected to the gate and drain of the NMOS transistor MN5, and the gates of the NMOS transistors MN6, MN7, and MN8.

[0098] The drain of the PMOS transistor MP6 provides a bias current IB2 for the buck modulation circuit.

[0099] The source of the NMOS transistor MN5 is connected to the drain of the NMOS transistor MN6.

[0100] The source of the NMOS transistor MN7 is connected to the drain of the NMOS transistor MN8. The drain of MN7 provides a bias current IB1 for the port protection circuit.

[0101] As Figure 4 shown, the reference circuit includes: PMOS transistors MP1, MP2, MP3, MP4; NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6; PNP transistors Q1, Q2, Q3, Q4, Q5; NPN transistors Q6, Q7; resistors R1, R2, R3, R4, R5, R6, R7, R8, R9; capacitor C1; inverter INV1.

[0102] The positive electrodes of the resistors R1, R2, R3, and R4 are connected to the stable voltage VOUT output by the buck modulation circuit; the emitters of the PNP transistors Q2, Q3, and Q4 are connected to the stable voltage VOUT output by the buck modulation circuit; the sources of the PMOS transistors MP2, MP3, and MP4 are connected to the stable voltage VOUT output by the buck modulation circuit;

[0103] The sources of the NMOS transistors MN1, MN2, MN3, MN4, MN5, and MN6 are grounded; the negative electrode of the resistor R8 is grounded; the collector of the transistor Q5 is grounded;

[0104] The negative electrode of the resistor R1 is connected to the input terminal of the inverter INV1 and the drain of the NMOS transistor MN2;

[0105] The output terminal of the inverter IN1 is connected to the gate of the PMOS transistor MP1;

[0106] The source of the PMOS transistor MP1 is connected to the negative electrode of the resistor R2, the drain of MP1 is connected to the collector of the transistor Q1, the drain of the NMOS transistor MN3, and the gates of the NMOS transistors MN4 and MN5;

[0107] The base of the PNP transistor Q1 is connected to the negative electrode of the resistor R4, the drain of the MNOS transistor MN5, the base and collector of the transistor Q2, and the bases of Q3 and Q4, the emitter of Q1 is connected to the negative electrode of the resistor R3;

[0108] The collector of the PNP transistor Q3 provides the bias current IB3 for the buck modulation circuit;

[0109] The collector of the PNP transistor Q4 is connected to the gate and drain of the NMOS transistor MN1 and the gates of the NMOS transistors MN2 and MN3;

[0110] The drain of the NMOS transistor MN4 is connected to the gate and drain of the PMOS transistor MP2, and the gates of the PMOS transistors MP3 and MP4;

[0111] The drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN6, the base of the transistor Q5, and the positive electrode of the capacitor C1;

[0112] The drain of the PMOS transistor MP4 is connected to the emitter of the transistor Q5, and the positive electrodes of the resistors R5 and R6, and a reference voltage VREF is generated at this point;

[0113] The negative electrode of the resistor R5 is connected to the base and collector of the transistor Q6, and the inverting input terminal of the amplifier AMP1;

[0114] The negative electrode of the resistor R6 is connected to the positive electrode of the resistor R7 and the non-inverting input terminal of the amplifier AMP1;

[0115] The negative electrode of the resistor R7 is connected to the base and collector of the transistor Q7;

[0116] The emitter of the NPN transistor Q6 is connected to the emitter of the transistor Q7 and the positive electrode of the resistor R8;

[0117] The output terminal of the amplifier AMP1 is connected to the gate of the NMOS transistor MN6 and the negative electrode of the resistor R9;

[0118] The negative electrode of the capacitor C1 is connected to the positive electrode of the resistor R9.

[0119] As Figure 5 shown, the buck modulation circuit includes: NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12; PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6; resistors R1, R2, R3.

[0120] The positive electrode of the resistor R1 is connected to the output voltage VP of the port protection circuit; the sources of the PMOS transistors MP1, MP2, MP3, and MP6 are connected to the output voltage VP of the port protection circuit;

[0121] The sources of the NMOS transistors MN1, MN2, MN3, MN4, MN8 are grounded; the negative electrode of the resistor R3 is grounded;

[0122] The gate and drain of the NMOS transistor MN1 are connected to the bias current IB3 of the reference circuit and are connected to the gates of the NMOS transistors MN2, MN3, MN4;

[0123] The gate and drain of the NMOS transistor MN5 are connected to the bias current IB2 of the self-starting bias circuit and are connected to the gates of the NMOS transistors MN6, MN7, MN8;

[0124] The negative electrode of the resistor R1 is connected to the drain of the NMOS transistor MN6 and the gate of the PMOS transistor MP1;

[0125] The drain of the PMOS transistor MP1 is connected to the drains of the NMOS transistors MN7, MN12, the drain of the PMOS transistor MP3, and the gate of the PMOS transistor MP6;

[0126] The drain of the NMOS transistor MN2 is connected to the sources of the NMOS transistors MN7, MN9, MN10, and the drain of the NMOS transistor MN8;

[0127] The gate of the NMOS transistor MN9 is connected to the output voltage VREF of the reference circuit, and the drain of MN9 is connected to the drain of the PMOS transistor MP5, the source of the NMOS transistor MN12, and the drain of MN4;

[0128] The gate of the NMOS transistor MN10 is connected to the negative pole of the resistor R2 and the positive pole of the resistor R3, and the drain of MN10 is connected to the drain of the PMOS transistor MP4, the source of the NMOS transistor MN11, and the drain of MN3;

[0129] The gate and drain of the PMOS transistor MP2 are connected to the drain of the NMOS transistor MN11;

[0130] The gate of the NMOS transistor MN11 is connected to the gate of the NMOS transistor MN12, the gate and source of the PMOS transistor MP4, and the gate and source of the PMOS transistor MP5, and is connected to the bias voltage VB provided by the self-starting bias circuit;

[0131] The drain of the PMOS transistor MP6 is connected to the positive pole of the resistor R2 and serves as the output terminal of the buck modulation circuit, and the voltage is VOUT;

[0132] The negative pole of the resistor R3 is connected to GND.

[0133] The working principle of the present invention is:

[0134] Figure 2 In, the devices MP1 and MP2 are selected as high-voltage P-type LDMOS, and their source-drain breakdown voltage is as high as dozens of volts. MN1-MN4 are isolation-type CMOS, and the isolation ring breakdown voltage is as high as dozens of volts. When the circuit is working normally, the internal current mirror is turned on. At this time, for the MP1 and MP2 devices, V GS > V TH , this channel is turned on, and the voltage is transmitted from the port to the internal circuit; when the port is negative, at this time, the drain voltage of the MP1 device is lower than the gate-source voltage, and the device is turned off. Since the source-drain and gate-drain breakdown voltages of the MP1 device are both dozens of volts, the negative pressure can be blocked to ensure that the internal circuit is not damaged.

[0135] Figure 3 In, the devices MP1, MN1, and Q1 are connected in series. When the circuit is powered on normally, this branch is turned on, the transistor Q2 is turned on, and the NMOS transistor MN2 is turned on, pulling down the gate voltages of the PMOS transistors MP3-MP6, so that the PMOS transistors MP3-MP6 are turned on and copy the current of the MP3 branch.

[0136] The current of the MP3 branch is composed of two groups of currents converging.

[0137] Transistors Q1 and Q2 are transistors of the same size, and the number of Q1 is much larger than that of Q2. After the circuit starts, the emitter current of Q2 can be ignored. Transistors Q3, Q4, and Q5 are transistors of the same size, and the currents in the two branches are equal, both being I1. The bipolar transistor operates at different current densities, and the difference in its base-emitter voltage is proportional to the absolute temperature. Then there is:

[0138] ΔV BE =V BE4 -V BE3 =V T ·ln4=R2·I1

[0139] I1=(V T ·lna) / R2

[0140] Q5 copies the current of Q4, and then the positive temperature coefficient current I1 is obtained.

[0141] The voltage drop across resistor R3 is V BE5 , then there is:

[0142] I2=V BE5 / R3

[0143] The current in the branch where R3 is located is the negative temperature coefficient current I2.

[0144] The total current in the branch where MP3 is located is I3:

[0145] I3=V BE5 / R3+(V T ·lna) / R2

[0146] By adjusting the resistance values of resistors R2 and R3, as well as the value of a, a zero temperature coefficient current can be obtained.

[0147] The currents IB1 and IB2 generated by current mirror copying are both bias currents independent of the ambient temperature, and a bias voltage VB is generated at the gate of MN4:

[0148] VB=V GS4 +I3·R4

[0149] Figure 4 is a bandgap reference circuit with a startup circuit.

[0150] Figure 4On the left is the startup circuit part. When the circuit is powered on normally, the voltage at the input terminal of the inverter INV1 increases, and the voltage at the output terminal is at a low level. The PMOS transistor MP1 conducts, the gate voltage of the NMOS transistor MN5 is pulled high, MN5 conducts, the transistor Q2 is turned on, this branch conducts, and the circuit enters the working state; the NMOS transistor MN2 conducts, the voltage at the input terminal of the inverter INV1 decreases, and the PMOS transistor MP1 is cut off. The transistor Q3 copies the current of the transistor Q2 to obtain the bias current IB3; the NMOS transistor MN4 copies the current of the MN5 branch.

[0151] The transistors Q1 to Q4 are transistors of the same size but different numbers. The currents in the two branches of Q1 and Q4 are equal, both being I4. When the bipolar transistors operate at different current densities, the difference in the base-emitter voltage is proportional to the absolute temperature. Then there is:

[0152] ΔV BE =V BE4 -V BE1 =V T ·ln4=R3·I4

[0153] I4=(V T ·lnb) / R3

[0154] Q3 copies the current of Q4, and then the current IB3 with a positive temperature coefficient is obtained.

[0155] The voltage drop across the resistor R4 is V BE2 , then there is:

[0156] I5=V BE2 / R4

[0157] The current in the branch where R4 is located is the current I5 with a negative temperature coefficient.

[0158] The total current in the branch where MN5 is located is I6:

[0159] I6=V BE2 / R4+(V T ·lnb) / R3

[0160] By adjusting the resistance values of the resistors R3 and R4, as well as the value of b, a current with zero temperature coefficient can be obtained.

[0161] Figure 4 On the right is the bandgap reference circuit part. The basic principle of the bandgap reference voltage circuit is to superimpose a voltage with a negative temperature coefficient and a voltage with a positive temperature coefficient with appropriate weights to cancel the influence of temperature change on the output voltage, so as to obtain a constant voltage with zero temperature coefficient and almost independent of the power supply voltage. Generally, the temperature characteristics of bipolar transistors are used to generate positive / negative temperature coefficients.

[0162] Utilizing the "virtual short" characteristic of the operational amplifier, we have VX = VY. When R5 = R6, the collector currents flowing through the two transistors are the same, both being I. Then we have:

[0163] ΔVBE = VX - VZ = VY - VZ = I·R7

[0164] Since ΔVBE = V T lnc, the expression for VREF can be obtained:

[0165] VREF = 2I·R8 + V BE6 + I·R5 = V BE6 + V T lnc·(2·R8 + R5) / R7

[0166] It can be seen from the above formula that V BE6 has a negative temperature coefficient, and V T lnc·(2·R8 + R5) / R7 has a positive temperature coefficient. By reasonably setting the resistance values of R5~R8 and the value of c, a reference voltage VREF that does not change with temperature can be obtained.

[0167] Among them, R9 and C1 provide compensation for the circuit. MN6 and Q5 together with the bandgap reference main circuit form a feedback loop to improve the stability of the circuit.

[0168] Its feedback mechanism is as follows: when the reference voltage VREF increases, the output voltage of the amplifier increases, the driving ability of the NMOS transistor MN6 is enhanced, the base voltage of the transistor Q5 decreases, and the emitter voltage of Q5, which is also the reference voltage VREF, is pulled down; vice versa.

[0169] Figure 5 is a high-voltage pre-modulation circuit, which mainly consists of an auxiliary circuit, an error amplifier, a power transistor, and a feedback resistor network to form a negative feedback closed-loop system. When the input voltage or load current changes, the negative feedback regulation of its control loop suppresses the change of the output voltage and provides a stable working voltage for other modules.

[0170] Its working principle is as follows: the reference circuit generates a reference voltage VREF, which is input to the inverting input terminal of the error amplifier. The feedback resistor samples the output voltage, and the sampled voltage is input to the non-inverting input terminal of the error amplifier and compared with the reference voltage. The error amplifier amplifies the comparison result, and the amplified signal serves as the gate voltage of the power transistor, thereby controlling the output of the power transistor.

[0171] Its negative feedback process is as follows: when the output voltage VOUT decreases due to load changes or other reasons, the feedback voltage collected by the two series voltage-dividing resistors also decreases, resulting in a decrease in the output voltage of the error amplifier, causing the gate voltage of the power transistor to decrease, while the source voltage of the power transistor remains unchanged. As a result, |VGS| of the power transistor increases, then ISD of the power transistor increases, VSD decreases, and the output voltage VOUT rises, completing one feedback control; when the output voltage VOUT increases, the difference between the sampled value of the voltage-dividing resistor and the reference voltage VREF becomes smaller, the output voltage of the amplifier increases, the gate voltage of the power transistor increases, the drain current decreases, and the output voltage VOUT increases, causing the output voltage VOUT to return to the normal potential.

[0172] The highlight of the design of the present invention lies in adopting port protection design to enable the high-voltage pre-modulation circuit to have a negative voltage protection function, improving the reliability of the circuit; at the same time, adopting the loop design of the self-starting bias circuit, reference circuit and buck modulation circuit to achieve the buck modulation function under single power supply, reducing the system complexity. Figure 6 It is the simulation result of the high-voltage pre-modulation circuit.

Claims

1. A high-voltage pre-modulation circuit, characterized in that, Including: A port protection circuit, a self-starting bias circuit, a reference circuit, and a buck modulation circuit; The port protection circuit adopts a back-to-back P-type LDMOS design for the negative voltage protection port involved in the power input, which can block the negative voltage path and prevent the device from being damaged by the intrusion into the internal circuit; The self-starting bias circuit conducts when the power is turned on, provides a bias current IB1 for the port protection circuit, provides a bias current IB2 and a bias voltage VB1 for the buck modulation circuit, enables the buck modulation circuit to quickly get out of the degeneracy point, and performs a steady-state output; The reference circuit superimposes the positive temperature coefficient voltage generated by the transistor operating at different current densities and the negative temperature coefficient voltage between the base and emitter of the transistor to obtain a bandgap reference voltage, and provides a reference level for the buck modulation circuit; And introduces a negative feedback loop to maintain the stability of the reference voltage; The buck modulation circuit consists of an error amplifier, a power transistor, and a feedback resistor network to form a negative feedback closed-loop system. When the input voltage or the load current changes, the change of the output voltage is suppressed through the feedback regulation of the negative feedback closed-loop system, and a stable operating voltage is provided for other modules.

2. The high-voltage pre-modulation circuit according to claim 1, wherein The port protection circuit includes: PMOS transistors MP1, MP2; NMOS transistors MN1, MN2, MN3, MN4; and a resistor R1; The drain of the PMOS transistor MP1 serves as the input end of the port protection circuit and is connected to the external power supply voltage VIN; the gate of MP1 is connected to the gates of the PMOS transistor MP2, the gates and sources of the NMOS transistors MN1, the source of the NMOS transistor MN4, and the positive pole of the resistor R1, and the source of MP1 is connected to the sources of the PMOS transistor MP2, the drain of the NMOS transistor MN1, and the gates and drains of the NMOS transistor MN2; The drain of the PMOS transistor MP2 serves as the output end of the port protection circuit and provides a power supply voltage VP for the buck modulation circuit; The source of the NMOS transistor MN2 is connected to the gates and drains of the NMOS transistor MN3; The source of the NMOS transistor MN3 is connected to the gates and drains of the NMOS transistor MN4; The negative pole of the resistor R1 is connected to the bias current IB1 provided by the self-starting bias circuit.

3. The high-voltage pre-modulation circuit according to claim 2, characterized in that, The self-starting bias circuit includes: NPN transistors Q1, Q2, Q3, Q4, Q5; NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8; PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6; and resistors R1, R2, R3, R4; The positive pole of the resistor R1 is connected to the power supply voltage VDD after passing through a diode; the sources of the PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6 are connected to the power supply voltage VDD after passing through a diode; The emitters of the NPN transistors Q1, Q4, Q5 are grounded; the negative poles of the resistors R2, R3, R4 are grounded; the sources of the NMOS transistors MN6, MN8 are grounded; The negative pole of the resistor R1 is connected to the gates and drains of the NMOS transistor MN1, and the gates of the NMOS transistors MN2 and MN3; The source of the NMOS transistor MN1 is connected to the base and collector of the transistor Q1 and the base of the transistor Q2; The gate of the PMOS transistor MP1 is connected to the gates and drains of the PMOS transistors MP2, and the drain of the NMOS transistor MN3. The drain of MP1 is connected to the drain of the NMOS transistor MN2 and the gates of the PMOS transistors MP3, MP4, MP5, and MP6; The source of the NMOS transistor MN2 is connected to the collectors of the transistors Q2 and Q3; The emitter of the NPN transistor Q2 is connected to the emitters of the transistors Q3 and the positive pole of the resistor R2; The source of the NMOS transistor MN3 is connected to the collector of the transistor Q4; The base of the NPN transistor Q4 is connected to the base of the transistor Q3, the bases and collector of the transistor Q5, the drain of the PMOS transistor MP3, and the positive pole of the resistor R3; the collector of Q4 is connected to the source of the NMOS transistor MN3; The drain of the PMOS transistor MP4 is connected to the gate and drain of the NMOS transistor MN4, and a voltage VB is generated at this point to provide a bias voltage for the buck modulation circuit; The source of the NMOS transistor MN4 is connected to the positive pole of the resistor R4; The drain of the PMOS transistor MP5 is connected to the gate and drain of the NMOS transistor MN5 and the gates of the NMOS transistors MN6, MN7, and MN8; The drain of the PMOS transistor MP6 provides a bias current IB2 for the buck modulation circuit; The source of the NMOS transistor MN5 is connected to the drain of the NMOS transistor MN6; The source of the NMOS transistor MN7 is connected to the drain of the NMOS transistor MN8; the drain of MN7 provides a bias current IB1 for the port protection circuit.

4. A high-voltage pre-modulation circuit according to claim 3, characterized in that The reference circuit includes: PMOS transistors MP1, MP2, MP3, MP4; NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6; PNP transistors Q1, Q2, Q3, Q4, Q5; NPN transistors Q6, Q7; resistors R1, R2, R3, R4, R5, R6, R7, R8, R9; capacitor C1; inverter INV1; The positive poles of the resistors R1, R2, R3, and R4 are connected to the stable voltage VOUT output by the buck modulation circuit; the emitters of the PNP transistors Q2, Q3, and Q4 are connected to the stable voltage VOUT output by the buck modulation circuit; the sources of the PMOS transistors MP2, MP3, and MP4 are connected to the stable voltage VOUT output by the buck modulation circuit; The sources of the NMOS transistors MN1, MN2, MN3, MN4, MN5, and MN6 are grounded; the negative pole of the resistor R8 is grounded; the collector of the transistor Q5 is grounded; The negative pole of the resistor R1 is connected to the input terminal of the inverter INV1 and the drain of the NMOS transistor MN2; The output terminal of the inverter IN1 is connected to the gate of the PMOS transistor MP1; The source of the PMOS transistor MP1 is connected to the negative pole of the resistor R2, and the drain of MP1 is connected to the collector of the transistor Q1, the drain of the NMOS transistor MN3, and the gates of the NMOS transistors MN4 and MN5; The base of the PNP transistor Q1 is connected to the negative electrode of the resistor R4, the drain of the MNOS transistor MN5, the base and collector of the transistor Q2, and the bases of Q3 and Q4. The emitter of Q1 is connected to the negative electrode of the resistor R3; The collector of the PNP transistor Q3 provides the bias current IB3 for the buck modulation circuit; The collector of the PNP transistor Q4 is connected to the gate and drain of the NMOS transistor MN1, and the gates of the NMOS transistors MN2 and MN3; The drain of the NMOS transistor MN4 is connected to the gate and drain of the PMOS transistor MP2, and the gates of the PMOS transistors MP3 and MP4; The drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN6, the base of the transistor Q5, and the positive electrode of the capacitor C1; The drain of the PMOS transistor MP4 is connected to the emitter of the transistor Q5, and the positive electrodes of the resistors R5 and R6, and a reference voltage VREF is generated at this point; The negative electrode of the resistor R5 is connected to the base and collector of the transistor Q6, and the inverting input terminal of the amplifier AMP1; The negative electrode of the resistor R6 is connected to the positive electrode of the resistor R7, and the non-inverting input terminal of the amplifier AMP1; The negative electrode of the resistor R7 is connected to the base and collector of the transistor Q7; The emitter of the NPN transistor Q6 is connected to the emitter of the transistor Q7 and the positive electrode of the resistor R8; The output terminal of the amplifier AMP1 is connected to the gate of the NMOS transistor MN6 and the negative electrode of the resistor R9; The negative electrode of the capacitor C1 is connected to the positive electrode of the resistor R9.

5. A high-voltage pre-modulation circuit according to claim 4, characterized in that, The buck modulation circuit includes: NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12; PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6; resistors R1, R2, R3; The positive electrode of the resistor R1 is connected to the output voltage VP of the port protection circuit; the sources of the PMOS transistors MP1, MP2, MP3, and MP6 are connected to the output voltage VP of the port protection circuit; The sources of the NMOS transistors MN1, MN2, MN3, MN4, and MN8 are grounded; the negative electrode of the resistor R3 is grounded; The gate and drain of the NMOS transistor MN1 are connected to the bias current IB3 of the reference circuit and are connected to the gates of the NMOS transistors MN2, MN3, and MN4; The gate and drain of the NMOS transistor MN5 are connected to the bias current IB2 of the self-starting bias circuit and are connected to the gates of the NMOS transistors MN6, MN7, and MN8; The negative electrode of the resistor R1 is connected to the drain of the NMOS transistor MN6 and the gate of the PMOS transistor MP1; The drain of the PMOS transistor MP1 is connected to the drains of the NMOS transistors MN7 and MN12, the drain of the PMOS transistor MP3, and the gate of the MP6; The drain of the NMOS transistor MN2 is connected to the sources of the NMOS transistors MN7, MN9, and MN10, and the drain of MN8; The gate of the NMOS transistor MN9 is connected to the output voltage VREF of the reference circuit, and the drain of MN9 is connected to the drain of the PMOS transistor MP5, the source of the NMOS transistor MN12, and the drain of MN4; The gate of the NMOS transistor MN10 is connected to the negative pole of the resistor R2 and the positive pole of the resistor R3, and the drain of MN10 is connected to the drain of the PMOS transistor MP4, the source of the NMOS transistor MN11, and the drain of MN3; The gate and drain of the PMOS transistor MP2 are connected to the drain of the NMOS transistor MN11; The gate of the NMOS transistor MN11 is connected to the gate of the NMOS transistor MN12, the gate and source of the PMOS transistor MP4, and the gate and source of the PMOS transistor MP5, and is connected to the bias voltage VB provided by the self-starting bias circuit; The drain of the PMOS transistor MP6 is connected to the positive pole of the resistor R2 and serves as the output terminal of the buck modulation circuit, and the voltage is VOUT; The negative pole of the resistor R3 is connected to GND.

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