Relaxation oscillator and motor

Abstract

The invention discloses a relaxation oscillator and a motor, and relates to the field of electronic power, the relaxation oscillator comprises a reference voltage module, a high-side comparator, a low-side comparator, a control module and a filter, the control module is used for setting a high-side reset end to a high level under the condition that the high-side comparator outputs a high level, and setting a low-side reset end to a low level under the condition that the low-side comparator outputs a low level; the clamping circuit is used for clamping the output of the high-side comparator into a low level so as to form a preset narrow pulse at the high-side output end, and the preset narrow pulse is sequentially composed of the low level, the high level and the low level; the low-side comparator is also used for setting the low-side reset end as a low level under the condition that the low-side comparator outputs a high level, so that the output of the low-side comparator is clamped as the low level, and a preset narrow pulse is formed at the low-side output end; and the control module is also used for jumping the level of the clock signal output by the first output end under the condition that the high-side comparator outputs the high level or the low-side comparator outputs the high level. The problem that the precision of the clock signal output by the relaxation oscillator is poor is solved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic power technology, and particularly to a relaxation oscillator and a motor. Background Art

[0002] In the application of motor drive chips, a clock of 1 MHz (Megahertz) to 24 MHz is generally required. In a traditional ping-pong symmetric relaxation oscillator, a triangular wave signal is directly generated by switching to control the charging and discharging of a capacitor to generate a clock signal. However, there will be switch charge injection during the switch switching, resulting in voltage offset, and further reducing the clock accuracy. Therefore, there is currently a technical problem of poor accuracy of the clock signal output by the relaxation oscillator.

[0003] The above content is only used to assist in understanding the technical solution of the embodiments of the present application, and does not represent an admission that the above content is the prior art. Summary of the Invention

[0004] The main purpose of the embodiments of the present application is to provide a relaxation oscillator and a motor, aiming to solve the technical problem of poor accuracy of the clock signal output by the relaxation oscillator.

[0005] To achieve the above object, the embodiments of the present application provide a relaxation oscillator, which includes: a reference voltage module, a high-side comparator, a low-side comparator, a control module, and a filter. The reference voltage module is connected to the high-side reference terminal of the high-side comparator and the low-side reference terminal of the low-side comparator. The high-side comparison terminal of the high-side comparator and the low-side comparison terminal of the low-side comparator are connected to the voltage output terminal of the filter; The high-side output terminal of the high-side comparator and the low-side output terminal of the low-side comparator are both connected to the input terminal of the control module. The high-side reset terminal of the high-side comparator and the low-side reset terminal of the low-side comparator are both connected to the first output terminal of the control module; The control module is configured to, when the high-side comparator outputs a high level, set the high-side reset terminal to a high level to clamp the output of the high-side comparator to a low level to form a preset narrow pulse at the high-side output terminal. The preset narrow pulse consists of a low level, a high level, and a low level in sequence; The control module is further configured to, when the low-side comparator outputs a high level, set the low-side reset terminal to a low level to clamp the output of the low-side comparator to a low level to form a preset narrow pulse at the low-side output terminal; The control module is further configured to, when the high-side comparator outputs a high level or the low-side comparator outputs a high level, toggle the level of the clock signal output by the first output terminal.

[0006] In one embodiment, the high-side comparator includes a first current source unit, a high-side comparison unit, and a high-side secondary clamping unit connected in sequence; The high-side comparison unit is connected to the high-side reference terminal, the high-side comparison terminal, and the high-side output terminal. The high-side secondary clamping unit is connected to the high-side reset terminal and the high-side output terminal. The first current source unit is connected to the high-side enable terminal of the high-side comparator, and the high-side enable terminal is connected to the second output terminal of the control module; The high-side comparator is configured to output a high level when the high-side enable terminal is at a high level and the voltage of the high-side comparison terminal is greater than the voltage of the high-side reference terminal; The high-side secondary clamping unit is configured to clamp the high-side output terminal to a low level when the high-side reset terminal is set to a high level, so as to form a preset narrow pulse at the high-side output terminal; The first current source unit is configured to output a first preset maximum current when the high-side enable terminal is at a high level, and is further configured to output a first preset low-power consumption current when the high-side enable terminal is at a low level.

[0007] In one embodiment, the first current source includes a first switching transistor and a second switching transistor; the high-side comparison unit includes a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, and a ninth switching transistor; The first end of the first switching transistor is connected to the high-side enable terminal. The first end of the second switching transistor is connected to a first preset bias voltage. The second end of the second switching transistor is connected to a preset low voltage terminal, and the third end of the second switching transistor is connected to the second end of the first switching transistor; The third end of the first switching transistor is connected to the second ends of the third switching transistor and the fourth switching transistor. The first end of the third switching transistor is connected to the high-side reference terminal, and the first end of the fourth switching transistor is connected to the high-side comparison terminal; The third end of the fourth switching transistor is connected to the third end of the fifth switching transistor. The second end of the fifth switching transistor is connected to the second end of the sixth switching transistor. The first end of the sixth switching transistor is connected to the first end of the fifth switching transistor, and the third end of the sixth switching transistor is connected to the third end of the third switching transistor; The second end of the fourth switching transistor is connected to the third end of the ninth switching transistor. The first ends of the ninth switching transistor and the seventh switching transistor are both connected to a first preset bias voltage. The second end of the seventh switching transistor is connected to the second end of the ninth switching transistor, and the third end of the seventh switching transistor is connected to the high-side output terminal and the high-side secondary clamping unit; The high-side output terminal is further connected to the third end of the eighth switching transistor, and the first and second ends of the eighth switching transistor are both connected to the high-side secondary clamping unit.

[0008] In one embodiment, the high-side secondary clamping unit includes a first clamping switch transistor, a second clamping switch transistor, a first inverter, and a second inverter; The first end of the first clamping switch transistor is connected to the output end of the first inverter. The output end of the first inverter is also connected to the input end of the second inverter. The input end of the first inverter is connected to the high-side reset end. The second end of the first clamping switch transistor is connected to the second end of the eighth switch transistor. The third end of the first clamping switch transistor is connected to the first end of the eighth switch transistor; The output end of the second inverter is connected to the first end of the second clamping switch transistor. The second end of the second clamping switch transistor is connected to a preset low voltage end. The third end of the second clamping switch transistor is connected to the high-side output end.

[0009] In one embodiment, the low-side comparator includes a second current source unit, a low-side comparison unit, and a low-side secondary clamping unit connected in sequence; The low-side comparison unit is connected to the low-side reference end, the low-side comparison end, and the low-side output end. The low-side secondary clamping unit is connected to the low-side reset end and the low-side output end. The second current source unit is connected to the low-side enable end of the low-side comparator. The low-side enable end is connected to the second output end of the control module; The low-side comparator is configured to output a high level when the low-side enable end is at a low level and the voltage of the low-side comparison end is greater than the voltage of the low-side reference end; The low-side secondary clamping unit is configured to clamp the low-side output end to a low level when the low-side reset end is set to a low level, so as to form a preset narrow pulse at the low-side output end; The second current source unit is configured to output a second preset maximum current when the low-side enable end is at a low level, and is also configured to output a second preset low-power consumption current when the low-side enable end is at a high level.

[0010] In one embodiment, the second current source unit includes a tenth switch transistor and an eleventh switch transistor; The low-side comparison unit includes: a twelfth switch transistor, a thirteenth switch transistor, a fourteenth switch transistor, a fifteenth switch transistor, a sixteenth switch transistor, a seventeenth switch transistor, an eighteenth switch transistor, and a third inverter; The first end of the tenth switch transistor is connected to the low-side enable end. The first end of the eleventh switch transistor is connected to a second preset bias voltage. The second end of the eleventh switch transistor is connected to a preset power supply end. The third end of the eleventh switch transistor is connected to the second end of the tenth switch transistor; The third terminal of the tenth switching transistor is connected to the second terminal of the twelfth switching transistor and the second terminal of the thirteenth switching transistor. The first terminal of the twelfth switching transistor is connected to the low-side reference terminal, and the first terminal of the thirteenth switching transistor is connected to the low-side comparison terminal; The third terminal of the thirteenth switching transistor is connected to the third terminal of the fourteenth switching transistor. The second terminal of the fourteenth switching transistor is connected to the second terminal of the fifteenth switching transistor. The first terminal of the fifteenth switching transistor is connected to the first terminal of the fourteenth switching transistor. The third terminal of the fifteenth switching transistor is connected to the third terminal of the twelfth switching transistor; The second terminal of the twelfth switching transistor is connected to the third terminal of the eighteenth switching transistor. The first terminals of the eighteenth switching transistor and the seventeenth switching transistor are connected to a second preset bias voltage. The second and third terminals of the seventeenth switching transistor are connected to a low-side secondary clamping unit; The third terminal of the seventeenth switching transistor is connected to the input terminal of the third inverter and the third terminal of the sixteenth switching transistor. The first and second terminals of the sixteenth switching transistor are connected to the low-side secondary clamping unit. The output terminal of the third inverter is connected to the low-side output terminal.

[0011] In one embodiment, the low-side secondary clamping unit includes: a third clamping switching transistor, a fourth clamping switching transistor, a fourth inverter, and a fifth inverter; The low-side reset terminal is connected to the input terminal of the fourth inverter. The output terminal of the fourth inverter is connected to the input terminal of the fifth inverter and the first terminal of the third clamping switching transistor. The second terminal of the third clamping switching transistor is connected to the second terminal of the sixteenth switching transistor. The third terminal of the third clamping switching transistor is connected to the first terminal of the sixteenth switching transistor; The output terminal of the fifth inverter is connected to the first terminal of the fourth clamping switching transistor. The second terminal of the fourth clamping switching transistor is connected to a preset power supply terminal. The third terminal of the fourth clamping switching transistor is connected to the input terminal of the third inverter.

[0012] In one embodiment, the reference voltage module further includes a preset inverting unit and a preset voltage dividing unit. The preset inverting unit is connected to the preset voltage dividing unit. The preset voltage dividing unit is connected to the high-side reference terminal and the low-side reference terminal; The preset inverting unit includes a first preset switching transistor and a second preset switching transistor. The first terminals of the first preset switching transistor and the second preset switching transistor are both connected to a preset input control terminal. The second terminal of the first preset switching transistor is connected to a preset power supply terminal. The third terminal of the first preset switching transistor, the second and third terminals of the second preset switching transistor are all connected to the preset voltage dividing unit.

[0013] In one embodiment, the preset voltage dividing unit includes a first voltage dividing switching transistor, a second voltage dividing switching transistor, and a third voltage dividing switching transistor; The first end of the first voltage-dividing switch tube is connected to the high-side reference end, the second end of the first voltage-dividing switch tube is connected to the preset power supply end, and the third end of the first voltage-dividing switch tube is connected to the second end of the second voltage-dividing switch tube; The first end of the second voltage-dividing switch tube is connected to the third end of the first preset switch tube and the third end of the second preset switch tube, and the third end of the second voltage-dividing switch tube is connected to the second end of the third voltage-dividing switch tube and the low-side reference end; Both the first end and the third end of the third voltage-dividing switch tube are connected to the preset low voltage end.

[0014] In addition, to achieve the above object, an embodiment of the present application further provides a motor, including the relaxation oscillator as described above.

[0015] One or more technical solutions proposed in the embodiments of the present application have at least the following technical effects: The embodiments of the present application provide a reference voltage module, a high-side comparator, a low-side comparator, a control module, and a filter. The reference voltage module is connected to the high-side reference end of the high-side comparator and the low-side reference end of the low-side comparator. The high-side comparison end of the high-side comparator and the low-side comparison end of the low-side comparator are connected to the voltage output end of the filter; the high-side output end of the high-side comparator and the low-side output end of the low-side comparator are both connected to the input end of the control module, and the high-side reset end of the high-side comparator and the low-side reset end of the low-side comparator are both connected to the first output end of the control module. Thereby, the control module can jump the level of the clock signal output by the first output end when the high-side comparator outputs a high level or the low-side comparator outputs a high level, and further realize the generation of the clock signal through the high-side comparator and the low-side comparator, without generating an oscillation through a switch switch to generate a clock signal, thereby avoiding the switch charge injection in the switch switching process and also avoiding the influence of voltage offset on the clock signal, and further improving the accuracy of the clock signal.

[0016] Moreover, since the present application realizes the output of the clock signal through the levels output by the high-side comparator and the low-side comparator, and there will be a certain delay in the levels output by the high-side comparator and the low-side comparator respectively, there may be a situation where the high-side comparator and the low-side comparator output high levels simultaneously, which may in turn lead to the confusion of the clock signal and reduce the accuracy of the clock signal. Therefore, in the present application, when the high-side comparator outputs a high level, the high-side reset terminal is set to a high level so as to clamp the output of the high-side comparator to a low level, thereby forming a preset narrow pulse composed of a low level, a high level, and a low level in sequence. Also, when the low-side comparator outputs a high level, the low-side reset terminal is set to a low level so as to clamp the output of the low-side comparator to a low level, thereby also forming a preset narrow pulse, and further avoiding the situation where the low-side comparator and the high-side comparator output high levels simultaneously, so as to improve the accuracy of the clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments in accordance with the embodiments of the present application, and are used together with the specification to explain the principles of the embodiments of the present application.

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other accompanying drawings can also be obtained based on these accompanying drawings without creative efforts.

[0019] Figure 1 It is a schematic diagram of module connections of a relaxation oscillator according to an embodiment of the present application; Figure 2 It is a schematic diagram of module connections of a high-side comparator in the relaxation oscillator according to an embodiment of the present application; Figure 3 It is a schematic diagram of circuit connections of a high-side comparator in the relaxation oscillator according to an embodiment of the present application; Figure 4 It is a schematic diagram of module connections of a low-side comparator in the relaxation oscillator according to an embodiment of the present application; Figure 5 It is a schematic diagram of circuit connections of a low-side comparator in the relaxation oscillator according to an embodiment of the present application; Figure 6 It is a schematic diagram of module connections of another embodiment of the relaxation oscillator according to an embodiment of the present application; Figure 7 It is a schematic diagram of circuit connections of a specific circuit structure including a control module and a filter in the relaxation oscillator according to an embodiment of the present application; Figure 8Schematic diagram of the ideal VRC (Voltage of Resistance-Capacitance Filter, output voltage of the RC filter) waveform output by the filter in the relaxation oscillator of the embodiment of the present application; Figure 9 Schematic diagram of the actual VRC waveform output by the filter in the relaxation oscillator of the embodiment of the present application; Figure 10 Schematic diagram of the waveforms of the actual VRC waveform, clock signal, output of the high-side comparator, and output of the low-side comparator when there is no secondary clamping in the comparator and when there is secondary clamping in the comparator in the relaxation oscillator of the embodiment of the present application; Figure 11 Schematic diagram of the circuit connection of the specific circuit structure including the reference voltage module in an embodiment of the relaxation oscillator of the embodiment of the present application; Figure 12 Schematic diagram of the waveform of the soft start of the relaxation oscillator in the embodiment of the present application; Figure 13 Schematic diagram of the circuit connection of the specific circuit structure including the reference voltage module in another embodiment of the relaxation oscillator in the embodiment of the present application.

[0020] Explanation of the reference numerals in the figures: 100. Reference voltage module; 200. High-side comparator; 300. Low-side comparator; 400. Control module; 500. Filter; PI1 High-side comparison terminal; NI1 High-side reference terminal; PI2, Low-side reference terminal; NI2, Low-side reference terminal; PD, High-side reset terminal; PU, Low-side reset terminal; GT, High-side output terminal; DT, Low-side output terminal; R, First input terminal of the control module; S, Second input terminal of the control module; QBD, First output terminal of the control module; VRC, Voltage output by the filter; Q, Second output terminal of the control module; SW, High-side enable terminal; SWB, Low-side enable terminal; 210. First current source unit; 220. High-side comparison unit; 230. High-side secondary clamping unit; VBN, First preset bias voltage; M1 to M18, First switching transistor to Eighteenth switching transistor; MQ1 to MQ4, First clamping switching transistor to Fourth clamping switching transistor; F1 to F8, First inverter to Eighth inverter; 310. Second current source unit; 320. Low-side comparison unit; 330. Low-side secondary clamping unit; VBP, Second preset bias voltage; 600. Buffer; H1, First NOR gate; H2, Second NOR gate; YM, AND gate; PBD, Second input terminal of the AND gate; R1, First resistor; 510. Filter switching transistor; 410. RS latch; VSS, Preset low voltage terminal; VDD, Preset power supply terminal; My1 to My2, First preset switching transistor to Second preset switching transistor; Mf1 to Mf3, First voltage dividing switching transistor to Third voltage dividing switching transistor; Md1 to Md2, First preset grounding switching transistor to Second preset grounding switching transistor.

[0021] The implementation, functional features, and advantages of the embodiments of the present application will be further described in combination with the embodiments and with reference to the accompanying drawings. Detailed implementation manners

[0022] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the embodiments of the present application and are not used to limit the embodiments of the present application.

[0023] To better understand the technical solutions of the embodiments of the present application, the following will be described in detail in combination with the accompanying drawings of the specification and specific implementation manners.

[0024] In the application of motor drive chips, a clock of 1 MHz to 24 MHz is generally required. For drive chips, the accuracy of the clock may not be that critical, but it is desirable that the power consumption of the clock be as low as possible. The traditional ping-pong symmetric relaxation oscillator uses a structure of resistors, capacitors or a combination of reference current and capacitors to generate a clock signal, but it has the disadvantages of large area and high power consumption; at the same time, the relaxation oscillator directly generates a triangular wave by controlling the charging and discharging process of the capacitor through a switch. However, due to the switch control, there is a problem of switch charge injection in the triangular wave, and the switch charge injection will introduce voltage offset. The voltage offset is sensitive to PVT (Process, Voltage, Temperature), which will further reduce the clock accuracy.

[0025] Therefore, the present application provides a relaxation oscillator. The clock signal generated by the relaxation oscillator in the present application is not affected by the switch charge introduced by the switch switching, which can improve the clock accuracy. In the present application, a comparator with a faster single-edge response is used, that is, a high-side comparator and a low-side comparator, which can save the power consumption of the relaxation oscillator. At the same time, a two-stage clamping control is added to both the high-side comparator and the low-side comparator, which realizes avoiding clock confusion while reducing the power consumption, so as to improve the robustness of the relaxation oscillator.

[0026] Based on this, an embodiment of the present application provides a relaxation oscillator. Refer to Figure 1 , Figure 1 which is a schematic diagram of the modules of the relaxation oscillator according to the embodiment of the present application. A reference voltage module 100, a high-side comparator 200, a low-side comparator 300, a control module 400 and a filter 500. The reference voltage module 100 is connected to the high-side reference terminal NI1 of the high-side comparator 200 and the low-side reference terminal PI2 of the low-side comparator 300. The high-side comparison terminal PI1 of the high-side comparator 200 and the low-side comparison terminal NI2 of the low-side comparator 300 are connected to the voltage output terminal of the filter 500; The high-side output terminal GT of the high-side comparator 200 and the low-side output terminal DT of the low-side comparator 300 are both connected to the input terminal of the control module 400. The high-side reset terminal PD of the high-side comparator 200 and the low-side reset terminal PU of the low-side comparator 300 are both connected to the first output terminal QBD of the control module 400; The control module 400 is configured to set the high-side reset terminal PD to a high level when the high-side comparator 200 outputs a high level, so as to clamp the output of the high-side comparator 200 to a low level, so as to form a preset narrow pulse at the high-side output terminal GT. The preset narrow pulse consists of a low level, a high level and a low level in sequence; The control module 400 is further configured to set the low-side reset terminal PU to a low level when the low-side comparator 300 outputs a high level, so as to clamp the output of the low-side comparator 300 to a low level, and form a preset narrow pulse at the low-side output terminal DT. The control module 400 is further configured to change the level of the clock signal output from the first output terminal when the high-side comparator 200 outputs a high level or the low-side comparator 300 outputs a high level.

[0027] It should be noted that the reference voltage module 100 is used to generate a reference voltage. The reference voltage can be input to the high-side reference terminal NI1 of the high-side comparator 200 and the low-side reference terminal PI2 of the low-side comparator 300. The voltage input by the reference voltage module 100 to the high-side reference terminal NI1 is different from the voltage input to the low-side reference terminal PI2. For example, the voltage of the high-side reference terminal NI1 is VDD or 2 / 3VDD, and the voltage of the low-side reference terminal PI2 is VSS or 1 / 3VDD, etc. VDD is a preset power supply terminal, and the preset power supply terminal can be the positive voltage of the power supply connected to the reference voltage module 100. VSS can be a preset low voltage terminal, and the preset low voltage terminal is the negative voltage of the power supply connected to the reference voltage module 100.

[0028] The filter 500 can be a resistor-capacitor filter 500. The filter 500 can generate a triangular wave. The voltage output terminal of the filter 500 can be connected to the high-side comparison terminal PI1 of the high-side comparator 200 and the low-side comparison terminal NI2 of the low-side comparator 300. Both the high-side comparison terminal PI1 and the high-side reference terminal NI1 are input terminals of the high-side comparator 200, and both the low-side comparison terminal NI2 and the low-side reference terminal PI2 are input terminals of the low-side comparator 300. The filter 500 is connected to the high-side comparison terminal PI1 and the low-side comparison terminal NI2, and the reference voltage module 100 is connected to the high-side reference terminal NI1 and the low-side reference terminal PI2, which facilitates the high-side comparator 200 and the low-side comparator 300 to output different levels based on their respective inputs, so as to generate a clock signal subsequently.

[0029] In this embodiment, the high-side reference terminal NI1 can be the negative input terminal of the high-side comparator 200, the high-side comparison terminal PI1 can be the positive input terminal of the high-side comparator 200, the low-side reference terminal PI2 can be the positive input terminal of the low-side comparator 300, and the low-side comparison terminal NI2 can be the negative input terminal of the low-side comparator 300. When the voltage at the high-side comparison terminal PI1 is greater than the high-side reference terminal NI1, the high-side output terminal GT of the high-side comparator 200 outputs a high level, otherwise it outputs a low level. When the voltage at the low-side comparison terminal NI2 is less than the low-side reference terminal PI2, the low-side output terminal DT of the low-side comparator 300 outputs a high level, otherwise it outputs a low level.

[0030] The input end of the filter 500 is connected to the first output end of the control module 400. The filter 500 can output a corresponding triangular wave based on the level signal output from the first output end, and then the high-side comparator 200 and the low-side comparator 300 output corresponding levels according to the voltage of the triangular wave.

[0031] When the voltage at the high-side comparison terminal PI1 changes from being less than the voltage at the high-side reference terminal NI1 to being greater than the voltage at the high-side reference terminal NI1, the high-side output terminal GT of the corresponding high-side comparator 200 will jump from a low level to a high level. Therefore, before the high-side comparator 200 outputs a high level, the high-side comparator 200 will output a low level. The high-side reset terminal PD can be the power-down terminal of the high-side comparator 200. When the high-side reset terminal PD is at a high level, the output of the high-side comparator 200 can be clamped to a low level. Therefore, the low level output by the high-side comparator 200 before outputting a high level, the high level output by the high-side comparator, and the clamped low level output can form a preset narrow pulse. The preset narrow pulse consists of a low level, a high level, and a low level in sequence. The first low level in the preset narrow pulse is the low level before the output terminal of the comparator jumps to a high level, and the last low level in the preset narrow pulse is the clamped output. This can avoid the output clock disorder caused by the slow falling edge of the high-side comparator 200.

[0032] When the voltage at the low-side comparison terminal NI2 changes from being greater than the voltage at the low-side reference terminal PN2 to being less than the voltage at the low-side reference terminal PN2, the low-side output terminal DT of the corresponding low-side comparator 300 will jump from a low level to a high level. Therefore, before the low-side comparator outputs a high level, the low-side comparator will output a low level. The low-side reset terminal PU can be the power-up terminal of the low-side comparator 300. When the low-side reset terminal PU is at a low level, the output of the low-side comparator 300 can be clamped to a low level, so that the low level, high level, and clamped low level output by the low-side comparator 300 form a preset narrow pulse, which can avoid the output clock disorder caused by the slow falling edge of the low-side comparator 300. Furthermore, it is convenient to improve the accuracy of the clock signal.

[0033] The control module 400 can change the level of the clock signal output from the first output end when the high-side comparator 200 outputs a high level, and change the level of the clock signal output from the first output end when the low-side comparator 300 outputs a low level. The changed level means changing from a high level to a low level or from a low level to a high level.

[0034] In other embodiments, the first output end of the control module 400 can also be connected to a buffer, and the clock signal is output to the outside through the buffer to improve the stability of the clock signal output to the outside. Figure 1The buffer is not shown. The input end of the control module 400 may include a first input end and a second input end. In Figure 1 outs may represent the output of the clock signal. R may be the first input end of the control module 400, and S may be the second input end of the control module 400. The control module may include an RS latch. The first input end of the control module may be the R end of the RS latch, and the second input end of the control module may be the S end of the RS latch.

[0035] The embodiment of the present application can realize the generation of the clock signal through the high-side comparator 200 and the low-side comparator 300, without generating oscillation through switch switching to generate the clock signal, thereby avoiding the switch charge injection during the switch switching process and also avoiding the influence of voltage offset on the clock signal, and further improving the accuracy of the clock signal.

[0036] Moreover, since the present application outputs the clock signal through the levels output by the high-side comparator 200 and the low-side comparator 300, and there will be a certain delay in the levels output by the high-side comparator 200 and the low-side comparator 300 respectively, there may be a situation where the high-side comparator 200 and the low-side comparator 300 output high levels simultaneously. Since the control module includes an RS latch, when the high-side comparator and the low-side comparator output high levels simultaneously, the RS latch will also receive two high levels simultaneously, which will destroy the complementary relationship of the RS latch, resulting in the confusion of the clock signal and reducing the accuracy of the clock signal. Therefore, in the present application, when the high-side comparator 200 outputs a high level, the high-side reset end PD is set to a high level to clamp the output of the high-side comparator 200 to a low level. Also, when the low-side comparator 300 outputs a high level, the low-side reset end PU is set to a low level to clamp the output of the low-side comparator 300 to a low level, thereby avoiding the situation where the low-side comparator 300 and the high-side comparator 200 simultaneously output high levels, so as to improve the accuracy of the clock signal.

[0037] In a feasible embodiment, please refer to Figure 2 , the high-side comparator 200 includes a first current source unit 210, a high-side comparison unit 220, and a high-side secondary clamping unit 230 connected in sequence; The high-side comparison unit 220 is connected to the high-side reference end NI1, the high-side comparison end PI1, and the high-side output end GT. The high-side secondary clamping unit 230 is connected to the high-side reset end PD and the high-side output end GT. The first current source unit 210 is connected to the high-side enable end SW of the high-side comparator 200, and the high-side enable end SW is connected to the second output end Q of the control module 400; The high-side comparator 200 is used to output a high level when the high-side enable terminal SW is at a high level and the voltage of the high-side comparison terminal PI1 is greater than the voltage of the high-side reference terminal NI1; The high-side secondary clamping unit 230 is used to clamp the high-side output terminal GT to a low level to form a preset narrow pulse when the high-side reset terminal PD is set to a high level. The preset narrow pulse consists of a low level, a high level, and a low level in sequence; The first current source unit 210 is used to output a first preset maximum current when the high-side enable terminal SW is at a high level, and is also used to output a first preset low-power consumption current when the high-side enable terminal SW is at a low level.

[0038] It should be noted that the high-side comparator 200 is a comparator with fast single-edge response. For example, when the voltage of the high-side comparison terminal PI1 is greater than the voltage of the high-side reference terminal NI1, the high-side comparator 200 can output a high level relatively quickly. When the voltage of the high-side comparison terminal PI1 is less than the voltage of the high-side reference terminal NI1, the high-side comparator 200 outputs a low level relatively slowly.

[0039] The first current source unit 210 can generate a current to drive the high-side comparator 200 to output a corresponding level, such as a high level. The first current source is connected to the high-side enable terminal SW of the high-side comparator 200. The high-side enable terminal SW is connected to the second output terminal of the control module 400. The second output terminal is also connected to the low-side enable terminal SWB of the low-side comparator 300. The level received by the low-side enable terminal SWB is the same as the level received by the high-side enable terminal SW because they are both output from the second output terminal.

[0040] The current generated by the first current source is dynamic. For example, when the high-side enable terminal SW is at a high level, it outputs a first preset maximum current, and is also used to output a first preset low-power consumption current when the high-side enable terminal SW is at a low level. The first preset maximum current can be the maximum current that the first current source can generate. The first preset low-power consumption current can be determined based on the actual situation. The first preset low-power consumption current indicates that the first current source is not completely turned off and still retains a weak current source working so that when the high-side enable terminal SW is reset next time, the first current source can respond quickly, and further enable the high-side comparator 200 to respond quickly to quickly output a high level. The greater the current output by the first current source, the faster the response speed of the high-side comparator 200, and vice versa.

[0041] The high-side secondary clamping unit 230 is connected to the high-side comparison unit 220 and the high-side output terminal GT. When the high-side comparator 200 outputs a high level and the high-side reset terminal PD is at a high level, the high-side secondary clamping unit 230 can clamp the output of the high-side comparator 200 to a low level, which is also convenient for saving the power consumption of the high-side comparator 200. Since the time when the high-side comparator 200 is at a high level is reduced, the power consumption is saved.

[0042] The high-side comparison unit 220 enables the high-side comparator 200 to quickly respond when the voltage at the high-side comparison terminal PI1 is greater than that at the high-side reference terminal NI1, and respond slowly when the voltage at the high-side comparison terminal PI1 is less than that at the high-side reference terminal NI1. Thus, it is not necessary to respond quickly in both cases, which is convenient for saving power consumption. Because if both sides need to respond quickly, higher energy consumption needs to be provided for the case of slow response to make the response fast.

[0043] In a feasible embodiment, please refer to Figure 3 , the first current source includes a first switching transistor M1 and a second switching transistor M2; the high-side comparison unit 220 includes a third switching transistor M3, a fourth switching transistor M4, a fifth switching transistor M5, a sixth switching transistor M6, a seventh switching transistor M7, an eighth switching transistor M8, and a ninth switching transistor M9; The first end of the first switching transistor M1 is connected to the high-side enable terminal SW, the first end of the second switching transistor M2 is connected to the first preset bias voltage VBN, the second end of the second switching transistor M2 is connected to the preset low voltage terminal VSS, and the third end of the second switching transistor M2 is connected to the second end of the first switching transistor M1; The third end of the first switching transistor M1 is connected to the second end of the third switching transistor M3 and the second end of the fourth switching transistor M4. The first end of the third switching transistor M3 is connected to the high-side reference terminal NI1, and the first end of the fourth switching transistor M4 is connected to the high-side comparison terminal PI1; The third end of the fourth switching transistor M4 is connected to the third end of the fifth switching transistor M5. The second end of the fifth switching transistor M5 is connected to the second end of the sixth switching transistor M6. The first end of the sixth switching transistor M6 is connected to the first end of the fifth switching transistor M5, and the third end of the sixth switching transistor M6 is connected to the third end of the third switching transistor M3; The second end of the fourth switching transistor M4 is connected to the third end of the ninth switching transistor M9. The first ends of the ninth switching transistor M9 and the seventh switching transistor M7 are both connected to the first preset bias voltage VBN. The second end of the seventh switching transistor M7 is connected to the second end of the ninth switching transistor M9, and the third end of the seventh switching transistor M7 is connected to the high-side output terminal GT and the high-side secondary clamping unit 230; The high-side output terminal GT is also connected to the third end of the eighth switching transistor M8. The first and second ends of the eighth switching transistor M8 are both connected to the high-side secondary clamping unit 230.

[0044] It should be noted that each switching transistor is a field - effect transistor. For any switching transistor, the first terminal of the switching transistor can be the gate of the switching transistor, the second terminal of the switching transistor can be the source of the switching transistor, and the third terminal of the switching transistor can be the drain of the switching transistor. The first current source includes that the first switching transistor M1 and the second switching transistor M2 can both be NOMS.

[0045] The high - side enable terminal SW can serve as the switch of the first current source. For example, when the high - side enable terminal SW is at a high level, the first current source outputs a first preset maximum current, and the response speed of the high - side comparator 200 is the fastest. Until the high - side comparator 200 outputs a high level, the high - side enable terminal SW switches to a low level. When the high - side enable terminal SW switches to a low level, the first current source outputs a first preset low - power consumption current so that the comparator can respond quickly when SW is pulled high next time. Since the first current source does not need to continuously output the first preset maximum current all the time, it only needs to output the first preset maximum current when the high - side comparator 200 needs to output a high level, thereby saving power without affecting the original function. The preset low - voltage terminal VSS can be the negative pole of the power supply.

[0046] Among them, the control module 400 is used to output a low level at the second output terminal after the high - side comparator 200 outputs a high level, and thus can set both the high - side enable terminal SW and the low - side enable terminal SWB to a low level. In the case where the low - side comparator 300 outputs a high level, it outputs a high level at the second output terminal, and thus can set both the high - side enable terminal SW and the low - side enable terminal SWB to a high level. That is to say, after the high - side comparator 200 finishes comparing, the low - side comparator 300 conducts the comparison, and so on in a cycle.

[0047] The first preset bias voltage VBN can provide bias voltages for the second switching transistor M2, the ninth switching transistor M9, and the seventh switching transistor M7 to ensure the normal operation of the circuit. The third switching transistor M3, the fourth switching transistor M4, the seventh switching transistor M7, and the ninth switching transistor M9 can all be NMOS, and the fifth switching transistor M5, the sixth switching transistor M6, and the eighth switching transistor M8 can all be PMOS.

[0048] The following describes the process of the high - side output terminal GT outputting a level when the high - side comparison terminal PI1 and the high - side reference terminal NI1 change, in combination with the high - side comparison unit 220. When the voltage of the high - side comparison terminal PI1 is greater than the voltage of the high - side reference terminal NI1, the drain level of the fourth switching transistor M4 is pulled low, the current of the eighth switching transistor M8 increases, the drain level of the eighth switching transistor M8 is pulled high, and the high - side output terminal GT outputs a high level.

[0049] When the voltage at the high-side comparison terminal PI1 is less than that at the high-side reference terminal NI1, the drain level of the third switching transistor M3 is pulled low, the current of the fifth switching transistor M5 increases, the drain level of the fifth switching transistor M5 is pulled high, the current of the eighth switching transistor M8 decreases, the drain level of the eighth switching transistor M8 is pulled low, and the high-side output terminal GT outputs a low level. Therefore, when the voltage at the high-side comparison terminal PI1 is greater than the voltage at the high-side reference terminal NI1, the signal passes through the fourth switching transistor M4 and the eighth switching transistor M8. When the voltage at the high-side comparison terminal PI1 is less than the voltage at the high-side reference terminal NI1, the signal passes through the third switching transistor M3, the fifth switching transistor M5, the sixth switching transistor M6, and the eighth switching transistor M8. When the voltage at the high-side comparison terminal PI1 is greater than the voltage at the high-side reference terminal NI1, fewer devices are passed through by the signal, meaning less delay and faster response. When the voltage at the high-side comparison terminal PI1 is less than the voltage at the high-side reference terminal NI1, more devices are passed through by the signal, resulting in greater delay and slower response.

[0050] In a feasible embodiment, please refer to Figure 3 , the high-side secondary clamping unit 230 includes a first clamping switching transistor MQ1, a second clamping switching transistor MQ2, a first inverter F1, and a second inverter F2; The first end of the first clamping switching transistor MQ1 is connected to the output end of the first inverter F1. The output end of the first inverter F1 is also connected to the input end of the second inverter F2. The input end of the first inverter F1 is connected to the high-side reset terminal PD. The second end of the first clamping switching transistor MQ1 is connected to the second end of the eighth switching transistor M8. The third end of the first clamping switching transistor MQ1 is connected to the first end of the eighth switching transistor M8; The output end of the second inverter F2 is connected to the first end of the second clamping switching transistor MQ2. The second end of the second clamping switching transistor MQ2 is connected to the preset low voltage terminal VSS. The third end of the second clamping switching transistor MQ2 is connected to the high-side output terminal GT.

[0051] It should be noted that the first clamping switching transistor MQ1 can be a PMOS, and the second clamping switching transistor MQ2 can be an NMOS. The specific connection relationships of the first clamping switching transistor MQ1 and the second clamping switching transistor MQ2 with the high-side comparison unit 220 can be referred to Figure 3 , which will not be elaborated in this embodiment. The first inverter F1 and the second inverter F2 are used to invert the input. For example, when the input is a high level, the inverter outputs a low level. When the input is a low level, the inverter outputs a high level.

[0052] Refer to Figure 3, a brief description of the process of clamping the high-side secondary clamping unit 230 is as follows. After the high-side comparator 200 outputs a high level, the first output terminal of the control module 400 outputs a high level. The first output terminal is connected to the high-side reset terminal PD. Therefore, the high-side reset terminal PD is pulled high, the first clamping switch transistor MQ1 is turned on, the eighth switch transistor M8 is turned off, the second clamping switch transistor MQ2 is turned on, the second stage of the high-side comparator 200 is clamped to a low level, and the high-side output terminal GT of the high-side comparator 200 outputs a low level. Clamping the second stage of the high-side comparator 200 to a low level can save the power consumption of the second stage of the comparator. Moreover, the high level output by the high-side comparator 200 and the low level output by the second-stage clamping form a narrow pulse, which can avoid the output clock disorder caused by the slower falling edge of the high-side comparator 200.

[0053] In a feasible embodiment, please refer to Figure 4 , the low-side comparator 300 includes a second current source unit 310, a low-side comparison unit 320, and a low-side secondary clamping unit 330 connected in sequence; The low-side comparison unit 320 is connected to the low-side reference terminal PI2, the low-side comparison terminal NI2, and the low-side output terminal DT. The low-side secondary clamping unit 330 is connected to the low-side reset terminal PU and the low-side output terminal DT. The second current source unit 310 is connected to the low-side enable terminal SWB of the low-side comparator 300, and the low-side enable terminal SWB is connected to the second output terminal of the control module 400; The low-side comparator 300 is used to output a high level when the low-side enable terminal SWB is at a low level and the voltage of the low-side comparison terminal NI2 is greater than the voltage of the low-side reference terminal PI2; The low-side secondary clamping unit 330 is used to clamp the low-side output terminal DT to a low level when the low-side reset terminal PU is set to a low level to form a preset narrow pulse; The second current source unit 310 is used to output a second preset maximum current when the low-side enable terminal SWB is at a low level, and is also used to output a second preset low-power consumption current when the low-side enable terminal SWB is at a high level.

[0054] It should be noted that the low-side comparator 300 is also a comparator with a fast single-edge response. For example, when the voltage of the low-side comparison terminal NI2 is less than the voltage of the low-side reference terminal PI2, the low-side comparator 300 can output a high level relatively quickly. When the voltage of the low-side comparison terminal NI2 is greater than the voltage of the low-side reference terminal PI2, the low-side comparator 300 outputs a low level relatively slowly.

[0055] The second current source unit 310 can generate a current to drive the low-side comparator 300 to output a corresponding level, such as a high level. The second current source is connected to the low-side enable terminal SWB of the low-side comparator 300. The low-side enable terminal SWB is connected to the second output terminal of the control module 400, and the second output terminal is also connected to the low-side enable terminal SWB of the low-side comparator 300. The level received by the low-side enable terminal SWB is the same as the level received by the low-side enable terminal SWB because they are both output from the second output terminal.

[0056] The current generated by the second current source is dynamic. For example, when the low-side enable terminal SWB is at a low level, the second preset maximum current is output, and it is also used to output the second preset low-power consumption current when the low-side enable terminal SWB is at a high level. After the low-side comparator 300 outputs a high level, the control module 400 will set the low-side enable terminal SWB to a high level.

[0057] The second preset maximum current can be the maximum current that the second current source can generate. The second preset low-power consumption current can be determined based on the actual situation. The second preset low-power consumption current indicates that the second current source is not completely turned off and still retains a weak current source working so that when the low-side enable terminal SWB is pulled low next time, the second current source can respond quickly, and then the low-side comparator 300 can respond quickly to quickly output a high level. The greater the current output by the second current source, the faster the response speed of the low-side comparator 300, and vice versa. The first preset maximum current and the second preset maximum current can be the same or different.

[0058] The low-side secondary clamping unit 330 is connected to the low-side comparison unit 320 and the low-side output terminal DT. The low-side secondary clamping unit 330 can clamp the output of the low-side comparator 300 to a low level when the low-side comparator 300 outputs a high level and the low-side reset terminal PU is at a low level, which also helps to save the power consumption of the low-side comparator 300 because it reduces the time when the low-side comparator 300 is at a high level, so the power consumption is saved.

[0059] The low-side comparison unit 320 can enable the low-side comparator 300 to quickly respond when the voltage of the low-side comparison terminal NI2 is less than the voltage of the low-side reference terminal PI2, and respond slowly when the voltage of the low-side comparison terminal NI2 is greater than the voltage of the low-side reference terminal PI2. Then, it is not necessary to respond quickly to both situations, which helps to save power consumption because if both sides need to respond quickly, higher energy consumption needs to be provided for the slow-response situation to make the response fast.

[0060] In a feasible embodiment, referring to Figure 5 , the second current source unit 310 includes a tenth switching transistor M10 and an eleventh switching transistor M11; The low-side comparison unit 320 includes: a twelfth switching transistor M12, a thirteenth switching transistor M13, a fourteenth switching transistor M14, a fifteenth switching transistor M15, a sixteenth switching transistor M16, a seventeenth switching transistor M17, an eighteenth switching transistor M18, and a third inverter F3; A first end of the tenth switching transistor M10 is connected to a low-side enable terminal SWB, a first end of the eleventh switching transistor M11 is connected to a second preset bias voltage VBP, a second end of the eleventh switching transistor M11 is connected to a preset power supply terminal VDD, and a third end of the eleventh switching transistor M11 is connected to a second end of the tenth switching transistor M10; A third end of the tenth switching transistor M10 is connected to a second end of the twelfth switching transistor M12 and a second end of the thirteenth switching transistor M13, a first end of the twelfth switching transistor M12 is connected to a low-side reference terminal PI2, and a first end of the thirteenth switching transistor M13 is connected to a low-side comparison terminal NI2; A third end of the thirteenth switching transistor M13 is connected to a third end of the fourteenth switching transistor M14, a second end of the fourteenth switching transistor M14 is connected to a second end of the fifteenth switching transistor M15, a first end of the fifteenth switching transistor M15 is connected to a first end of the fourteenth switching transistor M14, and a third end of the fifteenth switching transistor M15 is connected to a third end of the twelfth switching transistor M12; A second end of the twelfth switching transistor M12 is connected to a third end of the eighteenth switching transistor M18, a first end of the eighteenth switching transistor M18 and a first end of the seventeenth switching transistor M17 are connected to the second preset bias voltage VBP, and a second end and a third end of the seventeenth switching transistor M17 are connected to a low-side secondary clamping unit 330; A third end of the seventeenth switching transistor M17 is connected to an input end of the third inverter F3 and a third end of the sixteenth switching transistor, a first end and a second end of the sixteenth switching transistor are connected to the low-side secondary clamping unit 330, and an output end of the third inverter F3 is connected to a low-side output end DT.

[0061] It should be noted that the tenth switch tube and the eleventh switch tube M11 included in the second current source can both be PMOS. The low-side enable terminal SWB can serve as the switch of the second current source. For example, when it is necessary for the low-side comparator 300 to make a comparison, the low-side enable terminal SWB can be set to a low level. When the low-side enable terminal SWB is at a low level, the second current source outputs a second preset maximum current, and the response speed of the low-side comparator is the fastest at this time. Until the low-side comparator 300 outputs a high level, the low-side enable terminal SWB switches to a high level. After the low-side enable terminal SWB switches to a low level, the second current source outputs a second preset low-power consumption current so that the low-side comparator 300 can quickly respond after SWB is pulled low next time. Since the second current source does not need to continuously output the second preset maximum current all the time, it only needs to output the second preset maximum current when the low-side comparator 300 needs to output a high level, thereby saving power without affecting the original function. The preset power supply terminal VDD can be the positive pole of the power supply.

[0062] Among them, the control module 400 is used to output a high level at the second output terminal after the low-side comparator 300 outputs a high level, and thus can set both the high-side enable terminal SW and the low-side enable terminal SWB to a high level.

[0063] The second preset bias voltage VBP can provide a bias voltage for the eleventh switch tube M11, the seventeenth switch tube M17, and the eighteenth switch tube M18 to ensure the normal operation of the circuit. The twelfth switch tube M12, the thirteenth switch tube M13, the seventeenth switch tube M17, and the eighteenth switch tube M18 are PMOS, and the fourteenth switch tube M14, the fifteenth switch tube M15, and the sixteenth switch tube M16 can all be NMOS. The third inverter F3, the fourth inverter F4, and the fifth inverter F5 can all be used to invert the input.

[0064] The following combines with the low-side comparison unit 320 to illustrate the process of the output level of the low-side output terminal DT when the low-side comparison terminal NI2 and the low-side reference terminal PI2 change. When the voltage of the low-side comparison terminal NI2 is less than the voltage of the low-side reference terminal PI2, the drain level of the thirteenth switch tube M13 is pulled high, the current of the sixteenth switch tube M16 increases, the drain level of the sixteenth switch tube M16 is pulled low, and the third inverter F3 reverses the input low level to a high level, causing the low-side output terminal DT to output a high level.

[0065] When the voltage of the low-side comparison terminal NI2 is greater than the voltage of the low-side reference terminal PI2, the drain level of the twelfth switch tube M12 is pulled high, the current of the fourteenth switch tube M14 increases, the drain level of the fourteenth switch tube M14 is pulled low, the current of the sixteenth switch tube M16 decreases, the drain level of the sixteenth switch tube M16 is pulled high, and a low level is output after passing through the third inverter F3.

[0066] When the voltage of the low-side comparison terminal NI2 is greater than the voltage of the low-side reference terminal PI2, the signal passes through the thirteenth switching transistor M13, the sixteenth switching transistor M16, and the third inverter F3; when the voltage of the low-side comparison terminal NI2 is less than the voltage of the low-side reference terminal PI2, the signal passes through the twelfth switching transistor M12, the fourteenth switching transistor M14, the fifteenth switching transistor M15, the sixteenth switching transistor M16, and the third inverter F3. Therefore, when the voltage of the low-side comparison terminal NI2 is less than the voltage of the low-side reference terminal PI2, fewer devices are passed through, the delay is small, and the response is faster; while when the voltage of the low-side comparison terminal NI2 is greater than the voltage of the low-side reference terminal PI2, more devices are passed through, the delay is large, and the response is slow. Furthermore, when a too-fast response speed is not required, power consumption can be saved. And since both the low-side comparator 300 and the high-side comparator 200 exist in this embodiment, when each comparator needs to output a high level respectively, a fast response can be achieved, thereby reducing the delay.

[0067] In a feasible embodiment, please refer to Figure 5 , the low-side secondary clamping unit 330 includes: a third clamping switching transistor MQ3, a fourth clamping switching transistor MQ4, a fourth inverter F4, and a fifth inverter F5; The low-side reset terminal PU is connected to the input terminal of the fourth inverter F4. The output terminal of the fourth inverter F4 is connected to the input terminal of the fifth inverter F5 and the first terminal of the third clamping switching transistor MQ3. The second terminal of the third clamping switching transistor MQ3 is connected to the second terminal of the sixteenth switching transistor M16, and the third terminal of the third clamping switching transistor MQ3 is connected to the first terminal of the sixteenth switching transistor M16; The output terminal of the fifth inverter F5 is connected to the first terminal of the fourth clamping switching transistor MQ4. The second terminal of the fourth clamping switching transistor MQ4 is connected to the preset power supply terminal VDD, and the third terminal of the fourth clamping switching transistor MQ4 is connected to the input terminal of the third inverter F3.

[0068] It should be noted that the third clamping switching transistor MQ3 can be an NMOS, the fourth clamping switching transistor MQ4 can be a PMOS, and both the second terminal and the third terminal of the third clamping switching transistor MQ3 can be connected to the low-side comparison unit 320. The specific connection relationship between the third clamping switching transistor MQ3 and the fourth clamping switching transistor MQ4 and the low-side comparison unit 320 can refer to Figure 5 , which will not be elaborated in this embodiment. Both the fourth inverter F4 and the fifth inverter F5 are used to invert the input.

[0069] Refer to Figure 5, a brief description of the clamping process of the low-side secondary clamping unit 330 is given. After the low-side comparator 300 outputs a high level, the first output terminal of the control module 400 outputs a low level. The first output terminal is connected to the low-side reset terminal PU. Therefore, the low-side reset terminal PU is pulled low, the third clamping switch transistor MQ3 conducts, the sixteenth switch transistor M16 cuts off, the fourth clamping switch transistor MQ4 conducts, the second stage of the low-side comparator 300 is clamped to a low level, and the low-side output terminal DT of the low-side comparator 300 outputs a low level. Furthermore, the power consumption of the second stage of the low-side comparator 300 can be saved, and the high level output by the low-side comparator 300 and the low level output by the second-stage clamping form a narrow pulse, which can avoid the output clock disorder caused by the slower falling edge of the low-side comparator 300.

[0070] It can be understood that when the first output terminal outputs a low level, both the low-side reset terminal PU and the high-side reset terminal PD are pulled low. At this time, the output of the low-side comparator 300 is clamped to a low level, while the high-side comparator 200 outputs a high level when the high-side comparison terminal PI1 is greater than the voltage of the high-side reference terminal NI1, and the high-side comparator is not clamped, that is, the high-side comparator 200 performs comparison. When the first output terminal outputs a high level, both the low-side reset terminal PU and the high-side reset terminal PD are pulled high. At this time, the output terminal of the high-side comparator 200 will be clamped to a low level, while the low-side comparator 300 will output a high level when the low-side comparison terminal NI2 is less than the voltage of the low-side reference terminal PI2, that is, the low-side comparator 300 performs comparison.

[0071] In addition, for a better understanding of the circuit connection relationship of this embodiment, reference can be made to Figure 6 , Figure 6 which shows the overall circuit connection schematic diagram of the relaxation oscillator. The buffer 600 is shown in Figure 6 , and the VRC in Figure 6 can refer to the voltage output by the filter 500.

[0072] Furthermore, for a better understanding of this embodiment, an explanation of the situation where there is no clock disorder after the comparator is clamped at two levels can be made. Reference can be made to Figure 7 , Figure 8 , Figure 9 and Figure 10 , Figure 7 which gives the internal structure of the control module 400 and the internal structure of the filter 500. Figure 8 shows the waveform schematic diagram of the VRC waveform output by the filter 500 under ideal conditions. Figure 9 shows the schematic diagram of the VRC waveform actually output by the filter 500. Figure 10 shows the schematic diagram of the waveform of the actual output VRC of the filter 500 when the comparator has two-level clamping and when there is no two-level clamping.

[0073] First, refer toFigure 7 , a brief description will be given to the connection relationship between the control module 400 and the filter 500 shown in Figure 7 . Among them, the control module 400 includes an RS latch 410, an AND gate, a sixth inverter F6, and a seventh inverter F7; the RS latch 410 includes a first NOR gate H1 and a second NOR gate H2. The first input terminal of the AND gate YM can be used as the second output terminal of the control module, the second input terminal PBD of the AND gate can be used as the preset input control terminal in the reference voltage module 100, and the output terminal of the sixth inverter F6 can be used as the first output terminal of the control module 400; the high-side output terminal GT of the high-side comparator 200 can be connected to the R terminal of the RS latch 410, the low-side output terminal DT of the low-side comparator 300 can be connected to the S terminal of the RS latch 410, the R terminal of the RS latch 410 can be the first input terminal of the control module 400, and the S terminal of the RS latch 410 can be the second input terminal of the control module 400. The filter 500 includes a filter switching transistor 510 and a first resistor R1. The source, drain, and body of the filter switching transistor 510 are connected to the ground, and the first resistor R1 can be a P-Poly resistor. For the connection relationship between the components in the control module 400 and the filter 500, reference can be specifically made to Figure 7 , and this embodiment will not elaborate on this again.

[0074] Referring to Figure 8 , the reference voltage of the high-side comparator 200 is , the reference voltage of the low-side comparator 300 , Figure 8 where VRC in refers to the voltage waveform output from the voltage output terminal of the filter 500. From it increases to through the RC response, taking a time of the first ideal time tr. After passing through the relaxation loop of the comparator, and then from it decreases to through the RC response, taking a time of the second ideal time tf. The ideal oscillation period

[0075]

[0076]

[0077]

[0078]

[0079] It should be noted that the ideal oscillation period is the sum of tr and tf, and e is the natural logarithm.

[0080] Referring again to Figure 9 , Figure 9 shows the actual VRC waveform of the filter 500. In the relaxation oscillator of this embodiment, there is a comparator delay , and there is a latch delay of the RS latch 410 in the control module 400 , an inverter delay and an AND gate delay . When VRC is greater than , it first experiences the delay of the high-side comparator 200, and then the delay of going around the control module 400 and returning to the high-side comparator 200 is set as the first delay td1. At this time, VRC reaches the maximum value VH, and then drops to through the RC response. This delay is set as the second delay td2. Similarly, when VRC is less than , it first experiences the delay of the low-side comparator 300, plus the delay of the control module 400. This delay is also td1. At this time, VRC reaches the minimum value VL, and then rises to through the RC response. This delay is also td2. And from increases to through the RC response, taking RCln2 time, and from decreases to through the RC response, taking RCln2 time. Therefore, the actual period of the oscillator is twice the sum of RCln2, td1, and td2. For example, reference can be made to Formulas 6 to 10, which give the derivation process of the actual period.

[0081]

[0082]

[0083]

[0084] Formula 9:

[0085]

[0086] It should be noted that referring to Figure 7 , it can be seen that there are two inverters in the control module 400, so the first delay is twice the . Figure 9The output waveform of the clock signal is also given, and it can be seen that the output period of the clock signal is also , and the high and low levels of the clock signal output will change with the jump of the VRC.

[0087] Refer to Figure 10 , in Figure 10 , the waveform in the a area shows the situation when neither the high-side comparator 200 nor the low-side comparator 300 is clamped, and the waveform in the b area shows the waveform after the high-side comparator 200 and the low-side comparator 300 are both clamped at the second stage. Among them, GR can represent the level change of the high-side output terminal GT. Since the high-side output terminal GT is connected to the R terminal of the RS latch 410, GR can also reflect the level change of the R terminal of the RS latch 410; DS can represent the level change of the low-side output terminal DT. Since the low-side output terminal DT is connected to the S terminal of the RS latch 410, DS can also reflect the level change of the S terminal of the RS latch 410; QBD can refer to the level change of the first output terminal of the control module 400, and the level change of the clock signal is also shown. It can be seen that the level change of the QBD output is the same as the level change of the clock signal.

[0088] Refer to Figure 10 , it can be seen from the a area of that when the second stage of the low-side comparator 300 and the high-side comparator 200 is not dynamically clamped, when the low-side output terminal DT (i.e., DS) of the low-side comparator 300 is pulled high, the output (i.e., GR) of the high-side comparator 200 responds slowly. After the VRC is less than Figure 10 , it does not quickly pull low. The QBD maintains the original state until GR pulls low, and then the QBD changes state. This leads to an increase in delay, that is, in tdx1>td1, tdx2>td2. Among them, in the area represented by c, it can be seen that there is a situation where GR and DS are both at high level, which leads to the delay becoming tdx1 and tdx2. When the second stage of the high-side comparator 200 and the low-side comparator 300 is added with dynamic clamping control, after the VRC is greater than , a narrow pulse is generated. After the VRC is less than Figure 10 , a narrow pulse is also generated. Furthermore, the second-stage clamping of the low-side comparator 300 and the high-side comparator 200 can be realized, which can ensure that the RS latch 410 in each cycle is only sensitive to the rising edge. Furthermore, the latch state of the RS latch 410 can be changed through the narrow pulse, so that the rising delay is td1 and the falling delay is td2, and there will be no situation where the rising delay is unstable and the falling delay is unstable (for example, in

[0089] In another feasible embodiment, please refer to Figure 11 , the reference voltage module 100 further includes a preset inverting unit and a preset voltage dividing unit. The preset inverting unit is connected to the preset voltage dividing unit, and the preset voltage dividing unit is connected to the high-side reference terminal NI1 and the low-side reference terminal PI2; The preset inverting unit includes a first preset switching transistor My1 and a second preset switching transistor My2. The first ends of the first preset switching transistor My1 and the second preset switching transistor My2 are both connected to a preset input control terminal. The second end of the first preset switching transistor My1 is connected to a preset power supply terminal VDD. The third ends of the first preset switching transistor My1, the second preset switching transistor My2, and the second end of the second preset switching transistor My2 are all connected to the preset voltage dividing unit.

[0090] It should be noted that the preset inverting unit can be used to implement the soft start process. By controlling the high-threshold reference voltage to gradually stabilize from VDD to 2 / 3VDD and the low-threshold reference voltage to gradually stabilize from VSS to 1 / 3VDD, the clock frequency of the clock signal is gradually established from low to high to the target frequency to avoid the digital circuit from running wild. The target frequency is the frequency that the clock signal needs to reach. The high-threshold reference voltage can be the voltage provided by the reference voltage module 100 to the high-side reference terminal NI1, and the low-threshold voltage can be the voltage provided by the reference voltage module 100 to the low-side reference terminal PI2.

[0091] The first preset switching transistor My1 can be a PMOS, and the second preset switching transistor My2 can be an NMOS. Since the body terminal of the second switching transistor M2 is connected to the preset low voltage terminal VSS, when the PDB switches from low level to high level, the voltage of the second preset switching transistor My2 can increase gradually without sudden change. For example, please refer to Figure 12 , when the PDB switches from low level to high level, the high-threshold reference voltage gradually stabilizes from VDD to 2 / 3VDD, the low-threshold reference voltage gradually stabilizes from VSS to 1 / 3VDD, and then VRC can jump back and forth between 2 / 3VDD and 1 / 3VDD, and the frequency of the clock signal can also gradually stabilize from low to high to the target frequency, thereby avoiding the clock frequency of the digital circuit being too fast when it is just connected, avoiding the digital circuit from running wild, and facilitating the improvement of the circuit stability.

[0092] In a feasible embodiment, please refer to Figure 11 , the preset voltage dividing unit includes a first voltage dividing switching transistor Mf1, a second voltage dividing switching transistor Mf2, and a third voltage dividing switching transistor Mf3; The first end of the first voltage-dividing switch transistor Mf1 is connected to the high-side reference terminal NI1, the second end of the first voltage-dividing switch transistor Mf1 is connected to the preset power supply terminal VDD, and the third end of the first voltage-dividing switch transistor Mf1 is connected to the second end of the second voltage-dividing switch transistor Mf2; The first end of the second voltage-dividing switch transistor Mf2 is connected to the third end of the first preset switch transistor My1 and the third end of the second preset switch transistor My2, and the third end of the second voltage-dividing switch transistor Mf2 is connected to the second end of the third voltage-dividing switch transistor Mf3 and the low-side reference terminal PI2; Both the first end and the third end of the third voltage-dividing switch transistor Mf3 are connected to the preset low voltage terminal VSS.

[0093] It should be noted that the preset voltage-dividing unit can provide a high threshold reference voltage for the high-side comparator 200 and a low threshold reference voltage for the low-side comparator 300. A first preset grounding switch transistor Md1 can also be provided between the first voltage-dividing switch transistor Mf1 and the high-side comparison terminal PI1, and a second preset grounding switch transistor Md2 can also be provided between the second end of the third voltage-dividing switch transistor Mf3 and the low-side reference terminal PI2. The first preset grounding switch transistor Md1 and the second preset grounding switch transistor Md2 can both be NMOS, which play a role in filtering and voltage stabilization.

[0094] The first voltage-dividing switch transistor Mf1, the second voltage-dividing switch transistor Mf2, and the third voltage-dividing switch transistor Mf3 have the same model and can all be PMOS. The first voltage-dividing switch transistor Mf1, the second voltage-dividing switch transistor Mf2, and the third voltage-dividing switch transistor Mf3 are connected in series to divide the voltage to obtain a high threshold reference voltage and a low threshold reference voltage.

[0095] In other embodiments, reference can also be made to Figure 13 , Figure 13 shows a circuit connection diagram of the reference voltage module 100 when the first voltage-dividing switch transistor Mf1, the second voltage-dividing switch transistor Mf2, and the third voltage-dividing switch transistor Mf3 are all NMOS. When the first voltage-dividing switch transistor Mf1, the second voltage-dividing switch transistor Mf2, and the third voltage-dividing switch transistor Mf3 are all NMOS, an inverter can also be provided between the input terminal of the preset inverting unit and the PDB. For example, Figure 13The eighth inverter F8 in it is used to enable the reference voltage module 100 to input a high threshold voltage to the high-side comparison terminal PI1 and input a low threshold voltage to the low-side comparison terminal NI2. When PDB is at a low level, the first preset switching transistor My1 is turned off, the second preset switching transistor My2 is turned on, and the second voltage-dividing switching transistor Mf2 is turned off. The high threshold reference voltage is VDD, and the low threshold reference voltage is VSS. When PDB is at a high level, the first preset switching transistor My1 is turned on, the second preset switching transistor My2 is turned off, and the gate of the second voltage-dividing switching transistor Mf2 is connected to the drain. At this time, the high threshold reference becomes 2 / 3VDD, and the low threshold reference voltage becomes 1 / 3VDD. When the first voltage-dividing switching transistor Mf1, the second voltage-dividing switching transistor Mf2, and the third voltage-dividing switching transistor Mf3 are all NMOS, the connection relationship between the voltage-dividing diodes can refer to Figure 13 , and this embodiment does not make specific limitations on this.

[0096] In this embodiment, switching transistors are used in the reference voltage module 100 to generate a high threshold reference voltage and a low threshold reference voltage, which can reduce the area of the reference voltage module 100, and further reduce the area of the relaxation oscillator.

[0097] The motor provided by the embodiment of the present application uses the relaxation oscillator in the above embodiment, aiming to solve the technical problem of poor accuracy of the clock signal output by the relaxation oscillator. Compared with the prior art, the beneficial effects of the motor provided by the embodiment of the present application are the same as those of the relaxation oscillator provided by the above embodiment, and will not be elaborated here.

[0098] The above are only the preferred embodiments of the embodiments of the present application, and do not limit the patent scope of the embodiments of the present application. Any equivalent structure or equivalent process transformation made by using the specification and drawings of the embodiments of the present application, or directly or indirectly applied to other related technical fields, are equally included in the patent scope of the embodiments of the present application.

Claims

1. A relaxation oscillator, characterized in that, The relaxation oscillator includes: a reference voltage module, a high-side comparator, a low-side comparator, a control module, and a filter. The reference voltage module is connected to the high-side reference terminal of the high-side comparator and the low-side reference terminal of the low-side comparator. The high-side comparison terminal of the high-side comparator and the low-side comparison terminal of the low-side comparator are connected to the voltage output terminal of the filter; The high-side output terminal of the high-side comparator and the low-side output terminal of the low-side comparator are both connected to the input terminal of the control module. The high-side reset terminal of the high-side comparator and the low-side reset terminal of the low-side comparator are both connected to the first output terminal of the control module; The control module is configured to, when the high-side comparator outputs a high level, set the high-side reset terminal to a high level to clamp the output of the high-side comparator to a low level, so as to form a preset narrow pulse at the high-side output terminal. The preset narrow pulse consists of a low level, a high level, and a low level in sequence; The control module is further configured to, when the low-side comparator outputs a high level, set the low-side reset terminal to a low level to clamp the output of the low-side comparator to a low level, so as to form a preset narrow pulse at the low-side output terminal; The control module is further configured to, when the high-side comparator outputs a high level or the low-side comparator outputs a high level, toggle the level of the clock signal output from the first output terminal.

2. The relaxation oscillator according to claim 1, wherein The high-side comparator includes a first current source unit, a high-side comparison unit, and a high-side secondary clamping unit connected in sequence; The high-side comparison unit is connected to the high-side reference terminal, the high-side comparison terminal, and the high-side output terminal. The high-side secondary clamping unit is connected to the high-side reset terminal and the high-side output terminal. The first current source unit is connected to the high-side enable terminal of the high-side comparator, and the high-side enable terminal is connected to the second output terminal of the control module; The high-side comparator is configured to output a high level when the high-side enable terminal is at a high level and the voltage of the high-side comparison terminal is greater than the voltage of the high-side reference terminal; The high-side secondary clamping unit is configured to, when the high-side reset terminal is set to a high level, clamp the high-side output terminal to a low level to form a preset narrow pulse at the high-side output terminal; The first current source unit is configured to output a first preset maximum current when the high-side enable terminal is at a high level, and is further configured to output a first preset low-power consumption current when the high-side enable terminal is at a low level.

3. The relaxation oscillator according to claim 2, wherein The first current source includes a first switching tube and a second switching tube; the high-side comparison unit includes a third switching tube, a fourth switching tube, a fifth switching tube, a sixth switching tube, a seventh switching tube, an eighth switching tube, and a ninth switching tube; The first end of the first switching tube is connected to the high-side enable terminal. The first end of the second switching tube is connected to a first preset bias voltage. The second end of the second switching tube is connected to a preset low voltage terminal. The third end of the second switching tube is connected to the second end of the first switching tube; The third terminal of the first switching tube is connected to the second terminal of the third switching tube and the second terminal of the fourth switching tube. The first terminal of the third switching tube is connected to the high-side reference terminal, and the first terminal of the fourth switching tube is connected to the high-side comparison terminal; The third terminal of the fourth switching tube is connected to the third terminal of the fifth switching tube. The second terminal of the fifth switching tube is connected to the second terminal of the sixth switching tube. The first terminal of the sixth switching tube is connected to the first terminal of the fifth switching tube. The third terminal of the sixth switching tube is connected to the third terminal of the third switching tube; The second terminal of the fourth switching tube is connected to the third terminal of the ninth switching tube. The first terminals of the ninth switching tube and the seventh switching tube are both connected to a first preset bias voltage. The second terminal of the seventh switching tube is connected to the second terminal of the ninth switching tube. The third terminal of the seventh switching tube is connected to the high-side output terminal and the high-side secondary clamping unit; The high-side output terminal is further connected to the third terminal of the eighth switching tube. The first and second terminals of the eighth switching tube are both connected to the high-side secondary clamping unit.

4. The relaxation oscillator according to claim 3, characterized in that, The high-side secondary clamping unit includes a first clamping switching tube, a second clamping switching tube, a first inverter, and a second inverter; The first terminal of the first clamping switching tube is connected to the output terminal of the first inverter. The output terminal of the first inverter is further connected to the input terminal of the second inverter. The input terminal of the first inverter is connected to the high-side reset terminal. The second terminal of the first clamping switching tube is connected to the second terminal of the eighth switching tube. The third terminal of the first clamping switching tube is connected to the first terminal of the eighth switching tube; The output terminal of the second inverter is connected to the first terminal of the second clamping switching tube. The second terminal of the second clamping switching tube is connected to a preset low voltage terminal. The third terminal of the second clamping switching tube is connected to the high-side output terminal.

5. The relaxation oscillator according to claim 1, wherein The low-side comparator includes a second current source unit, a low-side comparison unit, and a low-side secondary clamping unit connected in sequence; The low-side comparison unit is connected to the low-side reference terminal, the low-side comparison terminal, and the low-side output terminal. The low-side secondary clamping unit is connected to the low-side reset terminal and the low-side output terminal. The second current source unit is connected to the low-side enable terminal of the low-side comparator. The low-side enable terminal is connected to the second output terminal of the control module; The low-side comparator is used to output a high level when the low-side enable terminal is at a low level and the voltage of the low-side comparison terminal is less than the voltage of the low-side reference terminal; The low-side secondary clamping unit is used to clamp the low-side output terminal to a low level when the low-side reset terminal is set to a low level, so as to form a preset narrow pulse at the low-side output terminal; The second current source unit is used to output a second preset maximum current when the low-side enable terminal is at a low level, and is further used to output a second preset low-power consumption current when the low-side enable terminal is at a high level.

6. The relaxation oscillator according to claim 5, characterized in that, The second current source unit includes a tenth switching tube and an eleventh switching tube; The low-side comparison unit includes: a twelfth switching tube, a thirteenth switching tube, a fourteenth switching tube, a fifteenth switching tube, a sixteenth switching tube, a seventeenth switching tube, an eighteenth switching tube, and a third inverter; The first terminal of the tenth switching tube is connected to the low-side enable terminal, the first terminal of the eleventh switching tube is connected to the second preset bias voltage, the second terminal of the eleventh switching tube is connected to the preset power supply terminal, and the third terminal of the eleventh switching tube is connected to the second terminal of the tenth switching tube; The third terminal of the tenth switching tube is connected to the second terminal of the twelfth switching tube and the second terminal of the thirteenth switching tube. The first terminal of the twelfth switching tube is connected to the low-side reference terminal, and the first terminal of the thirteenth switching tube is connected to the low-side comparison terminal; The third terminal of the thirteenth switching tube is connected to the third terminal of the fourteenth switching tube. The second terminal of the fourteenth switching tube is connected to the second terminal of the fifteenth switching tube. The first terminal of the fifteenth switching tube is connected to the first terminal of the fourteenth switching tube, and the third terminal of the fifteenth switching tube is connected to the third terminal of the twelfth switching tube; The second terminal of the twelfth switching tube is connected to the third terminal of the eighteenth switching tube. The first terminals of the eighteenth switching tube and the seventeenth switching tube are connected to the second preset bias voltage. The second and third terminals of the seventeenth switching tube are connected to the low-side secondary clamping unit; The third terminal of the seventeenth switching tube is connected to the input terminal of the third inverter and the third terminal of the sixteenth switching tube. The first and second terminals of the sixteenth switching tube are connected to the low-side secondary clamping unit, and the output terminal of the third inverter is connected to the low-side output terminal.

7. The relaxation oscillator according to claim 6, characterized in that, The low-side secondary clamping unit includes: a third clamping switching tube, a fourth clamping switching tube, a fourth inverter, and a fifth inverter; The low-side reset terminal is connected to the input terminal of the fourth inverter. The output terminal of the fourth inverter is connected to the input terminal of the fifth inverter and the first terminal of the third clamping switching tube. The second terminal of the third clamping switching tube is connected to the second terminal of the sixteenth switching tube, and the third terminal of the third clamping switching tube is connected to the first terminal of the sixteenth switching tube; The output terminal of the fifth inverter is connected to the first terminal of the fourth clamping switching tube. The second terminal of the fourth clamping switching tube is connected to the preset power supply terminal, and the third terminal of the fourth clamping switching tube is connected to the input terminal of the third inverter.

8. The relaxation oscillator according to claim 1, characterized in that, The reference voltage module further includes a preset inverting unit and a preset voltage dividing unit. The preset inverting unit is connected to the preset voltage dividing unit, and the preset voltage dividing unit is connected to the high-side reference terminal and the low-side reference terminal; The preset inverting unit includes a first preset switching tube and a second preset switching tube. The first terminals of the first preset switching tube and the second preset switching tube are both connected to the preset input control terminal. The second terminal of the first preset switching tube is connected to the preset power supply terminal. The third terminal of the first preset switching tube, the second and third terminals of the second preset switching tube are all connected to the preset voltage dividing unit.

9. The relaxation oscillator according to claim 8, wherein, The preset voltage dividing unit includes a first voltage dividing switching tube, a second voltage dividing switching tube, and a third voltage dividing switching tube; The first terminal of the first voltage dividing switching tube is connected to the high-side reference terminal. The second terminal of the first voltage dividing switching tube is connected to the preset power supply terminal. The third terminal of the first voltage dividing switching tube is connected to the second terminal of the second voltage dividing switching tube; The first end of the second voltage-dividing switching tube is connected to the third end of the first preset switching tube and the third end of the second preset switching tube, and the third end of the second voltage-dividing switching tube is connected to the second end of the third voltage-dividing switching tube and the low-side reference end; Both the first end and the third end of the third voltage-dividing switching tube are connected to a preset low-voltage end.

10. A motor, characterized in that, The motor includes the relaxation oscillator according to any one of claims 1-9.

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