Digital phase shifter based on FPGA (Field Programmable Gate Array) and phase shift pulse noise suppression method

Abstract

The invention relates to the technical field of new energy electrical technology control, and provides an FPGA-based digital phase shifter and a phase shift pulse noise suppression method, and the digital phase shifter comprises a digital phase shift control module which receives a phase shift trigger signal, carries out the phase shift angle deviation calculation according to the phase shift trigger signal, and carries out the phase shift pulse noise suppression when the deviation value of the phase shift angle is equal to a preset value. Outputting a phase shift ending signal; and the pulse width control module is used for receiving the phase shift ending signal, calculating the pulse width of the phase shift ending signal, and outputting a phase shift pulse control signal when the pulse width of the phase shift ending signal is equal to a pulse width preset value so as to suppress random noise interference generated in the phase shift process. According to the scheme, the digital phase shifter based on the FPGA and the phase shift pulse noise suppression method output the phase shift angle and the pulse width without limitation, have good noise suppression performance and can quickly adapt to various application requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of new energy electrical technology control, and particularly relates to a digital phase shifter based on FPGA and a phase-shifting pulse noise suppression method. Background Art

[0002] The energy structure is moving towards the direction of being clean, low-carbon, safe, and efficient. Energy storage technology, as a flexible adjustment resource, will play a key role in the construction of a new power system. Power electronics technology is the key technology for the application of energy storage technology. Rectification and inversion, as the basis of power electronics technology, are widely used. In a rectification and inversion system, the phase shifter, as one of the core components, plays a decisive role in adjusting the rectified output voltage. The phase-shifting angle range of traditional phase shifters is small, the anti-interference ability is insufficient, the quality of the rectified voltage signal output is poor, and it is easy to cause disastrous effects. Summary of the Invention

[0003] The purpose of the present invention is to solve at least one technical problem in the background art, and provide a digital phase shifter based on FPGA and a phase-shifting pulse noise suppression method.

[0004] To achieve the above purpose, the present invention provides a digital phase shifter based on FPGA, including:

[0005] A digital phase-shifting control module, which receives a phase-shifting trigger signal, calculates the phase-shifting angle offset according to the phase-shifting trigger signal, and outputs a phase-shifting end signal when the offset value of the phase-shifting angle is equal to a preset value, so as to suppress the random noise interference generated during the phase-shifting process;

[0006] A pulse width control module, which receives the phase-shifting end signal, calculates the pulse width of the phase-shifting end signal, and outputs a phase-shifting pulse control signal when the pulse width of the phase-shifting control signal is equal to a preset pulse width value, so as to suppress the random noise interference during the pulse generation process.

[0007] According to one aspect of the present invention, the digital phase-shifting control module includes: a noise suppression counter, a state flip controller, and a logic operation module;

[0008] The noise suppression counter calculates the phase-shifting angle offset according to the phase-shifting trigger signal, and outputs a status flag when the offset value of the phase-shifting angle is equal to a preset value; the noise suppression counter is connected to the system clock CLK and outputs a carry flag, where the carry flag serves as the clock input signal of the state flip controller;

[0009] The input phase-shifting trigger signal is respectively input as the reset signal of the state flip controller and the AND gate input of the logic operation module;

[0010] The state flip controller outputs a phase-shifting end signal according to the clock input signal and the phase-shifting trigger signal;

[0011] The phase shift end signal is simultaneously used as the input of the AND gate of the logic operation module. The output of the AND gate of the logic operation module and the status flag output by the noise suppression counter are used as the inputs of the OR gate of the logic operation module. The output signal of the OR gate of the logic operation module is connected to the reset port of the noise suppression counter to control the counting reset and clearing of the noise suppression counter.

[0012] According to one aspect of the present invention, the noise suppression counter is a 16-bit cyclic counter.

[0013] According to one aspect of the present invention, the state flip controller is a T flip-flop.

[0014] According to one aspect of the present invention, the pulse width control module includes a pulse width counter, a D flip-flop, and an inverter;

[0015] The pulse width counter inputs a clock signal and a low-level reset signal, and the pulse width counter outputs a counting carry flag, and the output is sent to the reset signal of the D flip-flop through the inverter;

[0016] The phase shift end signal output by the digital phase shift control module is used as the clock signal of the D flip-flop, and the positive output end of the D flip-flop outputs a phase shift pulse control signal with a set pulse width.

[0017] According to one aspect of the present invention, the pulse width counter is a 4-bit cyclic counter.

[0018] To achieve the above object, the present invention also provides a phase shift pulse noise suppression method implemented by the above-mentioned FPGA-based digital phase shifter, including:

[0019] The digital phase shift control module receives a phase shift trigger signal, calculates the phase shift angle offset according to the phase shift trigger signal, and when the offset value of the phase shift angle is equal to a preset value, outputs a phase shift end signal to suppress the random noise interference generated during the phase shift process;

[0020] The pulse width control module receives the phase shift end signal, calculates the pulse width of the phase shift end signal, and when the pulse width of the phase shift control signal is equal to the preset pulse width value, outputs a phase shift pulse control signal to suppress the random noise interference during the pulse generation process.

[0021] To achieve the above object, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored on the memory and executable on the processor. When the computer program is executed by the processor, the phase shift pulse noise suppression method as described above is implemented.

[0022] To achieve the above object, the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the phase-shifting pulse noise suppression method as described above is implemented.

[0023] According to the solution of the present invention, the present invention is implemented based on FPGA, the phase-shifting angle and pulse width are configurable, with a wide adjustment range, and at the same time, random noise interference can be well suppressed.

[0024] According to the solution of the present invention, the digital phase shifter and phase-shifting pulse noise suppression method based on FPGA of the present invention have unlimited output phase-shifting angle and pulse width, have good noise suppression performance, and can quickly adapt to various application requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematically showing a system block diagram of a digital phase shifter based on FPGA according to an embodiment of the present invention;

[0026] Figure 2 Schematically showing a structural block diagram of a digital phase-shifting control module according to an embodiment of the present invention;

[0027] Figure 3 Schematically showing a structural block diagram of a pulse width control module according to an embodiment of the present invention;

[0028] Figure 4 Schematically showing a simulation diagram of the phase-shifted waveform output obtained by a digital phase shifter based on FPGA according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] Now, the content of the present invention will be described with reference to exemplary embodiments. It should be understood that the described embodiments are only for enabling those of ordinary skill in the art to better understand and thus implement the content of the present invention, rather than implying any limitation to the scope of the present invention.

[0030] As used herein, the term "comprising" and its variants are to be construed as open-ended terms meaning "including but not limited to". The term "based on" is to be construed as "at least partially based on". The terms "one embodiment" and "an embodiment" are to be construed as "at least one embodiment".

[0031] Figure 1 Schematically showing a system block diagram of a digital phase shifter based on FPGA according to an embodiment of the present invention. As Figure 1 shown, in this embodiment, the digital phase shifter based on FPGA includes:

[0032] The digital phase shift control module 5 receives a phase shift trigger signal, calculates the phase shift angle offset according to the phase shift trigger signal, and outputs a phase shift end signal when the offset value of the phase shift angle is equal to a preset value, so as to suppress the random noise interference generated during the phase shift process;

[0033] The pulse width control module 6 receives the phase shift end signal, calculates the pulse width of the phase shift end signal, and outputs a phase shift pulse control signal when the pulse width of the phase shift control signal is equal to the preset pulse width value, so as to suppress the random noise interference during the pulse generation process.

[0034] Further, Figure 2 Schematically shows a structural block diagram of a digital phase shift control module according to an embodiment of the present invention. As Figure 2 shown, in this embodiment, the digital phase shift control module 5 includes: a noise suppression counter CNT1, a state flip controller TFF, and a logic operation module;

[0035] The noise suppression counter CNT1 calculates the phase shift angle offset according to the phase shift trigger signal PulseTrig, and outputs a status flag Status when the offset value of the phase shift angle is equal to the preset value; the noise suppression counter CNT1 is connected to the system clock CLK and outputs a carry flag Carry1, where the carry flag Carry1 serves as the clock input signal of the state flip controller TFF;

[0036] The input phase shift trigger signal PulseTrig serves as the reset signal CLRn input of the state flip controller TFF and the input of the AND gate & of the logic operation module respectively;

[0037] The state flip controller TFF outputs a phase shift end signal PluseEnd according to the clock input signal and the phase shift trigger signal PulseTrig;

[0038] The phase shift end signal PluseEnd serves as the input of the AND gate of the logic operation module at the same time. The output of the AND gate of the logic operation module and the status flag Status output by the noise suppression counter CNT1 serve as the inputs of the OR gate of the logic operation module. The output signal of the OR gate of the logic operation module is connected to the reset port Rstn of the noise suppression counter CNT1 to control the counting reset and clearing of the noise suppression counter CNT1.

[0039] In this embodiment, the noise suppression counter CNT1 is a 16-bit cyclic counter.

[0040] In this embodiment, the state flip controller TFF is a T flip-flop.

[0041] In this embodiment, the input signals of the digital phase-shifting control module 5 are the system clock CLK and the phase-shifting trigger signal PulseTrig. When the phase-shifting trigger signal PulseTrig arrives, the noise suppression counter CNT1 is started. When a noise suppression count is completed (i.e., the phase-shift angle offset calculation is performed according to the phase-shifting trigger signal, and the calculation is completed when the offset value of the phase-shift angle is equal to the preset value of the offset value given by the system), the status flag Status outputs a low level, and the carry flag Carry1 outputs a high level. The carry flag Carry1 signal is connected to the clock of the T flip-flop, and the T flip-flop flips to output the phase-shift end control signal PulseEnd. One path is output to the subsequent pulse width control module 6, and the other path passes through an inverter and AND-OR gate logic and is connected to the reset port Rstn of the noise suppression counter CNT1 to control the reset of the noise suppression counter CNT1 and wait for the next phase-shifting trigger signal PulseTrig to arrive, and the foregoing process is repeated.

[0042] Further, Figure 3 Schematically shows a structural block diagram of a pulse width control module according to an embodiment of the present invention. As Figure 3 shown, in this embodiment, the pulse width control module 6 includes a pulse width counter CNT2, a D flip-flop, and an inverter;

[0043] The pulse width counter CNT2 inputs a clock signal and a low-level reset signal, and the pulse width counter CNT2 outputs a count carry flag Carry2, and the output passes through an inverter to the reset signal CLRn of the D flip-flop;

[0044] The phase-shift end signal PluseEnd output by the digital phase-shifting control module 5 serves as the clock signal of the D flip-flop, and the positive output end of the D flip-flop outputs a phase-shift pulse control signal Pulse with a set pulse width.

[0045] In this embodiment, the pulse width counter CNT2 inputs a clock signal CLK and a low-level reset signal Rstn, and the pulse width counter outputs a count carry flag, and the output passes through an inverter to the reset (clear) signal of the D flip-flop;

[0046] The low-level reset signal Rstn of the pulse width counter CNT2 is generated by Figure 3 the DFF and is a feedback control signal. Its mechanism is as follows: when the phase-shift end PluseEnd signal arrives, the Q end of the asynchronous clear DFF flip-flop outputs a high level. When the CNT2 counter counts up, Carry2 is set to 1, passes through an inverter to CLRn, and is asynchronously reset. The Q end of the DFF outputs a low level, and this low level generated is input to the Rstn end of CNT2, and CNT2 is cleared. In the whole process, a pulse signal with the width of the CNT2 counter is generated at the Q end, achieving the purpose of pulse width control.

[0047] In this embodiment, the pulse width counter CNT2 is a 4-bit cyclic counter.

[0048] In this embodiment, the rising edge of the phase shift end PluseEnd output by the digital phase shift control module 5 is connected to the clock terminal of the D flip-flop inside the pulse width control module 6. The data terminal of the D flip-flop is connected to a high level. When the rising edge of the phase shift control end arrives, the positive output Q terminal of the D flip-flop starts to output a high-level phase shift pulse signal, and at the same time, the internal pulse width counter CNT2 starts to count. When the pulse width count reaches the set value, the carry flag Carry2 output by the pulse width counter CNT2 is set high and output, and after passing through an inverter, a low level is output to control the reset of the D flip-flop. The positive output Q terminal of the D flip-flop outputs a low level, completing the output of the phase shift pulse control signal with a specified width.

[0049] Figure 4 Schematically shows the simulation diagram of the phase shift waveform output obtained by the FPGA-based digital phase shifter according to an embodiment of the present invention. As Figure 4 shown, they are respectively the system clock CLK signal, the Rstn reset signal, the Pulse phase shift trigger pulse signal, and the Q2 output phase shift pulse signal. It can be seen that in the four time periods marked 1, 2, 3, and 4 in the figure, there is a large amount of random noise interference in the simulation of the phase shift trigger pulse. At this time, the phase shift output pulse output by the Q2 port is not affected by the noise and normally outputs the waveform of the preset phase shift angle and pulse width.

[0050] Furthermore, to achieve the above object, the present invention also provides a method for suppressing phase shift pulse noise implemented by the above FPGA-based digital phase shifter, including:

[0051] The digital phase shift control module receives the phase shift trigger signal, calculates the phase shift angle offset according to the phase shift trigger signal, and when the offset value of the phase shift angle is equal to the preset value, outputs a phase shift end signal to suppress the random noise interference generated during the phase shift process;

[0052] The pulse width control module receives the phase shift end signal, calculates the pulse width of the phase shift end signal, and when the pulse width of the phase shift control signal is equal to the pulse width preset value, outputs a phase shift pulse control signal to suppress the random noise interference during the pulse generation process.

[0053] Furthermore, to achieve the above object, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the above-mentioned method for suppressing phase shift pulse noise is implemented.

[0054] Furthermore, to achieve the above object, the present invention also provides a computer-readable storage medium with a computer program stored thereon. When the computer program is executed by a processor, the phase-shifting pulse noise suppression method described above is implemented.

[0055] According to the above solution of the present invention, the present invention is implemented based on FPGA. The phase-shifting angle and pulse width are configurable, with a wide adjustment range, and can also well suppress random noise interference.

[0056] According to the above solution of the present invention, the FPGA-based digital phase shifter and phase-shifting pulse noise suppression method of the present invention have unrestricted output phase-shifting angle and pulse width, have good noise suppression performance, and can quickly adapt to various application requirements.

[0057] Those of ordinary skill in the art can realize that the modules and algorithm steps described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0058] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the devices and equipment described above can refer to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0059] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or modules can be in an electrical, mechanical or other forms.

[0060] The modules described as separate components may or may not be physically separated. The components shown as modules may or may not be physical modules, that is, they can be located in one place, or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present invention.

[0061] In addition, each functional module in the embodiments of the present invention may be integrated into one processing module, may exist separately physically for each module, or two or more modules may be integrated into one module.

[0062] If the above functions are implemented in the form of software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method for sending / receiving energy-saving signals in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, external hard drives, ROM, RAM, magnetic disks, or optical discs that can store program codes.

[0063] The above description is only for the preferred embodiments of the present application and the description of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in the present application.

[0064] It should be understood that the magnitudes of the sequence numbers of the steps in the inventive content and the embodiments of the present invention do not absolutely mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

Claims

1. A digital phase shifter based on FPGA, characterized in that, including: A digital phase-shift control module that receives a phase-shift trigger signal, calculates the phase-shift angle offset according to the phase-shift trigger signal, and outputs a phase-shift end signal when the offset value of the phase-shift angle is equal to a preset value, so as to suppress the random noise interference generated during the phase-shift process; A pulse width control module that receives the phase-shift end signal, calculates the pulse width of the phase-shift end signal, and outputs a phase-shift pulse control signal when the pulse width of the phase-shift control signal is equal to the preset pulse width value, so as to suppress the random noise interference generated during the pulse generation process.

2. The digital phase shifter based on FPGA according to claim 1, wherein The digital phase-shift control module includes: a noise suppression counter, a state flip-flop controller, and a logic operation module; The noise suppression counter calculates the phase-shift angle offset according to the phase-shift trigger signal, and outputs a status flag when the offset value of the phase-shift angle is equal to the preset value; the noise suppression counter is connected to the system clock CLK and outputs a carry flag, where the carry flag is used as the clock input signal of the state flip-flop controller; The input phase-shift trigger signal is respectively used as the reset signal input of the state flip-flop controller and the AND gate input of the logic operation module; The state flip-flop controller outputs a phase-shift end signal according to the clock input signal and the phase-shift trigger signal; The phase-shift end signal is simultaneously used as the input of the AND gate of the logic operation module, the output of the AND gate of the logic operation module and the status flag output by the noise suppression counter are used as the input of the OR gate of the logic operation module, and the output signal of the OR gate of the logic operation module is connected to the reset port of the noise suppression counter to control the counting reset and clearing of the noise suppression counter.

3. The digital phase shifter based on FPGA according to claim 2, characterized in that, The noise suppression counter is a 16-bit cyclic counter.

4. The digital phase shifter based on FPGA according to claim 2, characterized in that The state flip-flop controller is a T flip-flop.

5. The digital phase shifter based on FPGA according to claim 1, wherein The pulse width control module includes a pulse width counter, a D flip-flop, and an inverter; The pulse width counter inputs a clock signal and a low-level reset signal, the pulse width counter outputs a counting carry flag, and the output passes through an inverter to the reset signal of the D flip-flop; The phase-shift end signal output by the digital phase-shift control module is used as the clock signal of the D flip-flop, and the positive output terminal of the D flip-flop outputs a phase-shift pulse control signal with a set pulse width.

6. The digital phase shifter based on FPGA according to claim 5, wherein The pulse width counter is a 4-bit cyclic counter.

7. A phase shift pulse noise suppression method implemented by the FPGA-based digital phase shifter according to any one of claims 1-6, characterized in that, including: The digital phase-shift control module receives a phase-shift trigger signal, calculates the phase-shift angle offset according to the phase-shift trigger signal, and outputs a phase-shift end signal when the offset value of the phase-shift angle is equal to a preset value, so as to suppress the random noise interference generated during the phase-shift process; The pulse width control module receives the phase-shift end signal, calculates the pulse width of the phase-shift end signal, and outputs a phase-shift pulse control signal when the pulse width of the phase-shift control signal is equal to the preset pulse width value, so as to suppress the random noise interference generated during the pulse generation process.

8. An electronic device, characterized in that, including a processor, a memory, and a computer program stored on the memory and executable on the processor, where the computer program, when executed by the processor, implements the phase-shift pulse noise suppression method as claimed in claim 7.

9. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements the phase-shift pulse noise suppression method as claimed in claim 7.

Images