Buffer and analog-to-digital converter

Abstract

The analog-to-digital converter comprises a first switch, a second switch and a sampling capacitor, the first end of the first switch is connected with the input end of the buffer, the input end of the buffer is used for receiving an input signal, and the first end of the second switch is connected with the output end of the buffer. The second end of the first switch is connected with the second end of the second switch to form an output node, and the sampling capacitor is connected with the output node; the buffer comprises a first transistor, a second transistor, a first current source and a second current source; the first end of the first transistor is connected with a first current source, the control end of the second transistor is connected with the first end of the first transistor, and the first end of the second transistor is connected with a second current source. According to the buffer and the analog-to-digital converter, a traditional rail-to-rail operational amplifier is not adopted as the buffer, so that power consumption can be saved; by adopting the open-loop buffer, the signal establishment speed of the analog-to-digital converter in the pre-charging stage can be greatly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a buffer and an analog-to-digital converter. Background Art

[0002] A sampling capacitor C1 can be seen at the ADC (analog-to-digital converter) input acquisition port, and there is an equivalent input current. For an external high-impedance input signal, the input current will introduce an input offset, resulting in inaccurate ADC acquisition data. A common method is to add a buffer U1 at the ADC input port, as Figure 1 shown. Through the buffer U1, the internal capacitance can be blocked from extracting current from the outside, reducing the input current and improving the sampling accuracy of the ADC.

[0003] However, the common implementation method of the buffer U1 is generally in the form of an operational amplifier, and the operational amplifier consumes a relatively large amount of power.

[0004] The information disclosed in this background art section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of suggestion that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0005] The object of the present invention is to provide a buffer and an analog-to-digital converter that can reduce power consumption.

[0006] To achieve the above object, the technical solution provided by a specific embodiment of the present invention is as follows: A buffer for an analog-to-digital converter, the analog-to-digital converter includes a first switch, a second switch, and a sampling capacitor. The first end of the first switch is connected to the input end of the buffer, the input end of the buffer is used to receive an input signal, the first end of the second switch is connected to the output end of the buffer, the second end of the first switch and the second end of the second switch are connected to form an output node, the sampling capacitor is connected to the output node, the second switch is used to be turned on during the pre-charge stage to pre-charge the sampling capacitor through the buffer, and the first switch is used to be turned on after the pre-charge stage ends to charge the sampling capacitor through the input signal;

[0007] The buffer includes a first transistor, a second transistor, a first current source, and a second current source; the control end of the first transistor forms the input end of the buffer, the first end of the first transistor is connected to the first current source, the control end of the second transistor is connected to the first end of the first transistor, and the first end of the second transistor is connected to the second current source and forms the output end of the buffer.

[0008] In one or more embodiments of the present invention, the buffer further includes:

[0009] A matching unit, configured to obtain a first matching voltage equal to the voltage between the control terminal and the first terminal of the second transistor;

[0010] A clamping unit and a current generating unit, the clamping unit is connected to the matching unit to form a first node for receiving the first matching voltage, the clamping unit is connected to the current generating unit to form a second node for clamping the voltage of the second node to be equal to a second matching voltage of the first matching voltage, and the current generating unit generates a matching current based on the second matching voltage;

[0011] A control unit, connected to the clamping unit and the first current source, to control the first current source to mirror the matching current, and the first current source is configured to deliver the mirrored matching current to the first transistor, so that the voltage between the first terminal and the control terminal of the first transistor matches the voltage between the control terminal and the first terminal of the second transistor.

[0012] In one or more embodiments of the present invention, the matching unit includes a third current source and a third transistor, and the control terminal and the second terminal of the third transistor are connected to the third current source to form a first node.

[0013] In one or more embodiments of the present invention, the current generating unit includes a fourth transistor, the first terminal of the fourth transistor is connected to the second node, and the control terminal of the fourth transistor is connected to the second terminal of the fourth transistor.

[0014] In one or more embodiments of the present invention, the clamping unit includes an amplifier and a fifth transistor, the first input terminal of the amplifier is connected to the first node, the output terminal of the amplifier is connected to the control terminal of the fifth transistor, the second input terminal of the amplifier is connected to the first terminal of the fifth transistor and the second node, and the second terminal of the fifth transistor is connected to the control unit.

[0015] In one or more embodiments of the present invention, the control unit includes a sixth transistor, the control terminal of the sixth transistor is connected to the second terminal of the sixth transistor and the clamping unit, and the control terminal of the sixth transistor is connected to the first current source to control the first current source to mirror the matching current.

[0016] In one or more embodiments of the present invention, the first current source includes a seventh transistor, the control terminal of the seventh transistor is connected to the control unit, and the second terminal of the seventh transistor is connected to the first terminal of the first transistor and the control terminal of the second transistor.

[0017] In one or more embodiments of the present invention, the third transistor and the second transistor are equal, where I n3is the threshold current of the third transistor, W3 is the channel width of the third transistor, L3 is the channel length of the third transistor, I n2 is the threshold current of the second transistor, W2 is the channel width of the second transistor, L2 is the channel length of the second transistor.

[0018] In one or more embodiments of the present invention, the channel types of the second transistor and the third transistor are the same.

[0019] The present invention also discloses an analog-to-digital converter including the buffer described above.

[0020] Compared with the prior art, the buffer and the analog-to-digital converter of the present invention do not use a traditional rail-to-rail operational amplifier as a buffer, thus being able to save power consumption; using an open-loop buffer can greatly improve the signal establishment speed of the analog-to-digital converter during the precharge stage, and then improve the precharge speed of the sampling capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 FIG. is the circuit schematic diagram of an analog-to-digital converter with a buffer in the prior art.

[0023] Figure 2 FIG. is the circuit schematic diagram of the buffer in an embodiment of the present invention.

[0024] Figure 3 FIG. is the circuit schematic diagram of an analog-to-digital converter with a buffer in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0026] The "coupling", "connection", or "linkage" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through circuits or components such as switches and follower circuits. Additionally, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity, or order between these technical features.

[0027] In the detailed description of the specification, reference is made to the accompanying drawings that form a part thereof, in which like reference numerals always refer to like components, and which are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. Accordingly, the following detailed description should not be taken as limiting.

[0028] The various operations in the specification may be described sequentially as a number of discrete actions or operations in a manner most helpful for understanding the claimed subject matter. However, the order of description should not be construed to imply that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from that of the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0029] For the purposes of the present application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present application, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0030] Various components and devices may be referred to or shown herein in the singular form (e.g., "MOS transistor", "transistor", "switch", etc.), but this is merely for convenience of discussion, and any element referred to in the singular form may include a plurality of such elements in accordance with the teachings herein.

[0031] The specification describes using the phrase "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. Additionally, the terms "comprising", "including", "having", etc. used with respect to the embodiments of the present application are synonymous.

[0032] As Figure 2As shown, a buffer in an embodiment of the present invention can be used in an analog-to-digital converter. The buffer includes a first transistor M1, a second transistor M2, a first current source A1, and a second current source A2.

[0033] The control terminal of the first transistor M1 forms the input terminal Vin of the buffer to receive an input signal. The first terminal of the first transistor M1 is connected to the first current source A1, and the first current source A1 is simultaneously connected to the first power supply voltage. The control terminal of the second transistor M2 is connected to the first terminal of the first transistor M1. The second terminal of the second transistor M2 is connected to the second power supply voltage. The first terminal of the second transistor M2 is connected to the second current source A2 and forms the output terminal Vout of the buffer. In practical applications, the first power supply voltage is greater than the second power supply voltage.

[0034] In addition, the buffer further includes: a matching unit 10, a clamping unit 20, a current generating unit 30, and a control unit 40.

[0035] The matching unit 10 obtains a first matching voltage V1 equal to the voltage difference between the control terminal and the first terminal of the second transistor M2 based on the matching design with the second transistor M2.

[0036] The clamping unit 20 is connected to the matching unit 10 to form a first node to receive the first matching voltage V1. The clamping unit 20 is connected to the current generating unit 30 to form a second node to clamp the voltage of the second node to a second matching voltage V2 equal to the first matching voltage V1. The current generating unit 30 generates a matching current Ii based on the second matching voltage V2.

[0037] The control unit 40 is connected to the clamping unit 20 and the first current source A1 to control the first current source A1 to mirror the matching current Ii. The first current source A1 is used to deliver the mirrored matching current Ii to the first transistor M1, so that the voltage difference between the first terminal and the control terminal of the first transistor M1 matches the voltage difference between the control terminal and the first terminal of the second transistor M2.

[0038] Specifically, as Figure 2 shown, the matching unit 10 includes a third current source A3 and a third transistor M3. The control terminal, the second terminal of the third transistor M3 are connected to the third current source A3 to form a first node, and the first terminal of the third transistor M3 is connected to the ground voltage.

[0039] In one embodiment, the current generating unit 30 includes a fourth transistor M4. The first terminal of the fourth transistor M4 is connected to the second node, and the control terminal of the fourth transistor M4 is connected to the second terminal of the fourth transistor M4 and the ground voltage.

[0040] In one embodiment, the clamping unit 20 includes an amplifier OP and a fifth transistor M5. The first input terminal of the amplifier OP is connected to the first node, the output terminal of the amplifier OP is connected to the control terminal of the fifth transistor M5, the second input terminal of the amplifier OP is connected to the first terminal of the fifth transistor M5 and the second node, and the second terminal of the fifth transistor M5 is connected to the control unit 40.

[0041] In one embodiment, the control unit 40 includes a sixth transistor M6. The first terminal of the sixth transistor M6 is connected to the first power supply voltage. The control terminal of the sixth transistor M6 is connected to the second terminal of the sixth transistor M6 and the second terminal of the fifth transistor M5 of the clamping unit 20. The control terminal of the sixth transistor M6 is connected to the first current source A1 to control the first current source A1 to mirror and match the current Ii.

[0042] In one embodiment, the first current source A1 includes a seventh transistor M7. The first terminal of the seventh transistor M7 is connected to the first power supply voltage. The control terminal of the seventh transistor M7 is connected to the control terminal of the sixth transistor M6 of the control unit 40. The second terminal of the seventh transistor M7 is connected to the first terminal of the first transistor M1 and the control terminal of the second transistor M2.

[0043] The sixth transistor M6 and the seventh transistor M7 form a current mirror. In other embodiments, a current mirror with a cascode structure may also be used.

[0044] In one embodiment, the second transistor M2 and the third transistor M3 have the same channel type, that is, the second transistor M2 and the third transistor M3 are N-channel MOS transistors, and the fifth transistor M5 is also an N-channel MOS transistor. The first transistor M1, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are P-channel MOS transistors. In other embodiments, the second transistor M2, the third transistor M3, and the fifth transistor M5 may be P-channel MOS transistors, and the first transistor M1, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 may be N-channel MOS transistors.

[0045] The first ends of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are source electrodes; the second ends of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are drain electrodes; the control ends of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are gate electrodes.

[0046] As Figure 2 shown, if it is required to make the output signal of the output terminal Vout of the buffer U2 equal to the input signal received by the input terminal Vin of the buffer U2, then it is necessary to make the gate-source voltage |VGS1| of the first transistor M1 equal to the gate-source voltage |VGS2| of the second transistor M2.

[0047] From the calculation formula of the gate-source voltage of the transistor: (Vth is the threshold voltage of the transistor, I n is the threshold current of the transistor, μ is the carrier mobility of the transistor, Cox is the gate oxide capacitance per unit area of the transistor, W is the channel width of the transistor, and L is the channel length of the transistor M), it can be seen that if the of the third transistor M3 and the of the second transistor M2 are made equal by matching design, where I n3 is the threshold current of the third transistor M3, W3 is the channel width of the third transistor M3, L3 is the channel length of the third transistor M3, I n2 is the threshold current of the second transistor M2, W2 is the channel width of the second transistor M2, and L2 is the channel length of the second transistor M2, then the gate-source voltage |VGS3| of the third transistor M3 is equal to the gate-source voltage |VGS2| of the second transistor M2.

[0048] Through the negative feedback loop formed by the amplifier OP and the fifth transistor M5, the gate-source voltage |VGS4| of the fourth transistor M4 (i.e., the second matching voltage V2) can be made equal to the gate-source voltage |VGS3| of the third transistor M3 (i.e., the first matching voltage V1). Due to its gate-source voltage |VGS3|, the third transistor M3 generates a matching current Ii. The matching current Ii flows into the first transistor M1 through the current mirror composed of the sixth transistor M6 and the seventh transistor M7. At this time, the gate-source voltage |VGS1| of the first transistor M1 is equal to the gate-source voltage |VGS4| of the fourth transistor M4. Therefore, the gate-source voltage |VGS1| of the first transistor M1 is equal to the gate-source voltage |VGS2| of the second transistor M2, that is, the output signal at the output terminal Vout of the buffer U2 is equal to the input signal received at the input terminal Vin of the buffer U2, realizing that the input range of the input signal of the buffer is not affected by the gate-source voltage |VGS| of the transistor, and achieving the effect of full-amplitude output without increasing too much power consumption.

[0049] In other embodiments, the matching unit 10, the clamping unit 20, the current generating unit 30, and the control unit 40 may not be provided. However, since the threshold voltage Vth1 of the first transistor M1 and the Vth2 of the second transistor M2 are not the same, and the carrier mobilities are also different, the gate-source voltage |VGS1| of the first transistor M1 is different from the gate-source voltage |VGS2| of the second transistor M2, resulting in poor complementary effect. The input range of the input signal of the buffer will be affected, and it is difficult to make the input signal of the buffer equal to the output signal.

[0050] As Figure 3 shown, the present invention also discloses an analog-to-digital converter, including a selector MUX, a capacitor C0, a first switch S1, a second switch S2, a buffer U2, a third switch S3, a sampling capacitor C1, a sampling resistor R, a fourth switch S4, a comparator COMP, and a control logic circuit CONTROL LOGIC. The buffer U2 is Figure 2 the buffer for the analog-to-digital converter as shown. In other embodiments, other analog-to-digital converters containing the buffer U2 may also be used.

[0051] The selector MUX has multiple input terminals and is connected to the corresponding input ports I / O0…I / O7. The output terminal of the selector MUX is connected to the input terminal Vin of the buffer U2. The input terminal Vin of the buffer U2 is used to receive the input signal. The capacitor C0 is connected between the input terminal Vin of the buffer U2 and the ground voltage.

[0052] The first terminal of the first switch S1 is connected to the input terminal Vin of the buffer U2, the first terminal of the second switch S2 is connected to the output terminal Vout of the buffer U2, and the second terminal of the first switch S1 is connected to the second terminal of the second switch S2 to form an output node O. The first terminal of the third switch S3 is connected to the output node O, the second terminal of the third switch S3 is connected to the ground voltage, and the common terminal of the third switch S3 is connected to the first terminal of the sampling capacitor C1. The third switch S3 is used to control the switching of the first terminal of the sampling capacitor C1 between the output node O and the ground voltage.

[0053] The second terminal of the sampling capacitor C1 is connected to the first terminal of the sampling resistor R. The second terminal of the sampling resistor R is connected to the first terminal of the fourth switch S4 and the non-inverting input terminal of the comparator COMP. The second terminal of the fourth switch S4 is connected to the ground voltage. The inverting input terminal of the comparator COMP is connected to the ground voltage. The output terminal of the comparator COMP is connected to the subsequent control logic circuit CONTROLLOGIC.

[0054] In one embodiment, during the pre-charge phase, the second switch S2 is turned on, the fourth switch S4 is turned on, and the first terminal of the sampling capacitor C1 is connected to the output node O to pre-charge the sampling capacitor C1 through the buffer U2. After the pre-charge phase ends, the first switch S1 is turned on to quickly charge the sampling capacitor C1 through the input signal. After the sampling phase ends, the first terminal of the sampling capacitor C1 is connected to the ground voltage and the fourth switch S4 is turned off, entering the hold phase.

[0055] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, in any aspect, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be encompassed by the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0056] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A buffer for an analog-to-digital converter, characterized in that, The analog-to-digital converter includes a first switch, a second switch, and a sampling capacitor. A first end of the first switch is connected to an input end of a buffer, and the input end of the buffer is configured to receive an input signal. A first end of the second switch is connected to an output end of the buffer. A second end of the first switch and a second end of the second switch are connected to form an output node, and the sampling capacitor is connected to the output node. The second switch is configured to be turned on during a pre-charge phase to pre-charge the sampling capacitor through the buffer, and the first switch is configured to be turned on after the pre-charge phase ends to charge the sampling capacitor through the input signal. The buffer includes a first transistor, a second transistor, a first current source, and a second current source. A control end of the first transistor forms the input end of the buffer. A first end of the first transistor is connected to the first current source. A control end of the second transistor is connected to the first end of the first transistor, and a first end of the second transistor is connected to the second current source and forms the output end of the buffer.

2. The buffer according to claim 1, wherein The buffer further includes: a matching unit configured to obtain a first matching voltage equal to a voltage between a control end and a first end of the second transistor; a clamping unit and a current generating unit. The clamping unit is connected to the matching unit to form a first node for receiving the first matching voltage, and the clamping unit is connected to the current generating unit to form a second node for clamping the voltage of the second node to a second matching voltage equal to the first matching voltage. The current generating unit generates a matching current based on the second matching voltage; a control unit connected to the clamping unit and the first current source to control the first current source to mirror the matching current. The first current source is configured to deliver the mirrored matching current to the first transistor, so that a voltage between a first end and a control end of the first transistor matches a voltage between a control end and a first end of the second transistor.

3. The buffer according to claim 2, characterized in that, The matching unit includes a third current source and a third transistor. A control end, a second end of the third transistor, and the third current source are connected to form a first node.

4. The buffer according to claim 2, wherein, The current generating unit includes a fourth transistor. A first end of the fourth transistor is connected to the second node, and a control end of the fourth transistor is connected to a second end of the fourth transistor.

5. The buffer according to claim 2, wherein The clamping unit includes an amplifier and a fifth transistor. A first input end of the amplifier is connected to the first node, an output end of the amplifier is connected to a control end of the fifth transistor, a second input end of the amplifier is connected to a first end of the fifth transistor and the second node, and a second end of the fifth transistor is connected to the control unit.

6. The buffer according to claim 2, characterized in that The control unit includes a sixth transistor. A control end of the sixth transistor is connected to a second end of the sixth transistor and the clamping unit, and the control end of the sixth transistor is connected to the first current source to control the first current source to mirror the matching current.

7. The buffer according to claim 2, characterized in that, The first current source includes a seventh transistor. A control end of the seventh transistor is connected to the control unit, and a second end of the seventh transistor is connected to a first end of the first transistor and a control end of the second transistor.

8. The buffer according to claim 3, characterized in that The of the third transistor is equal to that of the second transistor, where I n3 is the threshold current of the third transistor, W3 is the channel width of the third transistor, L3 is the channel length of the third transistor, and I n2 is the threshold current of the second transistor, W2 is the channel width of the second transistor, and L2 is the channel length of the second transistor.

9. The buffer according to claim 3, characterized in that, The second transistor and the third transistor have the same channel type.

10. An analog-to-digital converter, characterized in that, Comprising a buffer as described in any one of claims 1 to 9.

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