Voltage slew rate calibration circuit and method for fractional-N frequency-sampling phase-locked loop

Abstract

The present invention provides a voltage slew rate calibration circuit and method for a fractional-N sampling phase-locked loop (PLL). In addition to a voltage rate conversion state machine, the voltage slew rate calibration circuit also includes and utilizes a sampling phase detector, an oscillator, a sampling clock generation circuit, and a digital-to-time converter within the sampling PLL. The sampling phase detector includes a ramp generator and a sampling circuit, and the voltage slew rate calibration state machine controls the output voltage slew rate of the ramp generator. The fractional-N sampling PLL circuit and its voltage slew rate calibration circuit and method provided by the present invention address the shortcomings of existing voltage slew rate calibration techniques for sampling phase detectors within sampling PLLs, such as increased hardware design and other costs, and reduced calibration accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of voltage conversion rate calibration, and more particularly to a voltage conversion rate calibration circuit and method for a fractional-N frequency-sampling phase-locked loop circuit. Background Art

[0002] Traditional voltage slew rate calibration techniques are primarily used in driver circuits or analog amplifiers. These techniques detect the transition time between a low-to-high voltage and a high-to-low voltage on the rising or falling edge of the output signal. For example, they detect a high output level during the transition period and a low output level at all other times. Counters and / or other circuits are then used to generate control signals to adjust resistor / capacitor sizes, transistor dimensions, and other factors, ultimately achieving voltage slew rate calibration.

[0003] For the sampling phase detector in a sampling phase-locked loop (PLL), the voltage slew rate of the clock signal after passing through the ramp generator, along with the clock frequency, determines the sampling phase detector gain. Therefore, variations in the clock signal's voltage slew rate with process corners affect the loop bandwidth at different process corners. To minimize loop bandwidth variations, the clock signal's voltage slew rate must be calibrated. However, directly employing the aforementioned traditional voltage slew rate calibration technique requires additional detection circuitry, increasing hardware design and other costs.

[0004] Existing techniques for calibrating the voltage slew rate of a sampling phase detector in a sampling phase-locked loop (PLL) involve replicating the sampling phase detector circuit to generate a replicated differential sampling output signal. This sampled output signal is then passed through peak detection and comparator circuits to obtain a transfer time detection result. Finally, a counter is used to obtain a corresponding voltage slew rate control signal. Based on this control signal, the voltage slew rate of the sampling phase detector in the sampling phase-locked loop is calibrated (e.g., [US7288958B2]).

[0005] While existing technologies (e.g., [US7288958B2]) utilize a replicated sampling phase detector to reduce detection circuit design costs compared to directly applying traditional voltage slew rate calibration techniques, they still require the design of additional peak detection circuits, comparators, and counters. Furthermore, the deviation of the analog peak detection circuit can affect the voltage slew rate detection results, and it is not easy to iterate the design across different process generations. Consequently, existing technologies still suffer from the drawbacks of increased hardware design and other costs, as well as reduced calibration accuracy.

[0006] Based on the above technical problems, there is an urgent need for a solution that does not require additional hardware design and can effectively ensure calibration accuracy. Summary of the Invention

[0007] In view of the above problems, the purpose of the present invention is to provide a voltage conversion rate calibration circuit and method for a fractional-N sampling phase-locked loop circuit, so as to solve the problems that the existing voltage conversion rate calibration technology used for the sampling phase detector in the sampling phase-locked loop has the disadvantages of increasing hardware design and other costs, and reducing calibration accuracy.

[0008] The present invention provides a voltage conversion rate calibration circuit for a fractional-N frequency-sampling phase-locked loop, comprising a fractional-N frequency-sampling phase-locked loop circuit and a voltage conversion rate calibration state machine, wherein the fractional-N frequency-sampling phase-locked loop circuit comprises a sampling phase detector, an oscillator, a sampling clock generating circuit and a digital-to-time converter; wherein,

[0009] The oscillator is used to generate an oscillation clock signal;

[0010] The reference clock signal is processed by the digital-to-time converter and the sampling clock generating circuit in sequence to form a sampling clock signal;

[0011] The sampling phase detector is used to process the loop feedback clock signal converted from the oscillation clock signal and the sampling clock signal, and generate a phase detection output signal;

[0012] The voltage conversion rate calibration state machine is used to control the output voltage conversion rate of the sampling phase detector.

[0013] In addition, a preferred solution is that the fractional-N frequency-sampling phase-locked loop circuit further includes a multi-mode frequency divider; and

[0014] The multi-mode frequency divider is used to process the oscillation clock signal and output the loop feedback clock signal.

[0015] In addition, a preferred solution is that the fractional-N frequency-sampling phase-locked loop circuit further includes a modulator; and,

[0016] The fractional frequency division of the fractional-N frequency-sampling phase-locked loop circuit is achieved by controlling the multi-mode frequency divider through the output of the frequency control word after passing through the modulator.

[0017] In addition, a preferred solution is that the sampling phase detector includes a ramp generator and a sampling circuit; wherein,

[0018] The input signal of the ramp generator includes the loop feedback clock signal, the input signal of the sampling circuit includes the sampling clock signal, and the output signal of the ramp generator is sampled by the sampling circuit to form the phase detection output signal; and

[0019] The voltage slew rate calibration state machine is used to control the output voltage slew rate of the ramp generator.

[0020] In addition, a preferred solution is that a loop filter is provided between the output end of the sampling phase detector and the oscillator; wherein,

[0021] The phase detection output signal is used to control the frequency and phase of the oscillator after being processed by the loop filter; and

[0022] When the fractional-N sampling phase-locked loop circuit is closed, the frequency and phase of the oscillator track the reference clock signal.

[0023] In addition, a preferred solution is that the oscillator is equipped with an automatic frequency calibration module;

[0024] The digital-to-time converter is equipped with a range calibration module and a gain calibration module.

[0025] In addition, a preferred solution is that a sampling voltage monitoring circuit is connected to the output end of the sampling phase detector.

[0026] On the other hand, the present invention also provides a voltage conversion rate calibration method for a fractional-N frequency-sampling phase-locked loop, which is based on the aforementioned voltage conversion rate calibration circuit for the fractional-N frequency-sampling phase-locked loop. The calibration method includes:

[0027] S110: Performing automatic frequency calibration on the oscillator through an automatic frequency calibration module;

[0028] S120: Performing range calibration on the digital-to-time converter by a range calibration module;

[0029] S130: Perform voltage slew rate calibration on the sampling phase detector based on the voltage slew rate calibration state machine.

[0030] In addition, a preferred solution is that the range calibration module includes a digital-to-time converter replica and a digital-to-time converter range calibration state machine; and performing range calibration on the digital-to-time converter by the range calibration module includes:

[0031] The same reference clock signal is inputted into the digital-to-time converter and the replica digital-to-time converter simultaneously; wherein the input codewords of the digital-to-time converter and the replica digital-to-time converter are a maximum converter code and a minimum converter code respectively;

[0032] Performing phase comparison between the output signal of the digital-to-time converter and the output signal of the replica digital-to-time converter after a set delay through the sampling phase detector;

[0033] generating a range control codeword for the digital-to-time converter based on the phase comparison result by the digital-to-time converter range calibration state machine;

[0034] The digital-to-time converter is range-calibrated using the range control codeword.

[0035] In addition, a preferred solution is that the voltage slew rate calibration of the sampling phase detector based on the voltage slew rate calibration state machine includes:

[0036] Inputting the same reference clock signal into the digital-to-time converter and the replica digital-to-time converter simultaneously;

[0037] Using the output signal of the replica digital-to-time converter as an input signal of a ramp generator in the sampling phase detector, and using the sampling clock signal generated by processing the output signal of the digital-to-time converter by the sampling clock generating circuit as an input signal of a sampling circuit in the sampling phase detector;

[0038] Using the output signal of the sampling voltage monitoring circuit as the input signal of the voltage conversion rate calibration state machine;

[0039] The voltage slew rate of the sampling phase detector is calibrated based on the output signal of the voltage slew rate calibration state machine.

[0040] Compared with the prior art, the voltage conversion rate calibration circuit and method for a fractional-N frequency-sampling phase-locked loop circuit provided by the present invention can detect its voltage conversion rate by utilizing the existing hardware resources of the fractional-N frequency-sampling phase-locked loop circuit; in the detection of its voltage conversion rate, no additional design and other costs are incurred, and through the cooperation of other calibration modules or circuits (such as an automatic frequency calibration module, a range calibration module and a gain calibration module for a digital-to-time converter, a sampling voltage monitoring circuit, etc.) and a reasonable calibration process, the accuracy of the calibration can be effectively guaranteed.

[0041] To achieve the above and related ends, one or more aspects of the present invention include features that will be described in detail below and particularly pointed out in the claims. The following description and the accompanying drawings set forth certain exemplary aspects of the present invention in detail. However, these aspects are merely indicative of the various ways in which the principles of the present invention may be employed. Furthermore, the present invention is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] By referring to the following description and claims in conjunction with the accompanying drawings, and with a more complete understanding of the present invention, other objects and results of the present invention will become more apparent and readily understood. In the accompanying drawings:

[0043] Figure 1 A schematic diagram of a fractional-N frequency-sampling phase-locked loop circuit provided by an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of a voltage conversion rate calibration circuit for a fractional-N frequency-sampling phase-locked loop provided by an embodiment of the present invention;

[0045] Figure 3 A flowchart of a voltage conversion rate calibration method for a fractional-N frequency-sampling phase-locked loop provided by an embodiment of the present invention;

[0046] Figure 4 A schematic diagram of the range calibration principle of a digital-to-time converter provided by an embodiment of the present invention;

[0047] Figure 5 A schematic diagram of a voltage conversion rate calibration method for a fractional-N frequency-sampling phase-locked loop provided by an embodiment of the present invention;

[0048] Figure 6 A comparison diagram of various signals in a voltage conversion rate calibration method for a fractional-N frequency-sampling phase-locked loop provided by an embodiment of the present invention.

[0049] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0050] In the following description, for illustrative purposes, numerous specific details are set forth to provide a comprehensive understanding of one or more embodiments. However, it will be apparent that the embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate description of one or more embodiments.

[0051] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0052] The principle of the voltage conversion rate calibration circuit of the fractional-N frequency-sampling phase-locked loop circuit provided by the present invention is described in detail below with reference to the accompanying drawings. Figure 1 The principle of a fractional-N frequency-sampling phase-locked loop circuit provided by an embodiment of the present invention is shown. Figure 2 The principle of a voltage conversion rate calibration circuit for a fractional-N frequency-sampling phase-locked loop provided by an embodiment of the present invention is shown. Figure 3The flowchart of a voltage conversion rate calibration method for a fractional-N frequency-sampling phase-locked loop provided by an embodiment of the present invention is shown. Figure 4 The scope calibration principle of the digital-to-time converter provided by the embodiment of the present invention is shown. Figure 5 The principle of the voltage conversion rate calibration method of the fractional-N frequency-sampling phase-locked loop provided by the embodiment of the present invention is shown. Figure 6 The comparative relationship between various signals in the voltage conversion rate calibration method of the fractional-N frequency-sampling phase-locked loop provided by the embodiment of the present invention is shown.

[0053] Combine Figure 1 and Figure 2 It can be seen that the voltage conversion rate calibration circuit of the fractional-N frequency-sampling phase-locked loop circuit provided by the present invention includes a fractional-N frequency-sampling phase-locked loop circuit and a voltage conversion rate calibration state machine, wherein the fractional-N frequency-sampling phase-locked loop circuit includes a sampling phase detector, an oscillator, a sampling clock generation circuit and a digital-to-time converter; wherein,

[0054] The oscillator is used to generate an oscillation clock signal (DCLK). The reference clock signal (REF_CLK) is sequentially processed by the digital-to-time converter and the sampling clock generation circuit to form a two-phase sampling clock signal (including PH1 and PH2). The sampling phase detector is used to process the loop feedback clock signal (FB_CLK) converted from the oscillation clock signal and the sampling clock signal to generate a phase detection output signal. The voltage conversion rate calibration state machine is used to control the output voltage conversion rate of the sampling phase detector.

[0055] Furthermore, to realize the formation of the loop feedback clock signal, the fractional-N sampling phase-locked loop circuit further includes a multi-mode divider, which is used to process the oscillation clock signal and output the loop feedback clock signal (FB_CLK).

[0056] In a specific embodiment of the present invention, the sampling phase detector may include a ramp generator and a sampling circuit (a switched capacitor sampling circuit); wherein the ramp generator generates a ramp mainly from a resistor in a charging path, and the voltage conversion rate can be monotonically changed by changing the resistance value of the resistor.

[0057] Specifically, the input signal of the ramp generator includes the loop feedback clock signal DCLK output from the oscillator after passing through a multi-mode frequency divider. The input signal of the sampling circuit includes the sampling clock signal (which is the clock signal obtained by passing the reference clock signal through a digital-to-time converter and a sampling clock generation circuit). The output signal of the ramp generator is sampled by the sampling circuit to form the phase-detection output signal. The voltage conversion rate calibration state machine is used to control the output voltage conversion rate of the ramp generator.

[0058] Furthermore, a loop filter is provided between the output end of the sampling phase detector and the oscillator; wherein the phase detector output signal is used to control the frequency and phase of the oscillator after being processed by the loop filter; and when the fractional-N frequency-sampling phase-locked loop circuit is closed, the frequency and phase of the oscillator track the reference clock signal.

[0059] Furthermore, the fractional-N sampling phase-locked loop circuit provided by the present invention also includes a modulator (e.g., a ΔΣ modulator). Fractional frequency division in the fractional-N sampling phase-locked loop circuit is achieved by controlling the multi-mode frequency divider via the output of the frequency control word FCW after passing through the modulator. Furthermore, to minimize the impact of quantization noise on phase noise and fractional spurs caused by FCW passing through the ΔΣ modulator, phase compensation can be performed using a digital-to-time converter. Furthermore, to achieve optimal compensation, the digital-to-time converter typically requires a range and gain calibration module.

[0060] Specifically, the digital-to-time converter is equipped with a range calibration module and a gain calibration module. By setting the range calibration module and the gain calibration module, the digital-to-time converter can ideally complete phase compensation to offset the influence of quantization noise on phase noise or fractional spurious as much as possible.

[0061] More specifically, the oscillator is equipped with an automatic frequency calibration module, which can ensure that when the phase-locked loop operates in an open loop, the self-oscillation frequency of the oscillator is close to the target operating frequency when the loop is closed.

[0062] In addition, the fractional-N frequency-sampling phase-locked loop circuit provided by the present invention is further connected to a working status monitoring circuit (such as a sampling voltage monitoring circuit) at the output end of the sampling phase detector. The working status monitoring circuit can monitor in real time whether the sampling voltage exceeds the range of VL to VH.

[0063] It should be noted that by setting the various components in the fractional-N frequency-sampling phase-locked loop circuit provided by the present invention, it is possible to first obtain a more accurate clock frequency of DCLK on the basis of the above two existing calibration modules, and then use DCLK to complete the range calibration of the digital time converter, thereby obtaining a fine digital time conversion accuracy tdtc,res Under these conditions, the present invention can utilize the existing hardware resources of the fractional-N frequency-sampling phase-locked loop circuit to complete the voltage conversion rate calibration of the sampling phase detector.

[0064] It should be noted that Figure 2 It can be seen that the voltage conversion rate calibration circuit of the fractional-N frequency-sampling phase-locked loop provided by the present invention does not require complex additional hardware design costs, especially additional analog circuit design; the additional circuit is only the voltage conversion rate calibration state machine of the control circuit; that is, only a simple voltage conversion rate calibration state machine is needed, in conjunction with the existing calibration circuit of the fractional-N frequency-sampling phase-locked loop circuit, to complete the following. Figure 3 The process shown in FIG. 1 is used to calibrate the voltage conversion rate.

[0065] To further illustrate the working principle of a voltage conversion rate calibration circuit for a fractional-N frequency-sampling phase-locked loop provided by the present invention, the present invention also provides a voltage conversion rate calibration method for a fractional-N frequency-sampling phase-locked loop, which is implemented based on the voltage conversion rate calibration circuit of the fractional-N frequency-sampling phase-locked loop. Figure 3 As shown, the calibration method includes:

[0066] S110: Performing automatic frequency calibration on the oscillator through an automatic frequency calibration module;

[0067] S120: Performing range calibration on the digital-to-time converter by a range calibration module;

[0068] S130: Perform voltage slew rate calibration on the sampling phase detector based on the voltage slew rate calibration state machine.

[0069] In the present invention, according to Figure 3 After the process completes the oscillator automatic frequency calibration and the digital-to-time converter range calibration, the output of the digital-to-analog converter is copied to replace the output of the multi-mode divider as the input of the sampling phase detector, and the voltage conversion rate in the sampling phase detector is calibrated.

[0070] Specifically, if Figure 4 As shown, to implement range calibration of the digital-to-time converter, the range calibration module may include a replica digital-to-time converter and a digital-to-time converter range calibration state machine; and performing range calibration on the digital-to-time converter through the range calibration module further includes:

[0071] The same reference clock signal is inputted into the digital-to-time converter and the replica digital-to-time converter simultaneously; wherein the input codewords of the digital-to-time converter and the replica digital-to-time converter are a maximum converter code and a minimum converter code respectively;

[0072] Performing phase comparison between the output signal of the digital-to-time converter and the output signal of the replica digital-to-time converter after a set delay through the sampling phase detector;

[0073] generating a range control codeword for the digital-to-time converter based on a phase comparison result by the digital-to-time converter range calibration state machine;

[0074] The digital-to-time converter is range-calibrated using the range control codeword.

[0075] More specifically, in order to implement voltage slew rate calibration for the sampling phase detector, the voltage slew rate calibration for the sampling phase detector based on the voltage slew rate calibration state machine further includes:

[0076] Inputting the same reference clock signal into the digital-to-time converter and the replica digital-to-time converter simultaneously;

[0077] Using the output signal of the replica digital-to-time converter as an input signal of a ramp generator in the sampling phase detector, and using the sampling clock signal generated by processing the output signal of the digital-to-time converter by the sampling clock generating circuit as an input signal of a sampling circuit in the sampling phase detector;

[0078] Using the output signal of the sampling voltage monitoring circuit as the input signal of the voltage conversion rate calibration state machine;

[0079] The voltage slew rate of the sampling phase detector is calibrated based on the output signal of the voltage slew rate calibration state machine.

[0080] Furthermore, Figure 5 The main circuit connections involved in the voltage conversion rate calibration of the present invention are shown as follows: Figure 5 As shown, the inputs of the digital-to-time converter and the replica digital-to-time converter are the same reference clock. The output DTCRo of the replica digital-to-time converter serves as the input to the ramp generator in the sampling phase detector. In the sampling phase detector, the sampling clock is the clock signal PH1 / PH2 after the reference clock REF_CLK passes through the digital-to-time converter and the sampling clock generation circuit. The output IN_BOUND of the sampling voltage monitoring circuit serves as the input to the voltage slew rate calibration state machine. The voltage slew rate calibration state machine generates the output SR_CODE to control the resistor value in the ramp generator to achieve voltage slew rate calibration. The codeword of the replica digital-to-time converter is fixed at 0. When the codeword of the digital-to-time converter sweeps from 0, the output VSAMP of the sampling phase detector changes from high to low. In the sampling voltage detection circuit, VSAMP is the signal obtained by actually sampling Y1.

[0081] Figure 6 The following is the comparison of the main signals in voltage conversion rate calibration, such as Figure 6 As shown in the figure, by scanning the input codeword of the digital-to-time converter, the sampling edge offset of the sampling clock is generated. In this way, at different sampling times, the sampling phase detector will sample different voltage values ​​on the rising edge of the output Y1 after DTCRo passes through the ramp generator. When the sampling voltage VSAMP is between VH and VL, IN_BOUND is high, otherwise it is low. During the codeword scanning process, the voltage conversion rate calibration state machine records the codeword length corresponding to IN_BOUND=1 as D DTCr , using the calibrated digital time conversion accuracy t dtc,res Then the voltage conversion rate SR can be obtained as:

[0082]

[0083] Based on the detected voltage conversion rate and the monotonic change relationship between resistance and voltage conversion rate, the voltage conversion rate calibration codeword SR_CODE can be adjusted accordingly to change the resistance to obtain the required voltage conversion rate and complete the calibration.

[0084] The voltage slew rate calibration circuit and method for a fractional-N sampling phase-locked loop circuit according to the present invention have been described above by way of example with reference to the accompanying drawings. However, those skilled in the art will appreciate that various improvements may be made to the voltage slew rate calibration circuit and method for a fractional-N sampling phase-locked loop circuit proposed above without departing from the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the contents of the appended claims.

Claims

1. A voltage slew rate calibration circuit for a fractional-N sampling phase-locked loop, characterized in that: It includes a fractional-N frequency-sampling phase-locked loop circuit and a voltage conversion rate calibration state machine, wherein the fractional-N frequency-sampling phase-locked loop circuit includes a sampling phase detector, an oscillator, a sampling clock generation circuit and a digital-to-time converter; wherein, The oscillator is used to generate an oscillation clock signal; The reference clock signal is processed by the digital-to-time converter and the sampling clock generating circuit in sequence to form a sampling clock signal; The sampling phase detector is used to process the loop feedback clock signal converted from the oscillation clock signal and the sampling clock signal, and generate a phase detection output signal; The voltage conversion rate calibration state machine is used to control the output voltage conversion rate of the sampling phase detector; wherein, The digital-to-time converter is equipped with a range calibration module, which includes a replica digital-to-time converter and a digital-to-time converter range calibration state machine. The sampling phase detector is also used to perform a phase comparison between the output signal of the digital-to-time converter and the output signal of the replica digital-to-time converter after a set delay. The digital-to-time converter range calibration state machine generates a range control codeword for the digital-to-time converter based on the phase comparison result. The range control codeword is used to perform range calibration on the digital-to-time converter.

2. The voltage conversion rate calibration circuit of a fractional-N sampling phase-locked loop according to claim 1, wherein: The fractional-N frequency-sampling phase-locked loop circuit further includes a multi-mode frequency divider; and The multi-mode frequency divider is used to process the oscillation clock signal and output the loop feedback clock signal.

3. The voltage conversion rate calibration circuit of a fractional-N sampling phase-locked loop according to claim 2, wherein: The fractional-N sampling phase-locked loop circuit further includes a modulator; and The fractional frequency division of the fractional-N frequency-sampling phase-locked loop circuit is achieved by controlling the multi-mode frequency divider through the output of the frequency control word after passing through the modulator.

4. The voltage conversion rate calibration circuit of a fractional-N sampling phase-locked loop according to claim 3, wherein: The sampling phase detector includes a ramp generator and a sampling circuit; wherein, The input signal of the ramp generator includes the loop feedback clock signal, the input signal of the sampling circuit includes the sampling clock signal, and the output signal of the ramp generator is sampled by the sampling circuit to form the phase detection output signal; and The voltage slew rate calibration state machine is used to control the output voltage slew rate of the ramp generator.

5. The voltage conversion rate calibration circuit of a fractional-N sampling phase-locked loop according to claim 4, wherein: A loop filter is provided between the output end of the sampling phase detector and the oscillator; wherein, The phase detection output signal is used to control the frequency and phase of the oscillator after being processed by the loop filter; and When the fractional-N sampling phase-locked loop circuit is closed, the frequency and phase of the oscillator track the reference clock signal.

6. The voltage conversion rate calibration circuit of a fractional-N sampling phase-locked loop according to claim 5, wherein: The oscillator is equipped with an automatic frequency calibration module; The digital-to-time converter is further configured with a gain calibration module.

7. The voltage conversion rate calibration circuit of a fractional-N sampling phase-locked loop according to claim 6, wherein: The output end of the sampling phase detector is connected with a sampling voltage monitoring circuit.

8. A method for calibrating the voltage conversion rate of a fractional-N sampling phase-locked loop, characterized in that: Based on the voltage conversion rate calibration circuit of the fractional-N frequency sampling phase-locked loop according to claim 7, the calibration method includes: S110: Performing automatic frequency calibration on the oscillator through an automatic frequency calibration module; S120: Performing range calibration on the digital-to-time converter by a range calibration module; S130: Perform voltage slew rate calibration on the sampling phase detector based on the voltage slew rate calibration state machine.

9. The voltage conversion rate calibration method of a fractional-N sampling phase-locked loop according to claim 8, wherein: The range calibration module includes a replica digital-to-time converter and a digital-to-time converter range calibration state machine; and performing range calibration on the digital-to-time converter by the range calibration module includes: The same reference clock signal is inputted into the digital-to-time converter and the replica digital-to-time converter simultaneously; wherein the input codewords of the digital-to-time converter and the replica digital-to-time converter are a maximum converter code and a minimum converter code respectively; Performing phase comparison between the output signal of the digital-to-time converter and the output signal of the replica digital-to-time converter after a set delay through the sampling phase detector; generating a range control codeword for the digital-to-time converter based on the phase comparison result by the digital-to-time converter range calibration state machine; The digital-to-time converter is range-calibrated using the range control codeword.

10. The voltage conversion rate calibration method of a fractional-N sampling phase-locked loop according to claim 9, wherein: The performing voltage slew rate calibration on the sampling phase detector based on the voltage slew rate calibration state machine includes: Inputting the same reference clock signal into the digital-to-time converter and the replica digital-to-time converter simultaneously; Using the output signal of the replica digital-to-time converter as an input signal of a ramp generator in the sampling phase detector, and using the sampling clock signal generated by processing the output signal of the digital-to-time converter by the sampling clock generating circuit as an input signal of a sampling circuit in the sampling phase detector; Using the output signal of the sampling voltage monitoring circuit as the input signal of the voltage conversion rate calibration state machine; The voltage slew rate of the sampling phase detector is calibrated based on the output signal of the voltage slew rate calibration state machine.

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