Sigma-delta modulation circuit and high-precision temperature sensor

Abstract

The invention provides a sigma-delta modulation circuit and a high-precision temperature sensor. The sigma-delta modulation circuit comprises a two-phase non-overlapping clock, a first switched capacitor integrating circuit, a second switched capacitor integrating circuit, a quantizer and a digital-analog conversion module. The two-phase non-overlapping clock provides a driving signal; the first switched capacitor integrating circuit performs integration processing on the analog detection voltage and outputs a first differential voltage; the second switched capacitor integrating circuit performs integration processing on the first differential voltage and outputs a second differential voltage; the quantizer converts the second differential voltage into a modulation signal; the digital-to-analog conversion module converts the modulation signal into a feedback voltage; and the switching circuit is used for switching the working states of the first switched capacitor integrating circuit and the second switched capacitor integrating circuit. When a temperature signal is in a low frequency band, the first switched capacitor integrating circuit and the second switched capacitor integrating circuit are used to form a second-order one-bit CIFB topological structure, noise is pushed to a high frequency band, the signal-to-noise ratio of the low frequency band is improved, and high-precision temperature detection is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of sensors, and particularly relates to a sigma-delta modulation circuit and a high-precision temperature sensor. Background Art

[0002] Temperature is an important factor affecting the normal operation of a chip. Temperature is generally a low-frequency signal with relatively slow changes, and noise is usually distributed in the low-frequency band and is easily mixed into the temperature signal frequency band.

[0003] ADCs can be divided into Nyquist-type ADCs and oversampling-type ADCs. The Nyquist-type ADC can achieve a rate of GHz, but has obvious disadvantages such as complex structure, high power consumption, and high cost. As the semiconductor feature size continues to shrink, it is more difficult to achieve good matching between devices, and it is difficult to achieve high-precision purposes. Summary of the Invention

[0004] The main purpose of the present invention is to provide a sigma-delta modulation circuit and a high-precision temperature sensor, aiming to propose a method for achieving high-precision detection of temperature.

[0005] To achieve the above object, the sigma-delta modulation circuit proposed by the present invention includes: a two-phase non-overlapping clock, a first switched-capacitor integration circuit, a second switched-capacitor integration circuit, a quantizer, and a digital-to-analog conversion module;

[0006] The input end of the first switched-capacitor integration circuit is connected to an analog detection voltage, and the output end is connected to the input end of the second switched-capacitor integration circuit; the output end of the second switched-capacitor integration circuit is connected to the quantizer; the input end of the digital-to-analog conversion module is connected to the output end of the quantizer, and the output end is connected to the input ends of the first switched-capacitor integration circuit and the second switched-capacitor integration circuit;

[0007] The two-phase non-overlapping clock is used to provide a driving signal;

[0008] The first switched-capacitor integration circuit is used to sample and hold the analog detection voltage, and perform an integration process on the analog detection voltage, and output a first differential voltage after the integration process; the second switched-capacitor integration circuit is used to sample and hold the first differential voltage, and perform an integration process on the first differential voltage, and output a second differential voltage to the quantizer;

[0009] The quantizer is used to convert the second differential voltage into a modulation signal containing temperature information;

[0010] The digital-to-analog conversion module is configured to convert the modulation signal into a corresponding feedback voltage and output it to the first switched-capacitor integrating circuit and the second switched-capacitor integrating circuit;

[0011] A switching circuit is disposed in the first switched-capacitor integrating circuit and the second switched-capacitor integrating circuit. Controlled by the driving signal, the switching circuit is configured to switch the first switched-capacitor integrating circuit to sample the analog detection voltage or integrate the analog detection voltage, and switch the second switched-capacitor integrating circuit to integrate the first differential voltage or sample the first differential voltage.

[0012] Optionally, the digital-to-analog conversion module includes: a first switching device;

[0013] The controlled terminal of the first switching device is connected to the output terminal of the quantizer. The first terminal is connected to a first voltage, the second terminal is grounded and connected to the input terminals of the first switched-capacitor integrating circuit and the second switched-capacitor integrating circuit;

[0014] The first switching device is configured to output a first voltage to the input terminal of the first switched-capacitor integrating circuit and the second switched-capacitor integrating circuit when the voltage value of the modulation signal is greater than a preset conduction voltage value.

[0015] Optionally, the first switched-capacitor integrating circuit includes: a first switching circuit, a second switching circuit, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a first operational amplifier;

[0016] The first terminal of the first switching circuit is connected to the analog detection voltage, the second terminal is connected to the first terminal of the first capacitor, and the third terminal is connected to the first terminal of the second capacitor. The first terminal of the second switching circuit is connected to the second terminal of the first capacitor, the second terminal is connected to the second terminal of the second capacitor, the third terminal is connected to a second voltage, the fourth terminal is connected to the first terminal of the third capacitor and the first input terminal of the first operational amplifier, and the fifth terminal is connected to the first terminal of the fourth capacitor and the second input terminal of the first operational amplifier. The first output terminal of the first operational amplifier is connected to the second terminal of the third capacitor and the first input terminal of the second switched-capacitor integrating circuit, and the second output terminal is connected to the second terminal of the fourth capacitor and the second input terminal of the second switched-capacitor integrating circuit;

[0017] The two-phase non-overlapping clock connects the first switching circuit and the second switching circuit; the two-phase non-overlapping clock generates a first driving signal and a second driving signal; the first switching circuit is configured to conduct a path between the first end and the third end of the first switching circuit under the control of the first driving signal; the second switching circuit is configured to conduct a path between the first end and the third end of the second switching circuit and conduct a path between the second end and the third end of the second switching circuit under the control of the first driving signal;

[0018] The first switching circuit is further configured to conduct a path between the first end and the second end of the first switching circuit under the control of the second driving signal; the second switching circuit is further configured to conduct a path between the first end and the fourth end of the second switching circuit and conduct a path between the second end and the fifth end of the second switching circuit under the control of the second driving signal.

[0019] Optionally, the second switched-capacitor integrating circuit includes: a third switching circuit, a fourth switching circuit, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, and a second operational amplifier;

[0020] The input end of the third switching circuit is connected to the output end of the first switched-capacitor integrating circuit, the second end is connected to the first end of the fifth capacitor, and the third end is connected to the first end of the sixth capacitor; the first end of the fourth switching circuit is connected to the second end of the fifth capacitor, the second end is connected to the second end of the sixth capacitor, the third end is connected to a second voltage, the fourth end is connected to the first end of the seventh capacitor and the first input end of the second operational amplifier, and the fifth end is connected to the first end of the eighth capacitor and the second input end of the second operational amplifier; the first output end of the second operational amplifier is connected to the second end of the seventh capacitor and the first input end of the quantizer, and the second output end is connected to the second end of the eighth capacitor and the second input end of the quantizer;

[0021] The two-phase non-overlapping clock connects the third switching circuit and the fourth switching circuit; the two-phase non-overlapping clock generates a first driving signal and a second driving signal; the third switching circuit is configured to short-circuit a path between the second end and the third end of the third switching circuit under the control of the first driving signal; the fourth switching circuit is configured to conduct a path between the first end and the fourth end of the fourth switching circuit and conduct a path between the second end and the fifth end of the fourth switching circuit under the control of the first driving signal;

[0022] The third switching circuit is further configured to, under the control of the second driving signal, conduct the path between the input end of the third switching circuit and the first end of the fifth capacitor, and conduct the path between the input end of the third switching circuit and the first end of the sixth capacitor; the fourth switching circuit is further configured to, under the control of the second driving signal, conduct the path between the first end and the third end of the fourth switching circuit, and conduct the path between the second end and the third end of the fourth switching circuit.

[0023] Optionally, the first operational amplifier or the second operational amplifier is composed of a two-stage structure, the first stage structure is a cascode structure, and the second stage structure is a common-source amplifier structure.

[0024] Optionally, the cascode structure includes: a first resistor, a first to seventeenth NMOS transistor, and a first to eighth PMOS transistor;

[0025] The gates of the first to fourth NMOS transistors are connected to each other, the sources of the first to fourth NMOS transistors are connected to each other, the source of the fifth NMOS transistor, the source of the sixth NMOS transistor, and the drain of the first MOS transistor are connected, the drain of the fifth NMOS is connected to the source of the twelfth NMOS transistor, the drain of the sixth NMOS is connected to the source of the thirteenth NMOS transistor, the source of the seventh NMOS transistor, the source of the eighth NMOS transistor, and the drain of the second MOS transistor are connected, and the drains of the seventh NMOS and the eighth NMOS are connected to the source of the fourteenth NMOS transistor; the drain of the third NMOS transistor is connected to the source of the ninth NMOS transistor and the first end of the first resistor, the drain of the ninth NMOS transistor is connected to the source of the fifteenth NMOS transistor, the sources of the tenth NMOS transistor, the eleventh NMOS transistor, the drain of the fourth NMOS transistor, and the second end of the first resistor are connected, the gates of the tenth NMOS transistor and the eleventh NMOS transistor are connected to the common-mode setting output voltage, the gate of the ninth NMOS transistor is connected to the common-mode feedback voltage, the drain of the tenth NMOS transistor is connected to the source of the sixteenth NMOS transistor, and the drain of the eleventh NMOS transistor is connected to the source of the seventeenth NMOS transistor; the gates of the fifth NMOS transistor and the seventh NMOS transistor are connected to the positive-phase input end of the operational amplifier, and the gates of the sixth NMOS transistor and the eighth NMOS transistor are connected to the negative-phase input end of the operational amplifier; the gates of the twelfth to seventeenth NMOS transistors are connected to each other;

[0026] The drain of the fourteenth NMOS transistor is connected to the source of the first PMOS transistor, the gates of the fifth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor. The drain of the first PMOS transistor is connected to the source of the fifth PMOS transistor. The drain of the fifteenth NMOS transistor is connected to the gate of the second PMOS transistor, the source of the second PMOS transistor, and the gate of the sixth PMOS transistor. The drain of the second PMOS transistor is connected to the source of the sixth PMOS transistor. The drains of the twelfth NMOS transistor, the sixteenth NMOS transistor, the source of the third PMOS transistor, and the first end of the common-source amplifier circuit are connected. The drains of the thirteenth NMOS transistor, the seventeenth NMOS transistor, the source of the fourth PMOS transistor, and the second end of the common-source amplifier circuit are connected. The drain of the third PMOS transistor, the source of the seventh PMOS transistor, and the third end of the common-source amplifier circuit are connected. The drain of the fourth PMOS transistor, the source of the eighth PMOS transistor, and the fourth end of the common-source amplifier circuit are connected.

[0027] The gates of the twelfth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, and the seventeenth NMOS transistor are connected to each other. The gates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are connected to each other. The drains of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor are connected to each other.

[0028] Optionally, the common-source amplification structure includes: the second to third resistors, the eleventh to fourteenth capacitors, the eighteenth to nineteenth NMOS transistors, and the ninth to tenth PMOS transistors;

[0029] The gates of the eighteenth NMOS transistor and the nineteenth NMOS transistor are connected. The sources of the eighteenth NMOS transistor, the nineteenth NMOS transistor, and the source of the first NMOS transistor are connected. The drain of the eighteenth NMOS transistor is connected to the source of the ninth PMOS transistor. The second resistor and the eleventh capacitor are connected in parallel and disposed between the drain of the eighteenth NMOS transistor and the gate of the ninth NMOS transistor. The drain of the nineteenth NMOS transistor is connected to the source of the tenth PMOS transistor. The third resistor and the twelfth capacitor are connected in parallel and disposed between the drain of the nineteenth NMOS transistor and the gate of the ninth NMOS transistor. One end of the thirteenth capacitor is connected to the drain of the third PMOS transistor, and the other end is connected to the drain of the eighteenth NMOS transistor. One end of the fourteenth capacitor is connected to the drain of the fourth PMOS transistor, and the other end is connected to the drain of the nineteenth NMOS transistor. The gate of the ninth PMOS transistor is connected to the source of the third PMOS transistor. The gate of the tenth PMOS transistor is connected to the source of the fourth PMOS transistor. The drains of the ninth PMOS transistor, the tenth PMOS transistor, and the fifth PMOS transistor are connected.

[0030] Optionally, the quantizer includes: a preamplifier, a dynamic comparator, and a latch;

[0031] The input end of the preamplifier is connected to the output end of the second switched-capacitor integrating circuit, and the output end is connected to the input end of the dynamic comparator; the clock terminal of the dynamic comparator accesses a clock signal, and the output end is connected to the latch;

[0032] The preamplifier is used to reduce kickback noise and outputs the second differential voltage after amplifying it by a first multiple;

[0033] The dynamic comparator is used to compare the voltage at the output end of the preamplifier with a reference voltage when the clock signal is valid, and output a level signal to the latch according to the comparison result; the latch is used to latch and hold the level signal.

[0034] The present invention also provides a high-precision temperature sensor, which includes a temperature detection circuit, a counter, and the sigma-delta modulation circuit;

[0035] The output end of the temperature detection circuit is connected to the input end of the first switched-capacitor integrating circuit, and the output end of the quantizer is connected to the counter;

[0036] The temperature detection circuit is used to convert the detected temperature value into an analog detection voltage and output it to the input end of the first switched-capacitor integrating circuit;

[0037] The counter is used to sample and count the modulation signal, and convert the pulse density information in the modulation signal into a corresponding digital quantity.

[0038] Optionally, the counter includes: an AND gate circuit, and a register bank formed by a plurality of registers connected in series;

[0039] The first input end of the AND gate circuit accesses a clock signal, and the second input end is connected to the output end of the quantizer; the clock terminal of the first-stage register is connected to the output end of the AND gate circuit; the output end of the previous-stage register is connected to the clock terminal of the next-stage register and the data terminal of the previous-stage register.

[0040] The present invention provides a sigma-delta modulation circuit and a high-precision temperature sensor. The sigma-delta modulation circuit includes: a two-phase non-overlapping clock, a first switched-capacitor integration circuit, a second switched-capacitor integration circuit, a quantizer, and a digital-to-analog conversion module. The input end of the first switched-capacitor integration circuit is connected to an analog detection voltage, and the output end is connected to the input end of the second switched-capacitor integration circuit. The output end of the second switched-capacitor integration circuit is connected to the quantizer. The input end of the digital-to-analog conversion module is connected to the output end of the quantizer, and the output end is connected to the input ends of the first switched-capacitor integration circuit and the second switched-capacitor integration circuit. The two-phase non-overlapping clock is used to provide a driving signal. The first switched-capacitor integration circuit is used to sample and hold the analog detection voltage, and perform an integration process on the analog detection voltage, and output a first differential voltage after the integration process. The second switched-capacitor integration circuit is used to sample and hold the first differential voltage, and perform an integration process on the first differential voltage, and output a second differential voltage to the quantizer. The quantizer is used to convert the second differential voltage into a modulation signal containing temperature information. The digital-to-analog conversion module is used to convert the modulation signal into a corresponding feedback voltage and output it to the first switched-capacitor integration circuit and the second switched-capacitor integration circuit. A switching circuit is provided in the first switched-capacitor integration circuit and the second switched-capacitor integration circuit, and is controlled by the driving signal, and is used to switch the first switched-capacitor integration circuit to sample the analog detection voltage or perform an integration process on the analog detection voltage, and switch the second switched-capacitor integration circuit to perform an integration process on the first differential voltage or sample the first differential voltage. The temperature signal is in the low-frequency band. The present invention uses the first switched-capacitor integration circuit and the second switched-capacitor integration circuit to form a second-order one-bit CIFB topology structure, and pushes the noise to the high-frequency band through noise shaping, improves the signal-to-noise ratio in the low-frequency band, matches the application scenario of the temperature sensor, and realizes high-precision temperature detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the structures shown in these drawings without creative efforts.

[0042] Figure 1 FIG. is a schematic structural diagram of an embodiment of the sigma-delta modulation circuit of the present invention;

[0043] Figure 2Schematic diagram of the circuit structure of a second-order one-bit CIFB structure modulator in an embodiment of the sigma-delta modulation circuit of the present invention;

[0044] Figure 3 Schematic diagram of the timing of the two-phase non-overlapping clock output signal in an embodiment of the sigma-delta modulation circuit of the present invention;

[0045] Figure 4 Simulation result diagram of the effective number of bits of the sigma-delta modulation circuit in an embodiment of the sigma-delta modulation circuit of the present invention;

[0046] Figure 5 Schematic diagram of the circuit structure of the operational amplifier in an embodiment of the sigma-delta modulation circuit of the present invention;

[0047] Figure 6 Schematic diagram of the circuit structure of the quantizer in an embodiment of the sigma-delta modulation circuit of the present invention;

[0048] Figure 7 Block diagram of a solution in an embodiment of the high-precision temperature sensor of the present invention;

[0049] Figure 8 Circuit structure diagram of the temperature sensing circuit in an embodiment of the high-precision temperature sensor of the present invention;

[0050] Figure 9 Circuit structure diagram of the counter in an embodiment of the high-precision temperature sensor of the present invention;

[0051] Figure 10 Simulation result diagram of the counter in an embodiment of the high-precision temperature sensor of the present invention;

[0052] Figure 11 Temperature simulation diagram of the temperature detection circuit in an embodiment of the high-precision temperature sensor of the present invention.

[0053] Explanation of the reference numerals in the drawings:

[0054]

[0055]

[0056] The realization, functional features and advantages of the object of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0057] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0058] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative position relationship, movement conditions, etc. between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0059] In the present invention, unless otherwise clearly defined and limited, terms such as "connection" and "fixation" should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can be the internal connection of two components or the interaction relationship between two components, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] In addition, in the present invention, descriptions such as "first" and "second" are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0061] Refer to Figure 1 , the present invention provides a sigma-delta modulation circuit, and the sigma-delta modulation circuit includes: a two-phase non-overlapping clock 30, a first switched-capacitor integration circuit 10, a second switched-capacitor integration circuit 20, a quantizer 40, and a digital-to-analog conversion module 50;

[0062] The input end of the first switched-capacitor integrating circuit 10 is connected to an analog detection voltage, and the output end is connected to the input end of the second switched-capacitor integrating circuit 20; the output end of the second switched-capacitor integrating circuit 20 is connected to the quantizer 40; the input end of the digital-to-analog conversion module 50 is connected to the output end of the quantizer 40, and the output end is connected to the input end of the first switched-capacitor integrating circuit 10 and the input end of the second switched-capacitor integrating circuit 20;

[0063] The two-phase non-overlapping clock 30 is used to provide a driving signal;

[0064] The first switched-capacitor integrating circuit 10 is used to sample and hold the analog detection voltage, and perform an integration process on the analog detection voltage, and output a first differential voltage after the integration process; the second switched-capacitor integrating circuit 20 is used to sample and hold the first differential voltage, and perform an integration process on the first differential voltage, and output a second differential voltage to the quantizer 40;

[0065] The quantizer 40 is used to convert the second differential voltage into a modulation signal containing temperature information;

[0066] The digital-to-analog conversion module 50 is used to convert the modulation signal into a corresponding feedback voltage and output it to the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20;

[0067] The switching circuit is arranged in the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20, and is controlled by the driving signal, and is used to switch the first switched-capacitor integrating circuit 10 to sample the analog detection voltage or perform an integration process on the analog detection voltage, and switch the second switched-capacitor integrating circuit 20 to perform an integration process on the first differential voltage or sample the first differential voltage.

[0068] It should be noted that the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20 form a second-order one-bit CIFB topology. The first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20 include a switching circuit. It should be noted that the input end of the first switched-capacitor integrating circuit 10 is connected to an analog detection voltage, and the analog detection voltage is related to temperature. In particular, the analog detection voltage is an analog voltage quantity output by a temperature detection circuit and linearly related to temperature change.

[0069] The first switched-capacitor integrating circuit 10 is configured to sample and hold the analog detection voltage and perform an integration process on the analog detection voltage. It should be noted that the first switched-capacitor integrating circuit 10 has two operating states. One is to sample and hold the analog detection voltage, and the other is to perform an integration process on the analog detection voltage and output a first differential voltage to the second switched-capacitor integrating circuit 20 after the integration process. At any given time point, the two operating states do not overlap. Similarly, the second switched-capacitor integrating circuit 20 is configured to sample and hold the first differential voltage, perform an integration process on the first differential voltage, and output a second differential voltage to the quantizer 40. The second switched-capacitor integrating circuit 20 is configured to sample and hold the first differential voltage, perform an integration process on the first differential voltage, and output a second differential voltage to the quantizer 40. Similarly, the second switched-capacitor integrating circuit 20 also has two operating states. One is to sample and hold the first differential voltage, and the other is to perform an integration process on the first differential voltage and output a second differential voltage to the quantizer 40 after the integration process.

[0070] The quantizer 40 is configured to convert the second differential voltage into a modulation signal containing temperature information. It should be noted that the quantizer 40 is responsible for discretizing the analog signal into a digital signal. The quantizer 40 can be a low-resolution ADC, and the modulation signal output by the quantizer 40 can be a pulse density modulation signal, i.e., a one-bit binary code stream. The quantizer 40 converts the second differential voltage into a modulation signal containing temperature information for subsequent processing; the modulation signal is a digital signal.

[0071] The switch circuit is disposed in the first capacitor C1 integrating circuit and the second switched-capacitor integrating circuit 20, and is controlled by the driving signals output by the two-phase non-overlapping clock 30, and is used to switch the working states of the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20. It should be noted that temperature is an important factor affecting the normal operation of the chip. Temperature is generally a low-frequency signal with relatively slow changes, and noise (such as quantization noise and 1 / f noise) is usually easily mixed into the temperature signal frequency band in the low-frequency band, reducing the signal-to-noise ratio. In order to achieve high-precision temperature detection, it is necessary to improve the signal-to-noise ratio in the low-frequency band. The first capacitor C1 integrating circuit and the second switched-capacitor integrating circuit 20 push the low-frequency noise to the high-frequency band, realizing a significant attenuation of the noise power in the low-frequency band; the high-frequency noise can be filtered by the digital decimation filter in the temperature sensor, thereby improving the signal-to-noise ratio in the low-frequency band (temperature signal frequency band). Specifically, the digital-to-analog conversion module 50 converts the modulation signal output by the quantizer 40 into an analog signal, and feeds it back to the input ends of the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20 respectively. Among them, the analog signal is subtracted from the analog detection voltage signal to generate a first error signal; the first switched-capacitor integrating circuit 10 integrates the first error signal to initially realize noise shaping; the analog signal is subtracted from the first differential voltage to generate a second error signal; the second switched-capacitor integrating circuit 20 integrates the second error signal to further enhance the noise shaping effect.

[0072] Specifically, the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20 realize noise shaping through integration operations. In particular, the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20 may include integrators, and the transfer function of the integrator is which shows high gain in the low-frequency band and low gain in the high-frequency band in the frequency domain. In the Sigma-delta modulation circuit proposed in the present invention, the transfer function of the quantization noise is NTF(z) = 1 - H(z) = z -1 . This indicates that the noise is shaped by the high-pass characteristics of the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20, the low-frequency noise is suppressed, and the high-frequency noise is amplified. Since the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20 exist in a cascaded manner in the present invention. This means that the quantization noise decays at a slope of 40 dB / decade in the low-frequency band and is significantly amplified in the high-frequency band. In addition, both the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20 are fully differential structures, which can cancel common-mode noise (such as power supply noise and thermal noise), reduce the input offset voltage, and improve the system linearity. In addition, the integrators in the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20 accumulate the error signals to ensure the stability of the system.

[0073] Reference Figure 2 , the two-phase non-overlapping clock 30 provides drive signals for controlling the switching circuit to switch the operating states of the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20. It should be noted that the two-phase non-overlapping clock 30 (Two-Phase Non-Overlapping Clock) is a specially designed pair of clock signals. Its core feature is that the active levels (such as high levels) of two clock signals with the same frequency are completely staggered on the time axis, and there is a certain time interval between them (i.e., the "non-overlapping region"). It is easy to understand that the two-phase non-overlapping clock 30 outputs at least non-overlapping first drive signal and second drive signal. The first drive signal and the second drive signal can respectively correspond to the combined forms of the operating states of the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20.

[0074] It is easy to understand that the operating states of the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20 are controlled by the switching circuit. The first drive signal and the second drive signal output by the two-phase non-overlapping clock 30 can ensure that at the same moment, when the first switched-capacitor integrating circuit 10 performs integration processing on the held analog detection circuit and outputs the first differential voltage, the second switched-capacitor integrating circuit 20 samples and holds the first differential voltage; or when the first switched-capacitor integrating circuit 10 samples and holds the analog detection voltage, the second switched-capacitor integrating circuit 20 performs integration processing on the first differential voltage.

[0075] It should be noted that the sigma-delta modulation circuit proposed in the present invention is applied to a temperature sensor, and the temperature sensor further includes a counter; the quantizer 40 outputs a digital modulation signal so that the counter counts the pulse density modulation signal and converts the density information into a digital value to achieve digital demodulation. In addition, it should be noted that the counter actually performs low-pass filtering on the pulse density modulation signal by performing long-term counting on the pulse density modulation signal, for example: 4096 samplings, to filter out high-frequency noise and improve the signal-to-noise ratio in the low-frequency band.

[0076] In the first embodiment of the present invention, the digital-to-analog conversion module 50 includes: a first switching device;

[0077] The controlled end of the first switching device is connected to the output end of the quantizer 40, the first end is connected to a first voltage, the second end is grounded and connected to the input ends of the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20;

[0078] The first switching device is configured to output a first voltage to an input end of the first switched-capacitor integrating circuit 10 when a voltage value of the modulation signal is greater than a preset conduction voltage value.

[0079] It should be noted that the digital-to-analog conversion module 50 converts the modulation signal output by the quantizer 40 back into an analog signal and feeds it back to the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20. It is easy to understand that the modulation signal is a 1-bit digital signal; correspondingly, the digital-to-analog conversion module 50 only needs to generate two levels. In the first embodiment, a first end of the first switching device is connected to a first voltage, and is also connected to input ends of the first switched-capacitor integrating circuit 10 and the second switched-capacitor integrating circuit 20, and a second end is grounded. When the output of the quantizer 40 is 1, the first switching device is turned on, and the digital-to-analog conversion module 50 outputs the first voltage for feedback; when the output of the quantizer 40 is 0, the first switching device is turned off, and the digital-to-analog conversion module 50 outputs a 0 potential for feedback.

[0080] It should be noted that compared with a multi-bit digital-to-analog converter, the circuit structure of a 1-bit DAC is very simple and the cost is low. The first switching device can be a MOS transistor. The switching operation power consumption of the MOS transistor is relatively low, which is suitable for reducing power consumption; the switching speed of the MOS transistor is fast and the response time is short, which can meet the high-frequency feedback requirements of the Sigma-delta modulator.

[0081] The preset conduction voltage can be a conduction voltage value of the first switching device.

[0082] In a second embodiment of the present invention, the first switched-capacitor integrating circuit 10 includes: a first switching circuit 110, a second switching circuit 120, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a first operational amplifier OPA1;

[0083] A first end of the first switching circuit 110 is connected to the analog detection voltage, a second end is connected to a first end of the first capacitor C1, and a third end is connected to a first end of the second capacitor C2; a first end of the second switching circuit 120 is connected to a second end of the first capacitor C1, a second end is connected to a second end of the second capacitor C2, a third end is connected to a second voltage, a fourth end is connected to a first end of the third capacitor C3 and a first input end of the first operational amplifier OPA1, and a fifth end is connected to a first end of the fourth capacitor C4 and a second input end of the first operational amplifier OPA1; a first output end of the first operational amplifier OPA1 is connected to a second end of the third capacitor C3 and a first input end of the second switched-capacitor integrating circuit 20, and a second output end is connected to a second end of the fourth capacitor C4 and a second input end of the second switched-capacitor integrating circuit 20;

[0084] The two-phase non-overlapping clock 30 is connected to the first switching circuit 110 and the second switching circuit 120; the two-phase non-overlapping clock 30 generates a first driving signal and a second driving signal; the first switching circuit 110 is configured to conduct a path between a first end and a third end of the first switching circuit 110 under the control of the first driving signal; the second switching circuit 120 is configured to conduct a path between a first end and a third end of the second switching circuit 120 and conduct a path between a second end and a third end of the second switching circuit 120 under the control of the first driving signal;

[0085] The first switching circuit 110 is further configured to conduct a path between a first end and a second end of the first switching circuit 110 under the control of the second driving signal; the second switching circuit 120 is further configured to conduct a path between a first end and a fourth end of the second switching circuit 120 and conduct a path between a second end and a fifth end of the second switching circuit 120 under the control of the second driving signal.

[0086] Refer to Figure 2 , it should be noted that the operation of the first switched-capacitor integration circuit 10 is divided into two stages: a sampling stage and an integration stage, which are completed by controlling the first switching circuit 110 and the second switching circuit 120 with the two-phase non-overlapping clock 30. The first capacitor C1 and the second capacitor C2 are sampling capacitors for sampling the input signal; the third capacitor C3 and the fourth capacitor C4 are integration capacitors for storing and accumulating charges to implement the integration function. In the sampling stage, the two-phase non-overlapping clock 30 outputs the first driving signal to the first switching circuit 110 and the second switching circuit 120; the first switching circuit 110 conducts the path between the first end and the third end of the first switching circuit 110; the second switching circuit 120 conducts the path between the first end and the third end of the second switching circuit 120 and conducts the path between the second end and the third end of the second switching circuit 120; the first capacitor C1 and the second capacitor C2 start to store charges. Taking the second capacitor C2 as an example, the charge value on the second capacitor C2 is Q C2= C2 * ΔV, where ΔV is the simulated detection voltage. During the integration phase, the two-phase non-overlapping clock 30 outputs a second driving signal to the first switching circuit 110 and the second switching circuit 120; the first switching circuit 110 conducts the path between the first end and the second end of the first switching circuit 110; the second switching circuit 120 conducts the path between the first end and the fourth end of the second switching circuit 120, and conducts the path between the second end and the fifth end of the second switching circuit 120. That is, the channels for the second voltage to enter the first capacitor C1 and the second capacitor C2 are closed, the channel between the first capacitor C1 and the third capacitor C3 is conducted, and the channel between the second capacitor C2 and the fourth capacitor C4 is conducted; during the integration phase, the charge on the first capacitor C1 is transferred to the third capacitor C3, the charge on the second capacitor C2 is transferred to the fourth capacitor C4, and the output voltage of the first operational amplifier OPA1 gradually increases as the charge is transferred.

[0087] It should be noted that the input stage of the first operational amplifier OPA1 requires a stable bias voltage to ensure operation in the linear region; the second voltage is used as the bias voltage; the first voltage value can be twice the second voltage value; the second voltage value can be obtained from the first voltage value through a resistor voltage divider circuit. The first power supply terminal of the first operational amplifier OPA1 is connected to the first voltage, and the second power supply terminal is connected to the ground. Using the second voltage value as the bias voltage can ensure that the output signal of the first operational amplifier OPA1 swings symmetrically within the positive and negative power supply voltage ranges, maximizing the dynamic range.

[0088] It should be noted that the first switched-capacitor integration circuit 10 is a fully differential circuit, and common-mode noise can be canceled through a symmetric path. In the first example of this embodiment, the first switching circuit 110 includes: a first switch k1 and a second switch k2; the first end of the first switch k1 is connected to the analog detection voltage, and the second end is connected to the first end of the first capacitor C1; the first end of the second switch k2 is connected to the analog detection voltage, and the second end is connected to the first end of the second capacitor C2. The second switching circuit 120 includes: a third switch k3, a fourth switch, a fifth switch k5, and a sixth switch k6. The first end of the third switch k3 is connected to the second voltage, and the second end is connected to the second end of the first capacitor C1 and the first end of the fifth switch k5; the first end of the fourth switch is connected to the second voltage, and the second end is connected to the second end of the second capacitor C2 and the first end of the sixth switch k6; the second end of the fifth switch k5 is connected to the first end of the third capacitor C3 and the non-inverting input terminal of the first operational amplifier OPA1, and the second end of the sixth switch k6 is connected to the first end of the fourth capacitor C4 and the inverting input terminal of the first operational amplifier OPA1. During the sampling phase, the two-phase non-overlapping clock 30 outputs a first driving signal to the control terminals of the first switch k1, the third switch k3, and the fourth switch, so that the first switch k1, the third switch k3, and the fourth switch are closed; at this time, the second switch k2, the fifth switch k5, and the sixth switch k6 are open. The analog detection voltage charges the first capacitor C1 and the second capacitor C2. During the integration phase, the two-phase non-overlapping clock 30 outputs a second driving signal to the control terminals of the second switch k2, the fifth switch k5, and the sixth switch k6, so that the second switch k2, the fifth switch k5, and the sixth switch k6 are closed; at this time, the first switch k1, the third switch k3, and the fourth switch are open. The charge on the first capacitor C1 is transferred to the third capacitor C3 through the fifth switch k5; the charge on the second capacitor C2 is transferred to the fourth capacitor C4 through the sixth switch k6. The first to sixth switches k6 can be switching devices with a relatively high switching frequency, such as MOS transistors.

[0089] It should be noted that due to the existence of the charge storage effect, when the switch is turned off, there may be residual charge, and the residual charge may be injected into the first capacitor C1 and the second capacitor C2, resulting in errors. For example: the third switch k3 and the fourth switch are MOS transistors. When the third switch k3 or the fourth switch is turned off, the residual charge in the MOS transistor channel will be injected into the first capacitor C1 or the second capacitor C2. To solve the error caused by the charge storage effect, in the second example of this embodiment, the two-phase non-overlapping clock 30 outputs four signals, namely a first driving signal, a first delayed driving signal, a second driving signal, and a second delayed driving signal. Among them, refer to Figure 3, the first driving signal and the first delayed driving signal are generated simultaneously, but the first driving signal disappears earlier than the first delayed driving signal; the second driving signal and the second delayed driving signal are generated simultaneously, but the second driving signal disappears earlier than the second delayed driving signal. The two-phase non-overlapping clock 30 outputs the first driving signal to the control terminals of the third switch k3 and the fourth switch, outputs the first delayed driving signal to the control terminal of the second switch k2, and outputs the second driving signal to the control terminals of the fifth switch k5 and the sixth switch k6. It is easy to understand that, under the action of the signals output by the two-phase non-overlapping clock 30, during the sampling stage, the second switch k2, the third switch k3 and the fourth switch are turned on simultaneously, the third switch k3 and the fourth switch are turned off first, and the second switch k2 is turned off after a period of delay under the action of the first delayed driving signal, so that the residual charge reaches the ground through the second switch k2 for release, reducing the amount of charge injected into the first capacitor C1 and the second capacitor C2. During the integration stage, the first switch k1, the fifth switch k5 and the sixth switch k6 are turned on simultaneously, the fifth switch k5 and the sixth switch k6 are turned off first, disconnecting the channel between the third capacitor C3 and the first capacitor C1, and disconnecting the channel between the fourth capacitor C4 and the second capacitor C2. The first switch k1 is turned off after a period of delay under the action of the second delayed driving signal, releasing the residual charge of the first capacitor C1 and the second capacitor C2, improving the linearity and accuracy of the circuit.

[0090] In addition, it should be noted that, as Figure 2 shown, the output terminals of the digital-to-analog conversion module 50 are respectively connected to the first ends of the first capacitor C1 and the second capacitor C2; in particular, in order to realize the feedback of the first switched-capacitor integration circuit 10 and push the noise to the high-frequency band during the integration operation; when the two-phase non-overlapping clock 30 outputs the first delayed driving signal and the voltage value of the modulation signal is greater than the preset conduction voltage value, the digital-to-analog conversion module 50 outputs the first voltage to the first end of the first capacitor C1; when the two-phase non-overlapping clock 30 outputs the first delayed driving signal and the voltage value of the modulation signal is less than the preset conduction voltage value, the digital-to-analog conversion module 50 outputs zero potential to the first end of the first capacitor C1. It should be noted that during the sampling stage, the first end of the first capacitor C1 receives the first voltage or zero potential output from the digital-to-analog conversion module 50, and the first end of the second capacitor C2 receives the analog detection voltage. By transferring the charge of the first capacitor C1 to the third capacitor C3 during the integration stage, transferring the charge of the second capacitor C2 to the fourth capacitor C4, and performing integration operation through the first operational amplifier OPA1, the technical effect of pushing the low-frequency noise to the high-frequency band is achieved.

[0091] When the digital-to-analog conversion module 50 outputs a second delayed driving signal at the two-phase non-overlapping clock 30 and the voltage value of the modulation signal is greater than or equal to a preset conduction voltage value, the digital-to-analog conversion module 50 outputs a first voltage to the second capacitor C2; when the digital-to-analog conversion module 50 outputs a second delayed driving signal at the two-phase non-overlapping clock 30 and the voltage value of the modulation signal is less than the preset conduction voltage value, the digital-to-analog conversion module 50 outputs a zero potential to the second capacitor C2.

[0092] In the third embodiment of the present invention, the second switched-capacitor integrating circuit 20 includes: a third switching circuit 210, a fourth switching circuit 220, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, and a second operational amplifier OPA2;

[0093] The input end of the third switching circuit 210 is connected to the output end of the first switched-capacitor integrating circuit 10, the second end is connected to the first end of the fifth capacitor C5, and the third end is connected to the first end of the sixth capacitor C6; the first end of the fourth switching circuit 220 is connected to the second end of the fifth capacitor C5, the second end is connected to the second end of the sixth capacitor C6, the third end is connected to a second voltage, the fourth end is connected to the first end of the seventh capacitor C7 and the first input end of the second operational amplifier OPA2, and the fifth end is connected to the first end of the eighth capacitor C8 and the second input end of the second operational amplifier OPA2; the first output end of the second operational amplifier OPA2 is connected to the second end of the seventh capacitor C7 and the first input end of the quantizer 40, and the second output end is connected to the second end of the eighth capacitor C8 and the second input end of the quantizer 40;

[0094] The two-phase non-overlapping clock 30 is connected to the third switching circuit 210 and the fourth switching circuit 220; the two-phase non-overlapping clock 30 generates a first driving signal and a second driving signal; the third switching circuit 210 is configured to short-circuit the path between the second end and the third end of the third switching circuit 210 under the control of the first driving signal; the fourth switching circuit 220 is configured to conduct the path between the first end and the fourth end of the fourth switching circuit 220 and conduct the path between the second end and the fifth end of the fourth switching circuit 220 under the control of the first driving signal;

[0095] The third switching circuit 210 is further configured to conduct the path between the input end of the third switching circuit 210 and the first end of the fifth capacitor C5 and conduct the path between the input end of the third switching circuit 210 and the first end of the sixth capacitor C6 under the control of the second driving signal; the fourth switching circuit 220 is further configured to conduct the path between the first end and the third end of the fourth switching circuit 220 and conduct the path between the second end and the third end of the fourth switching circuit 220 under the control of the second driving signal.

[0096] Referring to Figure 2 , it should be noted that the operation of the second switched-capacitor integrating circuit 20 is divided into two stages: a sampling stage and an integrating stage, which are completed by the two-phase non-overlapping clock 30 controlling the third switching circuit 210 and the fourth switching circuit 220. The fifth capacitor C5 and the sixth capacitor C6 are sampling capacitors for sampling the input signal; the seventh capacitor C7 and the eighth capacitor C8 are integrating capacitors for storing and accumulating charges to achieve the integrating function. In the sampling stage, the two-phase non-overlapping clock 30 outputs a second driving signal, and the third switching circuit 210 conducts the path between the positive output terminal of the first operational amplifier OPA1 and the first terminal of the fifth capacitor C5, and conducts the path between the negative output terminal of the first operational amplifier OPA1 and the first terminal of the sixth capacitor C6. The fifth capacitor C5 and the sixth capacitor C6 store charges under the action of the first differential signal output by the first operational amplifier OPA1. In the integrating stage, the two-phase non-overlapping clock 30 outputs a first driving signal to the third switching circuit 210 and the fourth switching circuit 220; the fourth switching circuit 220, under the control of the first driving signal, conducts the path between the first terminal and the fourth terminal of the fourth switching circuit 220, and conducts the path between the second terminal and the fifth terminal of the fourth switching circuit 220, so that the charge of the fifth capacitor C5 is transferred to the seventh capacitor C7, and the charge of the sixth capacitor C6 is transferred to the eighth capacitor C8; the second operational amplifier OPA2 performs an integrating operation. The third switching circuit 210 is used to short-circuit the path between the second terminal and the third terminal of the third switching circuit 210 under the control of the first driving signal, so as to prevent the first differential signal output by the first switched-capacitor integrating circuit 10 from affecting the integrating operation of the second operational amplifier OPA2.

[0097] The first power supply terminal of the second operational amplifier OPA2 is connected to a first voltage, and the second power supply terminal is connected to ground. The second voltage value as a bias voltage can ensure that the output signal of the first operational amplifier OPA1 swings symmetrically within the positive and negative power supply voltage ranges, maximizing the dynamic range.

[0098] The second switched-capacitor integrating circuit 20 is a fully differential circuit. In the first example of this embodiment, the third switching circuit 210 includes: a seventh switch k7, an eighth switch k8, and a ninth switch k9; the first terminal of the seventh switch k7 is connected to the non-inverting input terminal of the first operational amplifier OPA1, and the second terminal is connected to the first terminal of the fifth capacitor C5; the first terminal of the eighth switch k8 is connected to the inverting input terminal of the first operational amplifier OPA1, and the second terminal is connected to the first terminal of the sixth capacitor C6; the ninth switch k9 is disposed between the second terminal of the seventh switch k7 and the second terminal of the eighth switch k8.

[0099] The fourth switching circuit 220 includes: a tenth switch k10, an eleventh switch k11, a twelfth switch k12, and a thirteenth switch k13; a first end of the tenth switch k10 is connected to a second voltage, and a second end thereof is connected to a second end of the fifth capacitor C5 and a first end of the twelfth switch k12; a first end of the eleventh switch k11 is connected to the second voltage, and a second end thereof is connected to a second end of the sixth capacitor C6 and a first end of the thirteenth switch k13; a second end of the twelfth switch k12 is connected to a non-inverting input terminal of the second operational amplifier OPA2 and a first end of the seventh capacitor C7, and a second end of the thirteenth switch k13 is connected to an inverting input terminal of the second operational amplifier OPA2 and a first end of the eighth capacitor C8.

[0100] During a sampling phase of the second switched-capacitor integrating circuit 20, the two-phase non-overlapping clock 30 outputs a second driving signal to the seventh switch k7, the eighth switch k8, the tenth switch k10, and the eleventh switch k11, so that the seventh switch k7, the eighth switch k8, the tenth switch k10, and the eleventh switch k11 are turned on; at this time, the ninth switch k9, the twelfth switch k12, and the thirteenth switch k13 are turned off. The fifth capacitor C5 and the sixth capacitor C6 accumulate charges under the action of a first differential signal output by the first operational amplifier OPA1. During an integrating phase of the second switched-capacitor integrating circuit 20, the two-phase non-overlapping clock 30 outputs a first driving signal to the ninth switch k9, the twelfth switch k12, and the thirteenth switch k13, so that the ninth switch k9, the twelfth switch k12, and the thirteenth switch k13 are turned on; at this time, the seventh switch k7, the eighth switch k8, the tenth switch k10, and the eleventh switch k11 are turned off. It is easy to understand that when the twelfth switch k12 is turned on, a channel from the fifth capacitor C5 to the seventh capacitor C7 is conducted, so that the charges on the fifth capacitor C5 are transferred to the seventh capacitor C7. When the thirteenth switch k13 is turned on, a channel from the sixth capacitor C6 to the eighth capacitor C8 is conducted, so that the charges on the sixth capacitor C6 are transferred to the eighth capacitor C8.

[0101] In order to avoid errors caused by charge storage effects in the integrating operation of the second switched-capacitor integrating circuit 20, in a second example of this embodiment, the two-phase non-overlapping clock 30 outputs four signals; specifically, the two-phase non-overlapping clock 30 outputs a second delayed driving signal to control terminals of the seventh switch k7 and the eighth switch k8, outputs a second driving signal to control terminals of the tenth switch k10 and the eleventh switch k11, outputs a first driving signal to control terminals of the twelfth switch k12 and the thirteenth switch k13, and outputs a first delayed driving signal to a control terminal of the ninth switch k9.

[0102] In the sampling stage, the seventh switch k7, the eighth switch k8, the tenth switch k10, and the eleventh switch k11 are turned on simultaneously. The tenth switch k10 and the eleventh switch k11 are turned off first, and the seventh switch k7 and the eighth switch k8 are turned off after a delay under the action of the second delay driving signal, so that the residual charge reaches the ground through the seventh switch k7 and the eighth switch k8 for release, reducing the amount of charge injected into the fifth capacitor C5 and the sixth capacitor C6. In the integration stage, the ninth switch k9, the twelfth switch k12, and the thirteenth switch k13 are turned on simultaneously. The ninth switch k9 is turned off after a delay under the action of the first delay driving signal, shorting the fifth capacitor C5 and the sixth capacitor C6 to avoid errors caused by the difference in the amount of charge on the fifth capacitor C5 and the sixth capacitor C6.

[0103] In addition, it should be noted that, as Figure 2 shown, the output terminals of the digital-to-analog conversion module 50 are respectively connected to the first ends of the fifth capacitor C5 and the sixth capacitor C6; in particular, in order to realize the feedback of the second switched-capacitor integration circuit 20 and push the noise to the high-frequency band during the integration operation; when the digital-to-analog conversion module 50 outputs a second delay driving signal in the two-phase non-overlapping clock 30 and the voltage value of the modulation signal is greater than the preset conduction voltage value, a zero potential is output to the first ends of the fifth capacitor C5 and the sixth capacitor C6; when the digital-to-analog conversion module 50 outputs a second delay driving signal in the two-phase non-overlapping clock 30 and the voltage value of the modulation signal is less than the preset conduction voltage value, a first voltage is output to the first ends of the fifth capacitor C5 and the sixth capacitor C6.

[0104] The digital-to-analog conversion module 50 is a one-bit DAC.

[0105] In the third example of this embodiment, the second switched-capacitor integration circuit 20 further includes: a ninth capacitor C9 and a tenth capacitor C10. The ninth capacitor C9 is connected in parallel with the fifth capacitor C5, and the tenth capacitor C10 is connected in parallel with the sixth capacitor C6. One end of the ninth capacitor C9 and one end of the tenth capacitor C10 are connected to the digital-to-analog conversion module 50. The charge output by the digital-to-analog conversion module 50 first enters the ninth capacitor C9 and the tenth capacitor C10, and then gradually transfers to the fifth capacitor C5 and the sixth capacitor C6.

[0106] It should be noted that the value of the first capacitor C1 is equal to the value of the second capacitor C2, the value of the third capacitor C3 is equal to the value of the fourth capacitor C4, the value of the fifth capacitor C5 is equal to the value of the sixth capacitor C6, the value of the seventh capacitor C7 is equal to the value of the eighth capacitor C8, and the value of the ninth capacitor C9 is equal to the value of the tenth capacitor C10. Refer to Figure 4, when the ratio of the value of the first capacitor C1 to the value of the third capacitor C3 is 1:12, and the ratio of the values of the fifth capacitor C5, the seventh capacitor C7, and the ninth capacitor C9 is 1:4:12. The effective number of bits for the sigma-delta modulation circuit proposed by the present invention to obtain temperature information can reach 14.65 bits.

[0107] In the fourth embodiment of the present invention, the first operational amplifier OPA1 or the second operational amplifier OPA2 is composed of a two-stage structure. The first-stage structure is a cascode common-source structure, and the second-stage structure is a common-source amplification structure.

[0108] It should be explained that the cascode common-source structure is adopted in the first stage because the cascode common-source structure has a higher gain. The simple common-source amplification structure is adopted in the second stage, which can improve the gain and has a higher output swing. The second-stage structure is a common-source amplification structure, which has the advantages of simple structure and low power consumption, and is conducive to reducing the power consumption of the overall circuit. The cascode common-source structure provides high gain, which can ensure the signal amplification accuracy, and the common-source amplification structure provides high bandwidth to ensure the signal's fast response. In addition, the cascode structure is beneficial to suppressing input noise and improving the signal-to-noise ratio. The cooperation of the cascode common-source structure and the common-source amplification structure can balance the gain and speed requirements and optimize the overall performance.

[0109] Referring to Figure 5 , the cascode common-source structure includes: the first resistor R1, the first to seventeenth NMOS transistors MN17, and the first to eighth PMOS transistors MP8;

[0110] The gates of the first NMOS transistor MN1 to the fourth NMOS transistor MN4 are interconnected, the sources of the first NMOS transistor MN1 to the fourth NMOS transistor MN4 are interconnected, the source of the fifth NMOS transistor MN5, the source of the sixth NMOS transistor MN6 and the drain of the first MOS transistor are connected, the drain of the fifth NMOS is connected to the source of the twelfth NMOS transistor MN12, the drain of the sixth NMOS is connected to the source of the thirteenth NMOS transistor MN13, the source of the seventh NMOS transistor MN7, the source of the eighth NMOS transistor MN8 and the drain of the second MOS transistor are connected, the drains of the seventh NMOS and the eighth NMOS are connected to the source of the fourteenth NMOS transistor MN14; the drain of the third NMOS transistor MN3 is connected to the source of the ninth NMOS transistor MN9 and the first end of the first resistor R1, the drain of the ninth NMOS transistor MN9 is connected to the source of the fifteenth NMOS transistor MN15, the source of the tenth NMOS transistor MN10, the source of the eleventh NMOS transistor MN11, the drain of the fourth NMOS transistor MN4 and the second end of the first resistor R1 are connected, the gates of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are connected to the common-mode setting output voltage, the gate of the ninth NMOS transistor MN9 is connected to the common-mode feedback voltage, the drain of the tenth NMOS transistor MN10 is connected to the source of the sixteenth NMOS transistor MN16, the drain of the eleventh NMOS transistor MN11 is connected to the source of the seventeenth NMOS; the gates of the fifth NMOS transistor MN5 and the seventh NMOS transistor MN7 are connected to the positive input terminal of the operational amplifier, the gates of the sixth NMOS transistor MN6 and the eighth NMOS transistor MN8 are connected to the negative input terminal of the operational amplifier; the gates of the twelfth NMOS transistor MN12 to the seventeenth NMOS transistor MN17 are interconnected;

[0111] The drain of the fourteenth NMOS transistor MN14 is connected to the source of the first PMOS transistor MP1, the gates of the fifth PMOS transistor MP5, the seventh PMOS transistor MP7, and the eighth PMOS transistor MP8. The drain of the first PMOS transistor MP1 is connected to the source of the fifth PMOS transistor MP5. The drain of the fifteenth NMOS transistor MN15 is connected to the gate of the second PMOS transistor MP2, the source of the second PMOS transistor MP2, and the gate of the sixth PMOS transistor MP6. The drain of the second PMOS transistor MP2 is connected to the source of the sixth PMOS transistor MP6. The drains of the twelfth NMOS transistor MN12, the sixteenth NMOS transistor MN16, the source of the third PMOS transistor MP3, and the first end of the common-source amplifier circuit are connected. The drains of the thirteenth NMOS transistor MN13, the seventeenth NMOS transistor MN17, the source of the fourth PMOS transistor MP4, and the second end of the common-source amplifier circuit are connected. The drain of the third PMOS transistor MP3, the source of the seventh PMOS transistor MP7, and the third end of the common-source amplifier circuit are connected. The drain of the fourth PMOS transistor MP4, the source of the eighth PMOS transistor MP8, and the fourth end of the common-source amplifier circuit are connected.

[0112] The gates of the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the fourteenth NMOS transistor MN14, the fifteenth NMOS transistor MN15, the sixteenth NMOS transistor MN16, and the seventeenth NMOS transistor MN17 are connected to each other. The gates of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are connected to each other. The drains of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, and the eighth PMOS transistor MP8 are connected to each other.

[0113] The common-source amplifier structure includes: the second to third resistors R3, the eleventh to fourteenth capacitors C14, the eighteenth to nineteenth NMOS transistors MN19, and the ninth to tenth PMOS transistors MP10;

[0114] The gates of the eighteenth NMOS transistor MN18 and the nineteenth NMOS transistor MN19 are connected, and the sources of the eighteenth NMOS transistor MN18, the nineteenth NMOS transistor MN19 and the first NMOS transistor MN1 are connected; the drain of the eighteenth NMOS transistor MN18 is connected to the source of the ninth PMOS transistor MP9, the second resistor R2 and the eleventh capacitor C11 are connected in parallel and arranged between the drain of the eighteenth NMOS transistor MN18 and the gate of the ninth NMOS transistor MN9, the drain of the nineteenth NMOS transistor MN19 is connected to the source of the tenth PMOS transistor MP10, the third resistor R3 and the twelfth capacitor C12 are connected in parallel and arranged between the drain of the nineteenth NMOS transistor MN19 and the gate of the ninth NMOS transistor MN9; one end of the thirteenth capacitor C13 is connected to the drain of the third PMOS transistor MP3, and the other end is connected to the drain of the eighteenth NMOS transistor MN18; one end of the fourteenth capacitor C14 is connected to the drain of the fourth PMOS transistor MP4, and the other end is connected to the drain of the nineteenth NMOS transistor MN19; the gate of the ninth PMOS transistor MP9 is connected to the source of the third PMOS transistor MP3, and the gate of the tenth PMOS transistor MP10 is connected to the source of the fourth PMOS transistor MP4; the drains of the ninth PMOS transistor MP9, the tenth PMOS transistor MP10 and the fifth PMOS transistor MP5 are connected.

[0115] It should be noted that since the output ends of the cascode structure and the common-source amplifier structure both correspond to high-impedance states, a common-mode feedback circuit is required to ensure normal operation. Specifically, the second resistor R2 and the third resistor R3 detect the output common-mode level and output it to the gate of the ninth NMOS transistor MN9. However, since the second resistor R2 and the third resistor R3 are prone to form low-frequency poles with parasitic capacitors at the output end, in this embodiment, the eleventh capacitor C11 and the twelfth capacitor C12 are respectively connected in parallel with the second resistor R2 and the third resistor R3 to extrapolate the poles at the common-mode output and maintain the stability of the common-mode loop. One end of the first resistor R1 is connected to the drain of the fourth NMOS transistor MN4, and the other end is connected to the drain of the third NMOS transistor MN3; the first resistor R1 can suppress the fluctuation of the common-mode level caused by load changes or reference voltage changes and play a filtering effect.

[0116] In addition, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 ensure that the drain-source voltage of the second NMOS transistor MN2 is the same as that of the fourth NMOS transistor MN4, and ensure that the drain-source voltages of the fifth PMOS transistor MP5, the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are the same, thereby increasing the accuracy of current replication and avoiding the deviation of the common-mode feedback voltage from the common-mode set output voltage.

[0117] In addition, the twelfth capacitor C12 and the thirteenth capacitor C13 are arranged between the sleeve-type cascode structure and the common-source amplification structure for Miller compensation. Specifically, one end of the twelfth capacitor C12 is connected to the source of the ninth PMOS transistor MP9, and the other end is connected to the drain of the third PMOS transistor MP3; one end of the thirteenth capacitor C13 is connected to the source of the tenth PMOS transistor MP10, and the other end is connected to the drain of the fourth PMOS transistor MP4. The third PMOS transistor MP3 and the fourth PMOS transistor MP4 serve as the zeroing resistors for Miller compensation.

[0118] Compared with the traditional operational amplifier, the operational amplifier proposed by the present invention eliminates the structure of the error amplifier, performs feedback in the form of currents I1, I2, I3, and I4, reduces poles, and improves the stability of the common-mode loop.

[0119] In the fifth embodiment of the present invention, the quantizer 40 includes: a preamplifier, a dynamic comparator, and a latch;

[0120] The input end of the preamplifier is connected to the output end of the second switched-capacitor integration circuit 20, and the output end is connected to the input end of the dynamic comparator; the clock end of the dynamic comparator accesses a clock signal, and the output end is connected to the latch;

[0121] The preamplifier is used to reduce the kickback noise and outputs the second differential voltage after amplifying it by a first multiple;

[0122] The dynamic comparator is used to compare the voltage at the output end of the preamplifier with a reference voltage when the clock signal is valid, and output a level signal to the latch according to the comparison result; the latch is used to latch and hold the level signal.

[0123] As Figure 6 shown, the preamplifier is to reduce the kickback noise. If Vip > Vin, then Von1 < Vop1. When CLK = 0, X < Y, the dynamic comparator does not work, Sb = 1, Rb = 1, and the SR latch is in the holding state; when CLK = 1, the output of the dynamic comparator will change according to the input. Due to the existence of the positive feedback structure, Y will quickly become the first voltage value, and X will quickly become 0. At this time, Sb = 0, Rb = 1, and Vout = 1, completing a comparison process.

[0124] The present invention also proposes a high-precision temperature sensor, which includes a temperature detection circuit, a counter, and the sigma-delta modulation circuit;

[0125] The output end of the temperature detection circuit is connected to the input end of the first switched-capacitor integration circuit 10, and the output end of the quantizer 40 is connected to the counter;

[0126] The temperature detection circuit is configured to convert the detected temperature value into an analog detection voltage and output it to the input end of the first switched-capacitor integration circuit 10;

[0127] The counter is configured to sample and count the modulation signal, and convert the pulse density information in the modulation signal into a corresponding digital quantity.

[0128] Refer to Figure 7 , the temperature detection circuit is configured to convert the actual temperature change into an analog detection voltage linearly related to the temperature change. The Sigma-delta modulator converts the analog detection voltage into modulation information. Specifically, the debugging information can be a one-bit binary PDM code stream, and the effective number of bits of the debugging information can reach more than 12 bits. The counter samples the modulation signal and counts the pulse density information in the modulation signal. For example: the counter samples the PDM code stream information and counts, and outputs a 12-bit parallel binary number to reflect the magnitude of the temperature.

[0129] Refer to Figure 8 , the temperature detection circuit is as Figure X shown, and the volt-ampere characteristic formula of the PN junction is as follows:

[0130]

[0131] where Ic is the collector current of the triode, V BE is the base-emitter voltage of the triode, is the thermal voltage, k is the Boltzmann constant, T is the temperature, q is the electron charge, Is is the saturation current, proportional to μ is the minority carrier mobility, n i is the intrinsic carrier concentration of silicon. Combining the relationship between μ, n i and temperature, it can be obtained that:

[0132]

[0133] where b is a proportionality coefficient and Eg is the bandgap energy of silicon. After differentiating the above formula with respect to temperature, it can be seen that VBE has a negative temperature coefficient, so the output voltage decreases as the temperature rises.

[0134] In the sixth embodiment of the present invention, the counter includes: an AND gate circuit, and a register group formed by a plurality of registers connected in series;

[0135] The first input end of the AND gate circuit is connected to the clock signal, and the second input end is connected to the output end of the quantizer 40; the clock end of the first-level register is connected to the output end of the AND gate circuit; the output end of the previous-level register is connected to the clock end of the next-level register and the data end of the previous-level register.

[0136] Reference Figure 9 The counter processes the 1-bit PDM signal output by the sigma-delta modulator and performs 2 12 Sampling and counting are performed, and the counting result can reflect the current temperature.

[0137] The present invention uses registers to build a counter, connects the output end of the previous level register to the clock end of the next level register, and then connects the output end back to the data input end of the current level register, so as to realize the rising edge reversal operation. Through the clock transmission and output reversal of each level register, the counting function can be realized. The present invention uses registers to build a counter, replacing the structure of traditional digital filtering. The sampling process is equivalent to the effect of low-pass filtering. The circuit complexity is low, the area power consumption is smaller, and it is more suitable for analog-to-digital conversion of low-frequency signals such as temperature sensors. Figure X As shown, before counting starts, RST is set high to reset. After the reset, the counting starts. The inverted clock signal and the PDM signal are ANDed, which is equivalent to sampling the PDM signal at the rising edge of CLKN. 12 After sampling, set LA high to latch the result.

[0138] Reference Figure 10 , the PDM signal is triggered by the rising edge of the clock. After the counter recognizes the high level of PDM, it adds one to the counting result at the falling edge of the clock, and latches the result after 212 samples. PDM corresponds to temperature one by one, so the final counting result can reflect the temperature.

[0139] Reference Figure 11 , at -45℃~135℃, the simulation is performed at intervals of 10℃. Each temperature will correspond to a counting result. The numerical value can be made into a lookup table. In practical applications, the current temperature value can be inferred based on the counting value. The test results show that for every increase in the counting result, the corresponding temperature changes by 0.25℃. Therefore, the temperature sensing resolution of the present invention can reach 0.25℃ / bit. A 128kHz sampling clock is used, so the time for a temperature detection is 212 / 128k=32ms.

[0140] The above are only alternative embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structural transformation made by using the content of the specification and drawings of the present invention under the inventive concept of the present invention, or any direct / indirect application in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A sigma-delta modulation circuit, characterized in that, The sigma-delta modulation circuit includes: a two-phase non-overlapping clock, a first switched-capacitor integration circuit, a second switched-capacitor integration circuit, a quantizer, and a digital-to-analog conversion module; The input end of the first switched-capacitor integration circuit is connected to an analog detection voltage, and the output end is connected to the input end of the second switched-capacitor integration circuit; the output end of the second switched-capacitor integration circuit is connected to the quantizer; the input end of the digital-to-analog conversion module is connected to the output end of the quantizer, and the output end is connected to the input ends of the first switched-capacitor integration circuit and the second switched-capacitor integration circuit; The two-phase non-overlapping clock is used to provide a driving signal; The first switched-capacitor integration circuit is used to sample and hold the analog detection voltage, and perform an integration process on the analog detection voltage, and output a first differential voltage after the integration process; the second switched-capacitor integration circuit is used to sample and hold the first differential voltage, and perform an integration process on the first differential voltage, and output a second differential voltage to the quantizer; The quantizer is used to convert the second differential voltage into a modulation signal containing temperature information; The digital-to-analog conversion module is used to convert the modulation signal into a corresponding feedback voltage and output it to the first switched-capacitor integration circuit and the second switched-capacitor integration circuit; A switching circuit is arranged in the first switched-capacitor integration circuit and the second switched-capacitor integration circuit, and is controlled by the driving signal, and is used to switch the first switched-capacitor integration circuit to sample the analog detection voltage or perform an integration process on the analog detection voltage, and switch the second switched-capacitor integration circuit to perform an integration process on the first differential voltage or sample the first differential voltage.

2. The sigma-delta modulation circuit according to claim 1, wherein, The digital-to-analog conversion module includes: a first switching device; The controlled end of the first switching device is connected to the output end of the quantizer, the first end is connected to a first voltage, the second end is grounded and connected to the input ends of the first switched-capacitor integration circuit and the second switched-capacitor integration circuit; The first switching device is used to output a first voltage to the input end of the first switched-capacitor integration circuit and the second switched-capacitor integration circuit when the voltage value of the modulation signal is greater than a preset conduction voltage value.

3. The sigma-delta modulation circuit according to claim 1, wherein The first switched-capacitor integration circuit includes: a first switching circuit, a second switching circuit, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a first operational amplifier; The first end of the first switching circuit is connected to the analog detection voltage, the second end is connected to the first end of the first capacitor, and the third end is connected to the first end of the second capacitor; the first end of the second switching circuit is connected to the second end of the first capacitor, the second end is connected to the second end of the second capacitor, the third end is connected to a second voltage, the fourth end is connected to the first end of the third capacitor and the first input terminal of the first operational amplifier, and the fifth end is connected to the first end of the fourth capacitor and the second input terminal of the first operational amplifier; the first output terminal of the first operational amplifier is connected to the second end of the third capacitor and the first input terminal of the second switched-capacitor integrating circuit, and the second output terminal is connected to the second end of the fourth capacitor and the second input terminal of the second switched-capacitor integrating circuit; The two-phase non-overlapping clock is connected to the first switching circuit and the second switching circuit; the two-phase non-overlapping clock generates a first driving signal and a second driving signal; the first switching circuit is configured to conduct the path between the first end and the third end of the first switching circuit under the control of the first driving signal; the second switching circuit is configured to conduct the path between the first end and the third end of the second switching circuit and conduct the path between the second end and the third end of the second switching circuit under the control of the first driving signal; The first switching circuit is further configured to conduct the path between the first end and the second end of the first switching circuit under the control of the second driving signal; the second switching circuit is further configured to conduct the path between the first end and the fourth end of the second switching circuit and conduct the path between the second end and the fifth end of the second switching circuit under the control of the second driving signal.

4. The sigma-delta modulation circuit according to claim 1, wherein, The second switched-capacitor integrating circuit includes: a third switching circuit, a fourth switching circuit, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, and a second operational amplifier; The input terminal of the third switching circuit is connected to the output terminal of the first switched-capacitor integrating circuit, the second end is connected to the first end of the fifth capacitor, and the third end is connected to the first end of the sixth capacitor; the first end of the fourth switching circuit is connected to the second end of the fifth capacitor, the second end is connected to the second end of the sixth capacitor, the third end is connected to a second voltage, the fourth end is connected to the first end of the seventh capacitor and the first input terminal of the second operational amplifier, and the fifth end is connected to the first end of the eighth capacitor and the second input terminal of the second operational amplifier; the first output terminal of the second operational amplifier is connected to the second end of the seventh capacitor and the first input terminal of the quantizer, and the second output terminal is connected to the second end of the eighth capacitor and the second input terminal of the quantizer; The two-phase non-overlapping clock is connected to the third switch circuit and the fourth switch circuit; the two-phase non-overlapping clock generates a first driving signal and a second driving signal; the third switch circuit is configured to short-circuit the path between the second end and the third end of the third switch circuit under the control of the first driving signal; the fourth switch circuit is configured to conduct the path between the first end and the fourth end of the fourth switch circuit and conduct the path between the second end and the fifth end of the fourth switch circuit under the control of the first driving signal. The third switch circuit is further configured to conduct the path between the input end of the third switch circuit and the first end of the fifth capacitor and conduct the path between the input end of the third switch circuit and the first end of the sixth capacitor under the control of the second driving signal; the fourth switch circuit is further configured to conduct the path between the first end and the third end of the fourth switch circuit and conduct the path between the second end and the third end of the fourth switch circuit under the control of the second driving signal.

5. The sigma-delta modulation circuit according to claim 4, wherein The first operational amplifier or the second operational amplifier is composed of a two-stage structure, the first stage structure is a cascode structure, and the second stage structure is a common-source amplifier structure.

6. The sigma-delta modulation circuit according to claim 5, wherein The cascode structure includes: a first resistor, first to seventeenth NMOS transistors, and first to eighth PMOS transistors. The gates of the first NMOS transistor to the fourth NMOS transistor are connected to each other, the sources of the first NMOS transistor to the fourth NMOS transistor are connected to each other, the source of the fifth NMOS transistor, the source of the sixth NMOS transistor and the drain of the first MOS transistor are connected, the drain of the fifth NMOS is connected to the source of the twelfth NMOS transistor, the drain of the sixth NMOS is connected to the source of the thirteenth NMOS transistor, the source of the seventh NMOS transistor, the source of the eighth NMOS transistor and the drain of the second MOS transistor are connected, the drains of the seventh NMOS and the eighth NMOS are connected to the source of the fourteenth NMOS transistor; the drain of the third NMOS transistor is connected to the source of the ninth NMOS transistor and the first end of the first resistor, the drain of the ninth NMOS transistor is connected to the source of the fifteenth NMOS transistor, the source of the tenth NMOS transistor, the source of the eleventh NMOS transistor, the drain of the fourth NMOS transistor and the second end of the first resistor are connected, the gates of the tenth NMOS transistor and the eleventh NMOS transistor are connected to the common-mode setting output voltage, the gate of the ninth NMOS transistor is connected to the common-mode feedback voltage, the drain of the tenth NMOS transistor is connected to the source of the sixteenth NMOS transistor, the drain of the eleventh NMOS transistor is connected to the source of the seventeenth NMOS transistor; the gates of the fifth NMOS transistor and the seventh NMOS transistor are connected to the positive-phase input end of the operational amplifier, the gates of the sixth NMOS transistor and the eighth NMOS transistor are connected to the negative-phase input end of the operational amplifier; the gates of the twelfth NMOS transistor to the seventeenth NMOS transistor are connected to each other. The drain of the fourteenth NMOS transistor is connected to the source of the first PMOS transistor, the gates of the fifth, seventh, and eighth PMOS transistors. The drain of the first PMOS transistor is connected to the source of the fifth PMOS transistor. The drain of the fifteenth NMOS transistor is connected to the gates of the second PMOS transistor, the second PMOS transistor's source, and the sixth PMOS transistor. The drain of the second PMOS transistor is connected to the source of the sixth PMOS transistor. The drains of the twelfth NMOS transistor, the sixteenth NMOS transistor, the source of the third PMOS transistor, and the first end of the common-source amplifier circuit are connected. The drains of the thirteenth NMOS transistor, the seventeenth NMOS transistor, the source of the fourth PMOS transistor, and the second end of the common-source amplifier circuit are connected. The drain of the third PMOS transistor, the source of the seventh PMOS transistor, and the third end of the common-source amplifier circuit are connected. The drain of the fourth PMOS transistor, the source of the eighth PMOS transistor, and the fourth end of the common-source amplifier circuit are connected. The gates of the twelfth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, and the seventeenth NMOS transistor are interconnected. The gates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are interconnected. The drains of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor are interconnected.

7. The sigma-delta modulation circuit according to claim 6, wherein The common-source amplifier structure includes: second to third resistors, eleventh to fourteenth capacitors, eighteenth to nineteenth NMOS transistors, ninth to tenth PMOS transistors; The gates of the eighteenth NMOS transistor and the nineteenth NMOS transistor are connected. The sources of the eighteenth NMOS transistor, the nineteenth NMOS transistor, and the source of the first NMOS transistor are connected. The drain of the eighteenth NMOS transistor is connected to the source of the ninth PMOS transistor. The second resistor and the eleventh capacitor are connected in parallel between the drain of the eighteenth NMOS transistor and the gate of the ninth NMOS transistor. The drain of the nineteenth NMOS transistor is connected to the source of the tenth PMOS transistor. The third resistor and the twelfth capacitor are connected in parallel between the drain of the nineteenth NMOS transistor and the gate of the ninth NMOS transistor. One end of the thirteenth capacitor is connected to the drain of the third PMOS transistor, and the other end is connected to the drain of the eighteenth NMOS transistor. One end of the fourteenth capacitor is connected to the drain of the fourth PMOS transistor, and the other end is connected to the drain of the nineteenth NMOS transistor. The gate of the ninth PMOS transistor is connected to the source of the third PMOS transistor. The gate of the tenth PMOS transistor is connected to the source of the fourth PMOS transistor. The drains of the ninth PMOS transistor, the tenth PMOS transistor, and the fifth PMOS transistor are connected.

8. The sigma-delta modulation circuit according to claim 4, wherein The quantizer includes: a preamplifier, a dynamic comparator, and a latch; The input end of the preamplifier is connected to the output end of the second switched-capacitor integrating circuit, and the output end is connected to the input end of the dynamic comparator. The clock terminal of the dynamic comparator receives a clock signal, and the output end is connected to the latch; The preamplifier is used to reduce the kickback noise and outputs the second differential voltage after being amplified by a first multiple; The dynamic comparator is configured to compare the voltage at the output terminal of the preamplifier with a reference voltage when the clock signal is valid, and output a level signal to the latch according to the comparison result; the latch is configured to latch and hold the level signal.

9. A high-precision temperature sensor, characterized in that, The high-precision temperature sensor includes a temperature detection circuit, a counter, and a sigma-delta modulation circuit according to any one of claims 1 to 8; The output terminal of the temperature detection circuit is connected to the input terminal of the first switched-capacitor integration circuit, and the output terminal of the quantizer is connected to the counter; The temperature detection circuit is configured to convert the detected temperature value into an analog detection voltage and output it to the input terminal of the first switched-capacitor integration circuit; The counter is configured to sample and count the modulation signal, and convert the pulse density information in the modulation signal into a corresponding digital quantity.

10. The high-precision temperature sensor according to claim 9, characterized in that, The counter includes: an AND gate circuit, and a register bank formed by a plurality of registers connected in series; The first input terminal of the AND gate circuit receives a clock signal, and the second input terminal is connected to the output terminal of the quantizer; the clock terminal of the first-stage register is connected to the output terminal of the AND gate circuit; the output terminal of the previous-stage register is connected to the clock terminal of the next-stage register and the data terminal of the previous-stage register.

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