Super junction trench gate MOSFET device and manufacturing method thereof

Abstract

The invention provides a super junction trench gate MOSFET device which comprises an N-type substrate, an N-type epitaxial layer is formed on the substrate, and a P-type body region is formed on the surface of the N-type epitaxial layer; a groove is formed in the top of the body region, the groove extends downwards from the upper surface of the N-type epitaxial layer to penetrate through the body region, and a first P column is formed on the N-type epitaxial layer at the bottom of the groove; the dielectric layer is located in the groove, and the groove is not completely filled with the dielectric layer; the gate dielectric layer is formed on the surface of the residual groove; the gate polycrystalline silicon layer is used for filling the residual groove; the source end heavily doped region is formed above the P-type body region; the second P column is formed on the N-type epitaxial layer below the P-type body region, and a transverse distance is formed between the first P column and the second P column; an interlayer dielectric layer is formed on the epitaxial layer, a contact hole for leading out a source end heavily doped region is formed in the interlayer dielectric layer, the heavily doped region is formed on the body region below the contact hole, and a metal electrode is formed in the contact hole. The breakdown voltage of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a superjunction trench-gate MOSFET device and a manufacturing method thereof. Background Art

[0002] SJ-DMOS (Super Junction Double-diffused MOS) is widely used in the fields of power supply, lighting, etc. because of its characteristics such as high breakdown voltage and low on-resistance.

[0003] Figure 1 As a schematic structural diagram of an existing superjunction trench-gate MOSFET device, this structure obtains sufficient longitudinal breakdown voltage by multi-step high-energy implantation of P-pillars (P-columns) at the bottom of the trench to deplete the N-type drift region.

[0004] Among them, the structures represented by each numerical number include: 1 - N-type substrate (drain end); 2 - N-type drift region; 3 - P-type body region; 4 - first P-type Pillar region; 5 - gate dielectric layer; 6 - polysilicon gate; 7 - N-type heavily doped region (source end); 8 - P-type heavily doped region; 9 - metal electrode.

[0005] Due to the limitation of the ion implantation energy on the depth of the P-column, it is difficult to significantly improve the breakdown voltage of this device structure. To solve the above problems, a new type of superjunction trench-gate MOSFET device and a manufacturing method thereof are needed. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a superjunction trench-gate MOSFET device and a manufacturing method thereof, which are used to solve the problem that the breakdown voltage of the superjunction trench-gate MOSFET device in the prior art needs to be further improved.

[0007] To achieve the above purpose and other related purposes, the present invention provides a superjunction trench-gate MOSFET device, including:

[0008] An N-type substrate, on which an N-type epitaxial layer is formed, and a P-type body region is formed on the surface of the N-type epitaxial layer;

[0009] A trench is formed on the top of the body region, the trench extends downward from the upper surface of the N-type epitaxial layer through the body region, and a first P-column is formed on the N-type epitaxial layer at the bottom of the trench;

[0010] A dielectric layer located in the trench, wherein the dielectric layer does not completely fill the trench;

[0011] A gate dielectric layer formed on the surface of the remaining trench, and a gate polysilicon layer filling the remaining trench;

[0012] A source heavily doped region formed above the P-type body region;

[0013] A second P pillar formed on the N-type epitaxial layer below the P-type body region, with a lateral spacing between the first P pillar and the second P pillar;

[0014] An interlayer dielectric layer formed on the epitaxial layer, a contact hole for leading out the source heavily doped region is formed on the interlayer dielectric layer, a heavily doped region is formed on the body region below the contact hole, and a metal electrode is formed in the contact hole.

[0015] Preferably, the depth of the second P pillar matches the depth of the trench: the depths of the two tend to be the same or the depth difference between the two is within a preset range.

[0016] Preferably, the energy of ion implantation for the first P pillar and the second P pillar is 400 - 3400 keV, and the ion implantation dose range is 1.0e12 - 1.0e13 (cm^-2).

[0017] Preferably, the first P pillar is led out by connecting in the width direction to the P-type body region.

[0018] The present invention also provides a manufacturing method of the above superjunction trench-gate MOSFET device, including:

[0019] Step 1: Provide an N-type substrate, form an N-type epitaxial layer on the substrate, form a P-type body region on the surface of the epitaxial layer, and then perform thermal diffusion and propulsion on the body region;

[0020] Step 2: Form a trench on the top of the body region, the trench extends downward from the upper surface of the N-type epitaxial layer through the body region, and form a first P pillar on the N-type epitaxial layer at the bottom of the trench;

[0021] Step 3: Form a dielectric layer in the trench, where the dielectric layer does not completely fill the trench;

[0022] Step 4: Form a gate dielectric layer on the surface of the remaining trench, and then form a gate polysilicon layer filling the remaining trench;

[0023] Step 5: Form a source heavily doped region above the P-type body region, and then form a second P pillar on the N-type epitaxial layer below the P-type body region, with a lateral spacing between the first P pillar and the second P pillar;

[0024] Step 6: Form an interlayer dielectric layer on the epitaxial layer, form a contact hole for leading out the heavily doped source region on the interlayer dielectric layer, perform heavy doping implantation on the body region below the contact hole, form a heavily doped region through thermal diffusion, and simultaneously activate the impurity implantation of the heavy doping implantation, and then form a metal electrode filling the contact hole.

[0025] Preferably, the method for forming the P-type body region in Step 1 includes: forming a first photoresist layer covering the N-type epitaxial layer; performing photolithography to open the first photoresist layer to define the formation region of the P-type body region; forming the P-type body region by ion implantation; and removing the first photoresist layer.

[0026] Preferably, the method for forming the trench in Step 2 includes: forming a second photoresist layer covering the N-type epitaxial layer; performing photolithography to open the second photoresist layer to define the formation region of the trench; and forming the trench by etching.

[0027] Preferably, the method for forming the first P pillar in Step 2 includes: using the second photoresist layer remaining after etching the trench as a mask, performing ion implantation to form the first P pillar; and removing the second photoresist layer.

[0028] Preferably, the method for forming the dielectric layer in Step 3 includes: forming the dielectric layer covering the N-type epitaxial layer by thermal oxidation or deposition; polishing the dielectric layer to the N-type epitaxial layer; and etching the dielectric layer in the trench to the required height.

[0029] Preferably, the method for forming the second P pillar in Step 5 includes: forming a third photoresist layer covering the N-type epitaxial layer; performing photolithography to open the third photoresist layer to define the formation region of the second P pillar; forming the second P pillar by ion implantation; and removing the third photoresist layer.

[0030] Preferably, the depth of the second P pillar in Step 5 matches the depth of the trench: the depths of the two tend to be the same or the depth difference between the two is within a preset range.

[0031] Preferably, the energy of ion implantation for the first P pillar and the second P pillar is 400 - 3400 KeV, and the ion implantation dose range is 1.0e12 - 1.0e13 (cm^-2).

[0032] Preferably, the first P pillar is led out by connecting in the width direction to the P-type body region.

[0033] As described above, the superjunction trench-gate MOSFET device and its manufacturing method of the present invention have the following beneficial effects:

[0034] The present invention improves the breakdown voltage of the device. Brief Description of the Drawings

[0035] Figure 1 Schematic diagram showing a superjunction trench-gate MOSFET device structure as prior art;

[0036] Figure 2 Schematic diagram showing the process flow of the present invention;

[0037] Figure 3 Schematic diagram showing the formation of a P-type body region according to the present invention;

[0038] Figure 4 Schematic diagram showing the formation of a first P pillar according to the present invention;

[0039] Figure 5 Schematic diagram showing the structure formed in the remaining trenches according to the present invention;

[0040] Figure 6 Schematic diagram showing the formation of a second P pillar according to the present invention;

[0041] Figure 7 Schematic diagram showing the formation of a metal electrode according to the present invention;

[0042] Figure 8 Schematic diagram showing a superjunction structure as prior art;

[0043] Figure 9 Schematic diagram showing the existing superjunction structure of the present invention;

[0044] Figure 10 Schematic diagram showing the comparison of the breakdown voltages of the existing superjunction structure and the superjunction structure of the present invention. Detailed Description of the Invention

[0045] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] Please refer to Figure 7 , the present invention provides a superjunction trench-gate MOSFET device, comprising:

[0047] An N-type substrate 1, on which an N-type epitaxial layer 2 is formed. The N-type epitaxial layer 2 serves as a drift region, and a P-type body region 3 is formed on the surface of the N-type epitaxial layer 2;

[0048] In an embodiment of the present invention, the substrate may include a bulk semiconductor substrate. Bulk semiconductors typically include crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multi-layer substrates, gradient substrates, or mixed-orientation substrates.

[0049] A trench is formed on top of the body region, the trench extends downward from the upper surface of the N-type epitaxial layer 2 through the body region, and a first P pillar 4 is formed on the N-type epitaxial layer 2 at the bottom of the trench;

[0050] A dielectric layer 10 is located in the trench, where the dielectric layer 10 does not completely fill the trench;

[0051] The material of the dielectric layer 10 may include dielectric materials such as silicon oxide, low-k dielectric materials, other suitable dielectric materials, or combinations thereof;

[0052] A gate dielectric layer 5 is formed on the surface of the remaining trench, and a gate polysilicon layer 6 fills the remaining trench;

[0053] The gate dielectric layer 5 may include dielectric materials such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SION). It can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods.

[0054] A source-end heavily doped region 7 is formed above the P-type body region 3;

[0055] A second P pillar 11 is formed on the N-type epitaxial layer 2 below the P-type body region 3, and there is a lateral spacing between the first P pillar 4 and the second P pillar 11;

[0056] In an embodiment of the present invention, the depth of the second P pillar 11 matches the depth of the trench: the depths of the two tend to be the same or the depth difference between the two is within a preset range. If the trench is too deep, the depletion regions of the two first P pillars 4 and the second P pillar 11 will be separated, so that the voltage will be all on the second P pillar 11 and the BV (breakdown voltage) will decrease suddenly.

[0057] In an embodiment of the present invention, the energy of ion implantation for the first P pillar 4 and the second P pillar 11 is 400 - 3400 KeV, and the ion implantation dose range is 1.0e12 - 1.0e13 (cm^-2).

[0058] An interlayer dielectric layer 10 is formed on the epitaxial layer. A contact hole for leading out the heavily doped source region 7 is formed on the interlayer dielectric layer 10. A heavily doped region 8 is formed on the body region below the contact hole, and a metal electrode 9 is formed in the contact hole.

[0059] In an embodiment of the present invention, the first P pillar 4 is led out by connecting to the P-type body region 3 in the width direction and is not floating.

[0060] The material of the interlayer dielectric layer 10 may include a dielectric material such as silicon oxide, a low-k dielectric material, other suitable dielectric materials, or a combination thereof.

[0061] In some examples, the low-k dielectric material includes fluorinated silicon glass (FSG), carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorocarbon, parylene, BCB (bisbenzocyclobutene), polyimide, and / or other suitable dielectric materials with a dielectric constant substantially less than that of thermally grown silicon oxide.

[0062] Please refer to Figure 8 , which shows a schematic diagram of a conventional superjunction structure. Please refer to Figure 9 , which shows a schematic diagram of the superjunction structure of the present invention. Please refer to Figure 10 , which shows a schematic diagram comparing the breakdown voltages of the conventional superjunction structure and the superjunction structure of the present invention. The breakdown voltage of the conventional superjunction structure is 135.2V, and the breakdown voltage of the superjunction structure of the present invention is 180.1V. It can be seen therefrom that the present invention improves the breakdown voltage of the device.

[0063] Please refer to Figure 2 , the present invention also provides a manufacturing method of the above superjunction trench-gate MOSFET device, including:

[0064] Step 1: Provide an N-type substrate 1. An N-type epitaxial layer 2 is formed on the substrate. The N-type epitaxial layer 2 serves as a drift region. A P-type body region 3 is formed on the surface of the epitaxial layer, and then thermal diffusion is carried out on the body region to form a structure as Figure 3 shown;

[0065] In an embodiment of the present invention, the substrate may include a bulk semiconductor substrate. The bulk semiconductor generally includes a crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloy, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or their combinations. The semiconductor material may be doped or undoped. Other substrates that can be used include multi-layer substrates, gradient substrates, or mixed-orientation substrates.

[0066] In an embodiment of the present invention, the method for forming the P-type body region 3 in step one includes: forming a first photoresist layer covering the N-type epitaxial layer 2; performing photolithography to open the first photoresist layer to define the formation region of the P-type body region 3; forming the P-type body region 3 by ion implantation; and removing the first photoresist layer.

[0067] Step two: forming a trench on the top of the body region, the trench extending downward from the upper surface of the N-type epitaxial layer 2 through the body region, and forming a first P pillar 4 on the N-type epitaxial layer 2 at the bottom of the trench, to form a structure as Figure 4 shown;

[0068] In an embodiment of the present invention, the method for forming the trench in step two includes: forming a second photoresist layer covering the N-type epitaxial layer 2; performing photolithography to open the second photoresist layer to define the formation region of the trench; forming the trench by etching, and the etching method is anisotropic dry etching.

[0069] In an embodiment of the present invention, the method for forming the first P pillar 4 in step two includes: using the second photoresist layer remaining after etching the trench as a mask, performing ion implantation to form the first P pillar 4; and removing the second photoresist layer.

[0070] Step three: forming a dielectric layer 10 in the trench, where the dielectric layer 10 does not completely fill the trench, and the material of the dielectric layer 10 can be a dielectric material including, such as silicon oxide, a low-k dielectric material, other suitable dielectric materials, or a combination thereof;

[0071] In an embodiment of the present invention, the method for forming the dielectric layer 10 in step three includes; forming the dielectric layer 10 covering the N-type epitaxial layer 2 by thermal oxidation or deposition; polishing the dielectric layer 10 onto the N-type epitaxial layer 2, and the polishing method is chemical mechanical planarization polishing; etching the dielectric layer 10 in the trench to the required height, and the etching method is dry etching or wet etching.

[0072] Step four: forming a gate dielectric layer 5 on the surface of the remaining trench, and then forming a gate polysilicon layer 6 filling the remaining trench, to form a structure as Figure 5 shown; the gate polysilicon layer 6 can be formed by deposition and polishing methods;

[0073] The gate dielectric layer 5 can include a dielectric material, such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SION). It can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods.

[0074] Step Five: Form an N-type heavily doped source region 7 above the P-type body region 3. Then, form a second P pillar 11 on the N-type epitaxial layer 2 below the P-type body region 3. There is a lateral spacing between the first P pillar 4 and the second P pillar 11, forming a structure as shown in Figure 6 . The first P pillar 4 and the second P pillar 11 are stacked for voltage withstand to obtain a higher voltage.

[0075] In an embodiment of the present invention, the method for forming the second P pillar 4 in Step Five includes: forming a third photoresist layer covering the N-type epitaxial layer 2; performing photolithography to open the third photoresist layer to define the formation region of the second P pillar 11; forming the second P pillar 11 by ion implantation; and removing the third photoresist layer.

[0076] In an embodiment of the present invention, the depth of the second P pillar 11 in Step Five matches the depth of the trench: the depths of the two tend to be the same or the depth difference between the two is within a preset range. If the trench is too deep, the depletion regions of the two first P pillars 4 and the second P pillar 11 will be separated, so that the voltage is all on the second P pillar 11 and the BV (breakdown voltage) will decrease sharply.

[0077] Step Six: Form an interlayer dielectric layer 10 on the epitaxial layer, form a contact hole for leading out the heavily doped source region 7 on the interlayer dielectric layer 10, perform heavy doping implantation on the body region below the contact hole, form a heavily doped region 8 through thermal diffusion, and at the same time activate the impurity implantation of the heavy doping implantation. Then, form a metal electrode 9 filling the contact hole, forming a structure as shown in Figure 7 .

[0078] The material of the interlayer dielectric layer 10 may include dielectric materials such as silicon oxide, low-k dielectric materials, other suitable dielectric materials, or combinations thereof.

[0079] In some examples, the low-k dielectric material includes fluorinated silicon glass (FSG), carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorocarbon, parylene, BCB (bisbenzocyclobutene), polyimide, and / or other suitable dielectric materials with a dielectric constant substantially less than that of thermally grown silicon oxide.

[0080] In an embodiment of the present invention, the energy of ion implantation for the first P pillar 4 and the second P pillar 11 is 400 - 3400 KeV, and the dose range of ion implantation is 1.0e12 - 1.0e13 (cm^-2).

[0081] In an embodiment of the present invention, the first P pillar 4 is led out by connecting in the width direction to the P-type body region 3 and is not floating.

[0082] Please refer to Figure 8 , which shows a schematic diagram of a conventional superjunction structure. Please refer to Figure 9 , which shows a schematic diagram of the superjunction structure of the present invention. Please refer toFigure 10 , which shows a schematic diagram of the breakdown voltage comparison between the existing superjunction structure and the superjunction structure of the present invention. The breakdown voltage of the existing superjunction structure is 135.2V, and the breakdown voltage of the superjunction structure of the present invention is 180.1V. It can be seen from this that the present invention improves the breakdown voltage of the device.

[0083] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0084] In summary, the present invention improves the breakdown voltage of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0085] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A superjunction trench-gate MOSFET device, characterized in that, Including: An N-type substrate, an N-type epitaxial layer is formed on the substrate, and a P-type body region is formed on the surface of the N-type epitaxial layer; A trench is formed on top of the body region, the trench extends downward from the upper surface of the N-type epitaxial layer through the body region, and a first P pillar is formed on the N-type epitaxial layer at the bottom of the trench; A dielectric layer located in the trench, wherein the dielectric layer does not completely fill the trench; A gate dielectric layer formed on the surface of the remaining trench, and a gate polysilicon layer filling the remaining trench; A source-end heavily doped region formed above the P-type body region; A second P pillar is formed on the N-type epitaxial layer below the P-type body region, and there is a lateral spacing between the first P pillar and the second P pillar; An interlayer dielectric layer is formed on the epitaxial layer, a contact hole for leading out the source-end heavily doped region is formed on the interlayer dielectric layer, a heavily doped region is formed on the body region below the contact hole, and a metal electrode is formed in the contact hole.

2. The superjunction trench-gate MOSFET device according to claim 1, characterized in that: The depth of the second P pillar matches the depth of the trench: the depths of the two tend to be the same or the depth difference between the two is within a preset range.

3. The superjunction trench-gate MOSFET device according to claim 1, characterized in that: The energy of ion implantation for the first P pillar and the second P pillar is 400 - 3400 KeV, and the dose range of ion implantation is 1.0e12 - 1.0e13 (cm^-2).

4. The superjunction trench-gate MOSFET device according to claim 1, wherein: The first P pillar is led out by connecting in the width direction to the P-type body region.

5. The manufacturing method of the superjunction trench gate MOSFET device according to any one of claims 1 to 4, characterized in that, At least including: Step 1: Provide an N-type substrate, form an N-type epitaxial layer on the substrate, form a P-type body region on the surface of the epitaxial layer, and then perform thermal diffusion propulsion on the body region; Step 2: Form a trench on top of the body region, the trench extends downward from the upper surface of the N-type epitaxial layer through the body region, and form a first P pillar on the N-type epitaxial layer at the bottom of the trench; Step 3: Form a dielectric layer located in the trench, wherein the dielectric layer does not completely fill the trench; Step 4: Form a gate dielectric layer on the surface of the remaining trench, and then form a gate polysilicon layer filling the remaining trench; Step 5: Form a source-end heavily doped region above the P-type body region, and then form a second P pillar on the N-type epitaxial layer below the P-type body region, and there is a lateral spacing between the first P pillar and the second P pillar; Step 6: Form an interlayer dielectric layer on the epitaxial layer, form a contact hole for leading out the source-end heavily doped region on the interlayer dielectric layer, perform heavy doping implantation on the body region below the contact hole, form a heavily doped region through thermal diffusion, and at the same time activate the impurity implantation of the heavy doping implantation, and then form a metal electrode filling the contact hole.

6. The manufacturing method of the superjunction trench-gate MOSFET device according to claim 5, characterized in that: The method for forming the P-type body region in Step 1 includes: forming a first photoresist layer covering the N-type epitaxial layer; performing photolithography to open the first photoresist layer to define the formation region of the P-type body region; forming the P-type body region by ion implantation; removing the first photoresist layer.

7. The manufacturing method of the superjunction trench-gate MOSFET device according to claim 5, characterized in that: The method for forming the trench in Step 2 includes: forming a second photoresist layer covering the N-type epitaxial layer; performing photolithography to open the second photoresist layer to define the formation region of the trench; forming the trench by etching.

8. The manufacturing method of the superjunction trench-gate MOSFET device according to claim 7, characterized in that: The method for forming the first P pillar in Step 2 includes: using the second photoresist layer remaining after etching to form the trench as a mask, performing ion implantation to form the first P pillar; removing the second photoresist layer.

9. The manufacturing method of the superjunction trench-gate MOSFET device according to claim 5, characterized in that: The method for forming the dielectric layer in Step 3 includes: forming the dielectric layer covering the N-type epitaxial layer by thermal oxidation or deposition; Grinding the dielectric layer to the N-type epitaxial layer; etching the dielectric layer in the trench to the required height.

10. The manufacturing method of the superjunction trench-gate MOSFET device according to claim 5, characterized in that: The method for forming the second P pillar in Step 5 includes: forming a third photoresist layer covering the N-type epitaxial layer; performing photolithography to open the third photoresist layer to define the formation region of the second P pillar; forming the second P pillar by ion implantation; removing the third photoresist layer.

11. The manufacturing method of the superjunction trench-gate MOSFET device according to claim 5, characterized in that: The depth of the second P pillar in Step 5 matches the depth of the trench: the depths of the two tend to be the same or the depth difference between the two is within a preset range.

12. The manufacturing method of the superjunction trench-gate MOSFET device according to claim 5, characterized in that: The energy of ion implantation for the first P pillar and the second P pillar is 400 - 3400 KeV, and the ion implantation dose range is 1.0e12 - 1.0e13 (cm^-2).

13. The manufacturing method of the superjunction trench-gate MOSFET device according to claim 1, characterized in that: The first P pillar is led out by connecting the P-type body region in the width direction.

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