Crystal oscillator deviation estimation method and device, electronic equipment and storage medium
The proposed method addresses the inefficiencies in A-PHY clock synchronization by using Early-Late gate detection and loop filtering to estimate crystal oscillator deviations, reducing latency and improving precision while conserving bandwidth.
Patent Information
- Application Number
- CN202510469552.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-15
- Publication Date
- 2025-07-15
AI Technical Summary
The crystal oscillator deviation estimation method in the existing A-PHY protocol has problems such as large estimation delay, poor accuracy and occupancy of effective bandwidth.
The crystal oscillator deviation estimation calculation method based on Bang-Bang CDR is used to perform the received signal sooner or later gate detection, loop filtering and frequency deviation detection, and the crystal oscillator deviation value is calculated using the slope of the frequency integrator output signal of the loop filter, thereby avoiding the process of sending CFS frames.
It realizes the accuracy and efficiency of crystal oscillator deviation estimation without increasing delay and occupancy of additional bandwidth, and solves the problems of large delay, poor accuracy and bandwidth occupancy in the existing methods.
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Figure CN120321078A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communication technologies, and in particular, to a crystal oscillator deviation estimation method, apparatus, electronic device, and storage medium. Background Art
[0002] A-PHY is a high-bandwidth, long-distance serial transmission technology designed specifically for automotive applications. The A-PHY technology is particularly suitable for the connection between cameras and displays, as well as data transmission from sensors to electronic control units (ECUs). Due to the possible influence of factors such as large crystal oscillator deviations and temperature variations in the automotive environment, accurate clock recovery is the key to ensuring data integrity and transmission reliability. Among them, the crystal oscillator deviation refers to the frequency deviation caused by the difference in crystal oscillator accuracy between the sending end and the receiving end.
[0003] In the existing A-PHY protocol, in order to achieve timing synchronization between the Source end (i.e., the sending end) and the Sink end (i.e., the receiving end), CFS (Clock and Frame Synchronization) frames are introduced. Due to the deviation of the crystal oscillators between the Source end and the Sink end, it is necessary to estimate and compensate the crystal oscillator deviation through CFS frames. A commonly used crystal oscillator deviation estimation method in A-PHY is that the sending end sends two CFS frames to the receiving end, and the receiving end obtains the time stamp of the sending end by parsing the CFS frames, and calculates the crystal oscillator deviation by comparing it with the time stamp of the receiving end.
[0004] The above crystal oscillator deviation estimation method has the following defects: 1. It is necessary to send at least two CFS frames, resulting in a large delay in frequency offset estimation; 2. The processing delays of the sending end and the receiving end are affected by their respective crystal oscillators, resulting in poor frequency offset estimation accuracy; 3. Sending CFS frames will occupy the effective bandwidth. Summary of the Invention
[0005] The purpose of the present invention is to provide a crystal oscillator deviation estimation method, apparatus, electronic device, and storage medium to alleviate the problems of large estimation delay, poor accuracy, and occupation of effective bandwidth existing in the existing crystal oscillator deviation estimation method.
[0006] In a first aspect, the present invention provides a crystal oscillator deviation estimation method, including:
[0007] Performing early-late gate detection on a group of received signals to obtain an error signal;
[0008] Filtering the error signal by using a loop filter to obtain a target error signal, where the target error signal is used to represent the cumulative phase error correction amount;
[0009] Determining a target crystal oscillator deviation value according to the slope of the target error signal changing with time.
[0010] In an alternative embodiment, performing an early-late gate detection on a set of received signals to obtain an error signal, including:
[0011] Obtaining a set of received signals;
[0012] Performing data clock sampling and edge clock sampling on the received signals to obtain a data clock sampling decision signal and an edge clock sampling decision signal;
[0013] Inputting the data clock sampling decision signal and the edge clock sampling decision signal into an early-late gate detector to obtain an error signal output by the early-late gate detector.
[0014] In an alternative embodiment, filtering the error signal by using a loop filter to obtain a target error signal, including:
[0015] Inputting the error signal into the loop filter, and determining an output signal of a frequency integrator in the loop filter as the target error signal.
[0016] In an alternative embodiment, determining a target crystal oscillator deviation value according to a slope of the target error signal varying with time, including:
[0017] Calculating a slope of the target error signal varying with time to obtain a target slope;
[0018] Determining a target crystal oscillator deviation value corresponding to the target slope according to a preset correspondence between the slope and the crystal oscillator deviation value.
[0019] In an alternative embodiment, calculating a slope of the target error signal varying with time to obtain a target slope, including:
[0020] Calculating a slope of the target error signal varying with time by using the least squares method to obtain a target slope.
[0021] In an alternative embodiment, the slope calculation formula corresponding to the least squares method is as follows:
[0022]
[0023] where k represents the slope, N represents the number of sampling points, x(n) represents a time output signal, x(n) = n, n represents the serial number of the sampling point, and y(n) represents the target error signal.
[0024] In an alternative embodiment, the loop filter includes a two-stage FIR filter.
[0025] In a second aspect, the present invention provides a crystal oscillator deviation estimation device, including:
[0026] An early-late gate detection module for performing early-late gate detection on a set of received signals to obtain an error signal;
[0027] A loop filtering module for filtering the error signal by using a loop filter to obtain a target error signal, where the target error signal is used to represent the cumulative phase error correction amount;
[0028] A frequency offset detection module for determining a target crystal oscillator deviation value according to the slope of the target error signal changing with time.
[0029] In a third aspect, the present invention provides an electronic device including a memory and a processor. A computer program that can run on the processor is stored in the memory. When the processor executes the computer program, the crystal oscillator deviation estimation method according to any one of the foregoing embodiments is implemented.
[0030] In a fourth aspect, the present invention provides a computer-readable storage medium with a computer program stored thereon. When the computer program is run by a processor, the crystal oscillator deviation estimation method according to any one of the foregoing embodiments is executed.
[0031] The crystal oscillator deviation estimation method, device, electronic device and storage medium provided by the present invention, when performing crystal oscillator deviation estimation, first perform early-late gate detection on a set of acquired received signals to obtain an error signal; then filter the error signal by using a loop filter to obtain a target error signal, where the target error signal is used to represent the cumulative phase error correction amount; and then determine the target crystal oscillator deviation value according to the slope of the target error signal changing with time. In this way, the receiving end only needs to perform processing such as early-late gate detection and loop filtering on normal received signals to achieve crystal oscillator deviation estimation, without introducing CFS frames, thus solving the problems of large estimation delay, poor accuracy and occupied effective bandwidth caused by CFS frames. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0033] Figure 1 It is a schematic flowchart of a crystal oscillator deviation estimation method provided by an embodiment of the present invention;
[0034] Figure 2 It is a schematic diagram of the implementation principle of a crystal oscillator deviation estimation method provided by an embodiment of the present invention;
[0035] Figure 3A circuit implementation method for slope calculation provided by an embodiment of the present invention;
[0036] Figure 4 A schematic structural diagram of a crystal oscillator deviation estimation device provided by an embodiment of the present invention;
[0037] Figure 5 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners
[0038] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
[0039] Bang-Bang Clock and Data Recovery (referred to as Bang-Bang CDR) is a technique for recovering the clock of a data signal, especially applicable to high-speed serial links. The working mode of its control logic is as follows: once a phase error is detected, it will immediately perform an adjustment with the maximum amplitude (i.e., the "bang-bang" action). In view of the problems of large estimation delay, poor accuracy, and occupation of effective bandwidth in the existing crystal oscillator deviation estimation methods for APHY chips, the embodiments of the present invention provide a crystal oscillator deviation estimation method, device, electronic device, and storage medium, which adopt a crystal oscillator deviation estimation algorithm based on Bang-Bang CDR and can effectively identify the crystal oscillator deviation without introducing CFS frames, solving the defects of the existing crystal oscillator deviation estimation methods.
[0040] It should be noted that the crystal oscillator deviation estimation algorithm based on Bang-Bang CDR provided by the embodiments of the present invention is not limited to the A-PHY protocol and is applicable to any estimator using Bang-Bang CDR.
[0041] For the convenience of understanding this embodiment, first, a crystal oscillator deviation estimation method disclosed in the embodiments of the present invention will be introduced in detail.
[0042] The embodiments of the present invention provide a crystal oscillator deviation estimation method, which can be executed by an electronic device disposed at the receiving end. Refer to Figure 1 The flowchart of a crystal oscillator deviation estimation method shown, and this method mainly includes the following steps S110 to step S130:
[0043] Step S110, perform early-late gate detection on a group of received signals to obtain an error signal.
[0044] Early-Late gate detection, also known as Early-Late detection, is a technique used in CDR. This technique helps the receiving end accurately recover the original data stream and clock information from the received signal. It determines the optimal sampling moment in the received signal by comparing the data samples around the sampling points, thereby ensuring that the data can be correctly decoded. The Early-Late detector estimates the phase error by comparing the "early", "accurate", and "late" sample values of the received data symbols and generates an error signal m(n), which reflects the offset of the current sampling moment relative to the ideal sampling point.
[0045] In some possible embodiments, the above step S110 may include: obtaining a set of received signals; performing data clock sampling and edge clock sampling on the received signals to obtain a data clock sampling decision signal and an edge clock sampling decision signal; inputting the data clock sampling decision signal and the edge clock sampling decision signal into an Early-Late gate detector to obtain an error signal output by the Early-Late gate detector.
[0046] The above data clock sampling decision signal can be obtained by sampling the received signal using a clock synchronized with the data rate; the edge clock sampling decision signal can be obtained by sampling the received signal using the rising edge or falling edge of the clock signal. The number of sampling points can be set according to actual needs and is not limited here. For example, the number of sampling points is 2048 or 4096, etc.
[0047] Step S120, filtering the error signal using a loop filter to obtain a target error signal, which is used to characterize the accumulated phase error correction amount.
[0048] The main function of the loop filter is to smooth or filter the error signal from the Early-Late gate detector. The loop filter can output the PI (Phase Interpolator) phase. The loop filter can include a first-stage integrator and a second-stage integrator. The second-stage integrator can be a frequency integrator, and the output of the second-stage integrator can reflect the accumulated phase error correction amount. Based on this, in some possible embodiments, step S120 may include: inputting the error signal into the loop filter and determining the output signal of the frequency integrator in the loop filter as the target error signal.
[0049] The above loop filter can adopt a two-stage FIR (Finite Impulse Response) filter or a higher-order FIR filter. The two-stage FIR filter can better suppress the high-frequency noise components in the input signal, has better transient response characteristics, can achieve an accurate linear phase response, is easy to implement, and has stability.
[0050] Step S130: Determine the target crystal oscillator deviation value according to the slope of the target error signal changing with time.
[0051] There is a one-to-one correspondence between the slope of the error signal changing with time and the crystal oscillator deviation value. Based on this, the above step S130 may include: calculating the slope of the target error signal changing with time to obtain the target slope; determining the target crystal oscillator deviation value corresponding to the target slope according to the preset correspondence between the slope and the crystal oscillator deviation value.
[0052] Optionally, the least squares method can be used to calculate the slope of the target error signal changing with time to obtain the target slope. It should be noted that the embodiment of the present invention does not limit the calculation method of the slope. In other embodiments, other calculation methods for the slope of discrete signals changing with time can also be used, such as the moving average method, Savitzky-Golay filter, polynomial regression, or autoregressive model, etc.
[0053] Furthermore, the slope calculation formula corresponding to the least squares method can be as follows:
[0054]
[0055] Where k represents the slope, N represents the number of sampling points, x(n) represents the time output signal, x(n) = n, n represents the serial number of the sampling point, and y(n) represents the target error signal.
[0056] The correspondence between the slope and the crystal oscillator deviation value can be in the form of a table, so that the target crystal oscillator deviation value corresponding to the target slope can be obtained by looking up the table.
[0057] In the crystal oscillator deviation estimation method provided by the embodiment of the present invention, when performing crystal oscillator deviation estimation, a group of received signals obtained are first subjected to early-late gate detection to obtain an error signal; then the error signal is filtered by a loop filter to obtain a target error signal, and the target error signal is used to represent the accumulated phase error correction amount; furthermore, the target crystal oscillator deviation value is determined according to the slope of the target error signal changing with time. In this way, the receiving end only needs to perform processing such as early-late gate detection and loop filtering on normal received signals to achieve crystal oscillator deviation estimation, without introducing CFS frames, thus solving the problems of large estimation delay, poor accuracy, and occupation of the effective bandwidth caused by CFS frames.
[0058] For ease of understanding, the above crystal oscillator deviation estimation method will be introduced in detail below.
[0059] The basic idea of the crystal oscillator deviation estimation algorithm based on Bang-Bang CDR provided by the embodiments of the present invention is as follows: while estimating the optimal sampling phase according to the Bang-Bang CDR algorithm at the receiving end, the result of the frequency integrator in the CDR loop filter is used to calculate the slope of the change of the result of the frequency integrator over time, and the crystal oscillator deviation is obtained by using the conversion relationship between the slope and the frequency offset.
[0060] The crystal oscillator deviation estimation algorithm based on Bang-Bang CDR includes three parts: Early-Late detection, loop filtering, and frequency offset detection. The specific implementation can refer to Figure 2 as shown.
[0061] 1. Early-Late detection:
[0062] As Figure 2 shown, the data clock sampling decision input is d(n), and the edge clock sampling decision input is e(n). Then, the Early-Late detection output (i.e., the output of the early-late gate detector) m(n) can be determined in the following way: check whether d(n - 1) and d(n) are different; if they are different, then enter the next-level conditional judgment, otherwise, m(n) = 0; in the case where d(n - 1) and d(n) are different, if e(n) = d(n - 1), then m(n) = 1, otherwise, m(n) = -1.
[0063] The corresponding pseudo-code is as follows:
[0064]
[0065] 2. Loop filtering:
[0066] As Figure 2 shown, the output m(n) of the early-late gate detector is input to the loop filter. m(n) becomes q(n) after passing through the first-stage integrator and then becomes y(n) after passing through the second-stage integrator. The loop filter adopts a two-stage FIR filter, including three filter coefficients cfg_cdr1, cfg_cdr2, and cfg_cdr3, and finally outputs the PI phase.
[0067] 3. Frequency offset detection:
[0068] The least squares method is used to calculate the slope of the curve of the output of the second-stage integrator (frequency integrator) of the loop filter changing with time. The specific implementation can refer to Figure 3 as shown. As Figure 2As shown, the output of the frequency integrator is y(n), and the time output is x(n). The slope k is calculated from x(n) and y(n) by a frequency calculator, and then the frequency offset is obtained through a LUT (Look-Up Table). Among them, after inputting 1 into the integrator, the output of the integrator is x(n), and its values are 1, 2, 3, 4, ···. As Figure 3 shown, the slope k corresponding to the least squares method is:[[]]
[0069]
[0070] Corresponding to the above crystal oscillator deviation estimation method, an embodiment of the present invention provides a crystal oscillator deviation estimation device. Refer to Figure 4 the structural schematic diagram of a crystal oscillator deviation estimation device shown. The device includes:[[]]
[0071] An early-late gate detection module 401, configured to perform early-late gate detection on a group of received signals to obtain an error signal;
[0072] A loop filter module 402, configured to filter the error signal by using a loop filter to obtain a target error signal, where the target error signal is used to represent the accumulated phase error correction amount;
[0073] A frequency offset detection module 403, configured to determine a target crystal oscillator deviation value according to the slope of the target error signal changing with time.
[0074] For the crystal oscillator deviation estimation device provided by the embodiment of the present invention, when performing crystal oscillator deviation estimation, first perform early-late gate detection on a group of acquired received signals to obtain an error signal; then filter the error signal by using a loop filter to obtain a target error signal, where the target error signal is used to represent the accumulated phase error correction amount; and further determine the target crystal oscillator deviation value according to the slope of the target error signal changing with time. In this way, the receiving end only needs to perform processing such as early-late gate detection and loop filtering on normal received signals to achieve crystal oscillator deviation estimation, without introducing CFS frames, thus solving the problems of large estimation delay, poor accuracy, and occupation of the effective bandwidth caused by CFS frames.
[0075] Further, the above-mentioned early-late gate detection module 401 is specifically configured to: acquire a group of received signals; perform data clock sampling and edge clock sampling on the received signals to obtain a data clock sampling decision signal and an edge clock sampling decision signal; input the data clock sampling decision signal and the edge clock sampling decision signal into an early-late gate detector to obtain an error signal output by the early-late gate detector.
[0076] Further, the above-mentioned loop filter module 402 is specifically configured to: input the error signal into a loop filter, and determine the output signal of the frequency integrator in the loop filter as the target error signal.
[0077] Further, the above frequency offset detection module 403 is specifically configured to: calculate the slope of the target error signal changing with time to obtain a target slope; and determine a target crystal oscillator deviation value corresponding to the target slope according to a preset correspondence between the slope and the crystal oscillator deviation value.
[0078] Further, the above frequency offset detection module 403 is further configured to: calculate the slope of the target error signal changing with time by using the least squares method to obtain a target slope.
[0079] Further, the slope calculation formula corresponding to the above least squares method is as follows:
[0080]
[0081] where k represents the slope, N represents the number of sampling points, x(n) represents the time output signal, x(n) = n, n represents the serial number of the sampling point, and y(n) represents the target error signal.
[0082] Further, the above loop filter includes a two - order FIR filter.
[0083] The principle of implementation and the technical effects generated by the crystal oscillator deviation estimation device provided in this embodiment are the same as those in the foregoing crystal oscillator deviation estimation method embodiment. For a brief description, for parts not mentioned in the crystal oscillator deviation estimation device embodiment, reference may be made to the corresponding content in the foregoing crystal oscillator deviation estimation method embodiment.
[0084] As Figure 5 shown, an electronic device 500 provided in an embodiment of the present invention includes: a processor 501, a memory 502, and a bus. The memory 502 stores a computer program that can run on the processor 501. When the electronic device 500 runs, communication between the processor 501 and the memory 502 is through the bus, and the processor 501 executes the computer program to implement the above crystal oscillator deviation estimation method.
[0085] Specifically, the above memory 502 and processor 501 can be general - purpose memory and processor, and no specific limitation is made here.
[0086] An embodiment of the present invention also provides a computer - readable storage medium. A computer program is stored on the computer - readable storage medium, and when the computer program is run by a processor, it executes the crystal oscillator deviation estimation method in the foregoing method embodiment. The computer - readable storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read - only memory (ROM), a RAM, a magnetic disk, or an optical disc that can store program codes.
[0087] As used herein, the term "and / or" is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.
[0088] In all the examples shown and described herein, any specific value should be construed as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values.
[0089] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of apparatuses, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.
[0090] In several embodiments provided in the present application, it should be understood that the disclosed apparatuses and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of modules is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the couplings or direct couplings or communication connections shown or discussed with each other can be through some communication interfaces, and the indirect couplings or communication connections of apparatuses or modules can be in electrical, mechanical, or other forms.
[0091] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0092] In addition, in each embodiment of the present invention, each functional module may be integrated into one processing module, may exist separately as individual physical modules, or two or more modules may be integrated into one module.
[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A crystal oscillator deviation estimation method, characterized in that, Including: Performing early-late gate detection on a group of acquired received signals to obtain an error signal; Filtering the error signal by using a loop filter to obtain a target error signal, where the target error signal is used to characterize the accumulated phase error correction amount; Determining a target crystal oscillator deviation value according to the slope of the change of the target error signal over time.
2. The method according to claim 1, wherein The performing early-late gate detection on a group of acquired received signals to obtain an error signal includes: Acquiring a group of received signals; Performing data clock sampling and edge clock sampling on the received signals to obtain a data clock sampling decision signal and an edge clock sampling decision signal; Inputting the data clock sampling decision signal and the edge clock sampling decision signal into an early-late gate detector to obtain the error signal output by the early-late gate detector.
3. The method according to claim 1, wherein The filtering the error signal by using a loop filter to obtain a target error signal includes: Inputting the error signal into a loop filter, and determining the output signal of the frequency integrator in the loop filter as the target error signal.
4. The method according to claim 1, wherein The determining a target crystal oscillator deviation value according to the slope of the change of the target error signal over time includes: Calculating the slope of the change of the target error signal over time to obtain a target slope; Determining a target crystal oscillator deviation value corresponding to the target slope according to a preset correspondence between the slope and the crystal oscillator deviation value.
5. The method according to claim 4, wherein The calculating the slope of the change of the target error signal over time to obtain a target slope includes: Calculating the slope of the change of the target error signal over time by using the least squares method to obtain the target slope.
6. The method according to claim 5, wherein The slope calculation formula corresponding to the least squares method is as follows: where k represents the slope, N represents the number of sampling points, x(n) represents the time output signal, x(n)=n, n represents the serial number of the sampling point, and y(n) represents the target error signal.
7. The method according to any one of claims 1-6, characterized in that, The loop filter includes a two-stage FIR filter.
8. A crystal oscillator deviation estimation device, characterized in that, Including: An early-late gate detection module, configured to perform early-late gate detection on a group of received signals to obtain an error signal; A loop filtering module, configured to filter the error signal by using a loop filter to obtain a target error signal, where the target error signal is used to characterize the accumulated phase error correction amount; A frequency offset detection module, configured to determine a target crystal oscillator deviation value according to the slope of the change of the target error signal over time.
9. An electronic device, comprising a memory and a processor, wherein a computer program that can run on the processor is stored in the memory, and is characterized in that When the processor executes the computer program, the crystal oscillator deviation estimation method according to any one of claims 1-7 is implemented.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is run by the processor, the crystal oscillator deviation estimation method according to any one of claims 1-7 is executed.